性能超过晶体的CMOS时钟

Silicone Laboratories 公司开 发成功一种通信交换机端口卡使用的时钟倍频器,通常与其他时钟器件一起构成完全的CMOS设计。 数字锁相环(PLL)是倍频器的核心,它采用与该公司的时钟和恢复电路同样的基本设计,获得小于0.7ps的抖动。倍频器可提供达到622MHz的四组输出频率。为了构成一种可靠的时钟源,端口卡倍频器使用双时钟源,因而,当一个时钟失效时,另一个时钟保持卡的运行。但是,这些时钟源的相位通常不同步。PLL的数字特性有可能从一个时钟源变换至另一个时钟源而不会影响输出信号。如果采用完全的模拟倍频器,当PLL试图…     

基于FPGA的数字基带传输位同步恢复

提出了一种基于全数字锁相环提取数字基带传输位同步时钟的设计方案,该方案采用环路鉴相器产生误差信号控制本地位同步电路的添加/扣除门在时钟输出的脉冲序列中附加或扣除1个或几个脉冲实现同步。给出了该方案的整体电路,并经VHDL程序设计,在MaxplusⅡ环境下做了时序仿真,从仿真结果分析了设计方法可实现数字基带传输位同步时钟的提取。     

全数字接收机中一种载波相位恢复的新方法

全数字接收机是在最近几年内提出的一个新的概念,它要求解调用的本地参考载波和采样时钟都振荡于固定的频率,不需要进行反馈控制,其他一些工作:载波相位误差和时钟定时误差的消除、信号的判定等全部由采样后的数字信号处理器完成。载波相位恢复问题和时钟同步问题是目前关于全数字接收机研究中的两个最主要的问题。本文仅讨论载波相位恢复问题。在本文中研究了载波相位估计算法中估计e~(jθ)和估计θ的差异,从理论上证明了估计e~(jθ)比估计θ有更好的统计特性,并且给出了一种估计e~(jθ)的方法,此方法有二个突出的优点:(1)它可以消除载波相位恢复过程中的相位区间跳变。(2)相位估计器的结构简单,它是全线性的,易于实现。利用16-QAM信号进行计算机仿真证实了此算法的可行性。     

一种基于软件无线电技术的中频数字接收机的实现

本文主要讨论了一种基于软件无线电技术的中频数字接收机的实现.在系统具体实现中,提出了利用信号的镜像频谱来实现信号数字正交解调的新方法,从而使得数字正交解调的关键部分--数字NCO只需用同采样时钟一样的参考时钟就可以对中频信号实现正交解调.实验结果表明,系统性能优良,可以满足实际需要.     

集成电路

可利用GPS信号进行同步的时钟ICAD9548内置一个数字PLL,能对1ppsGPS信号进行上变频,同时可将与外部参考相关的输入时间抖动或相位噪声降低至300fs。时钟分配部分提供四     

突发模式PSK信号的联合载波位时钟恢复算法

快速载波和位时钟恢复是突发模式传送系统的一个关键因素。本文提出了适用于突发模式PSK信号捕获阶段的一种快速联合载波位时钟恢复算法。算法基于一个特定图案的前导字,采用前向结构直接、同时估计各个同步参数。可估计的载波频差范围是大的,约为符号率的,并且算法所需的计算负载非常低,适合数字硬件实现。仿真结果验证了算法的可行性和有效性。     

采用高速A／D和FPGA的视频角翠码器

基于高速A/D和FPGA,针对PAL制黑白全电视信号的特点而提出来的视频解码器的设计方案,基于采样时钟的高精度定时器与选通脉冲发生器,利用选通脉冲实现对全电视信号中特定同步信息的提取,可以产生各种同步时序信号,实现对全电视信号的解码。     

CDMA2000基站GPS/GLONASS同步的可编程逻辑实现

给出了一种用于第三代移动通信系统(3G)CDMA2000基站的时钟同步方案。由一个双星接收卡接收GPS/GLONASS标准秒信号作为整个时钟同步系统的参考,分两级锁相环实现。该设计保证了输出时钟的长期稳定性和短期稳定性,满足协议所规定的同步精度。详细介绍了数字鉴相器、2s产生电路、相差检测及控制电路的电路设计和有关仿真结果。     

N×N MIMO基站与外部时序参考同步

针对电信基站,系统架构师需要花费相当多的精力和时间设计高性能时钟和正弦波振荡电路.单芯片收发器虽然整合了许多此类信号发生器,但仍然需要一个参考时钟.一个网络中的各基站一般相互同步,因此该参考时钟必须与一个全网络时序信号保持时序一致.本文讨论一个高性能时钟发生器如何配合一个或多个集成收发器工作,以便简化整体设计、降低复杂度和成本,同时实现出色的系统接收和发射性能.即使基站长时间丢失时序参考信号,网络中的所有其他基站仍能保持同步.     

一种基于CORDIC算法的高速高精度数字鉴相器

提出了一种基于CORDIC算法的高速、高精度数字鉴相器。该数字鉴相器根据正交解调原理测相,采用高速全流水线结构在FPGA上实现,利用CORDIC算法实现了数字下变频(DDC)和相角的计算。本方法不需要正交本振信号与参考信号严格同步,并且允许输入信号的频率与DDC的NCO频率存在一定频偏,便于工程实现。经时序仿真验证,系统工作时钟可达100 MHz,在30 dB的信噪比条件下,测相误差小于0.004 rad,样本标准差小于0.03 rad。     

GALDS: a complete framework for designing multiclock ASICs and SoCs

A Globally Asynchronous, Locally Synchronous (GALS) system with dynamic voltage and frequency scaling can use the slowest frequency possible to accomplish a task with minimal power consumption. With the mechanism for implementing dynamic voltage scaling at each synchronous domain left up to the designer, our Globally Asynchronous, Locally Dynamic System (GALDS) provides a top-down, system-level means to maximize power reduction in an integrated circuit and facilitate system-on-a-chip (SoC) design. Our solution includes three distinct components: a novel bidirectional asynchronous FIFO to communicate between independently clocked synchronous blocks , an all-digital dynamic clock generator to quickly and glitchlessly switch between frequencies and a digitally controlled oscillator to generate the global fixed frequency clocks required by the all-digital dynamic clock generator. In addition to being capable of reducing power consumption when combined with dynamic voltage scaling, a GALDS design benefits from numerous other advantages such as simplified clock distribution, high performance operation and faster time-to-market through the modular nature of the architecture.     

Novel system clock generation from a modulated signal

This paper describes a novel technique to derive a pure-spectral system clock with a common multi-modulus divider from a frequency modulated signal. Therefore, the dividing factor is inverse frequency modulated to compensate the frequency modulation component on the divider input signal. Additionally, $\Upsigma\Updelta$ dithering is applied to the frequency divider. The technique is used for a FM-radio transmitter based on an all-digital phase-locked loop (PLL) to generate a higher-frequency clock for baseband signal processing. It can also be applied to other PLL based transmitters or receivers, especially, if only a slow PLL reference clock is available and a faster system or baseband clock is required. The main factor determining the quality of the generated clock signal is the PLL??s reference quartz oscillator as it determines the accuracy of the PLL??s RF oscillator, which limits then the accuracy of the newly generated clock. In the FM-radio transmitter, a generated ??1?MHz clock signal with 30.58?ppm frequency offset and 515?ps root mean square jitter is generated. The phase noise is determined to ?83.5?dBc/Hz at 10?kHz offset and ?70.5?dBc/Hz at 1?kHz, respectively. The signal can also be used in co-integrated or external circuits.     

A wide-range programmable frequency synthesizer based on a finite state machine filter

In this article, an FPGA-based design and implementation of a fully digital wide-range programmable frequency synthesizer based on a finite state machine filter is presented. The advantages of the proposed architecture are that, it simultaneously generates a high frequency signal from a low frequency reference signal (i.e. synthesising), and synchronising the two signals (signals have the same phase, or a constant difference) without jitter accumulation issue. The architecture is portable and can be easily implemented for various platforms, such as FPGAs and integrated circuits. The frequency synthesizer circuit can be used as a part of SERDES devices in intra/inter chip communication in system-on-chip (SoC). The proposed circuit is designed using Verilog language and synthesized for the Altera DE2-70 development board, with the Cyclone II (EP2C35F672C6) device on board. Simulation and experimental results are included; they prove the synthesizing and tracking features of the proposed architecture. The generated clock signal frequency of a range from 19.8?MHz to 440?MHz is synchronized to the input reference clock with a frequency step of 0.12?MHz.     

Quad-level bit-stream adders and multipliers with efficient FPGA implementation

Novel adder and multiplier circuits for bit-stream signal processing customised for quad-level sigma-delta modulated signals are proposed. Compared with existing sorter-based quad-level sigma-delta adders and multipliers, the proposed implementation is more resource-efficient (>76% hardware savings) and faster (>93% higher clock frequency) when realised on state-of-the-art FPGA architecture featuring six- input look-up tables.     

A "flying-adder" architecture of frequency and phase synthesis with scalability

Most of today's digital designs, from small-scale digital block designs to system-on-chip (SoC) designs, are based on "synchronous" design principle. Clock is the most important issue in these designs. Frequency and phase synthesis is closely related to the clock generation. A frequency and phase synthesis technique based on phase-locked loop is proposed in that delivers high performance, easy integration, and high stability. However, there are problems associated with this architecture, such as: 1) its highest deliverable frequency is limited by the speed of the accumulator and 2) the phase synthesis circuitry will not work well in certain ranges (dead zone) and in certain conditions (dual stability). This paper presents an improved architecture that addresses these problems. The new frequency synthesis circuitry has scalability for higher output frequency. It also has an internal node whose frequency is twice that of output signal. When duty cycle is not a concern, this signal can be used directly as clock source. The new phase synthesis circuitry is free of "dead zone" and "dual stability." The improved architecture has better performance, is simpler to implement, and is easier to understand.     

Distributed source-destination synchronization using inband clockdistribution

This paper presents a new distributed methodology for source destination synchronization for interactive teleconferencing. The method is based on a reference clock, which is synthesized from a distributed global clock. The global clock is generated by periodically exchanging inband synchronization signals with neighboring nodes. The timing jitter achieved with this method can be arbitrarily close to the jitter obtained by the centralized synchronous methods which usually use an out-of-band, hard-wired reference clock. The global clock synchronization algorithm, used in this work, guarantees frequency locking of all the network nodes to the slowest clock in the system. As a result, the slowest clock can be used as an implicit reference clock for source-destination synchronization protocols, such as synchronous frequency encoding technique (SFET) and synchronous residual time stamp (SRTS). This inband synchronization method does not require the explicit knowledge of which clock is actually the slowest in the system. Therefore, if the slowest clock fails, then another clock on a different node will be the slowest, and the nodes will use it as a reference clock for the source-destination synchronization protocol. The existing out-of-band reference clock techniques do not have this strong fault tolerant property     

A 45-Mbit/s CMOS VLSI digital phase aligner

An eight-channel, 45-Mb/s digital phase aligner (DPA) has been fabricated in 2-μm CMOS. The device receives asynchronous serial data at a known average clock frequency and unknown phase, and phase-aligns it with a local clock of the same frequency for subsequent synchronous processing. The all-digital architecture of this device minimizes the need for external components and avoids reliance on analog MOS circuitry. Tracking over a phase excursion range of ±4-bit periods has been demonstrated     

An all-digital phase-locked loop (ADPLL)-based clock recoverycircuit

A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell. These modules have been designed and verified on a 0.6-μm CMOS process. Test results are summarized as follows: 1) the proposed ADPLL can satisfy full locked bandwidth and fast acquisition within one data transition; 2) the on-chip clock generator can generate any target clock rate f_clock ; and 3) the function of nonreturn-to-zero clock recovery has a maximum f_clock/4 recovering capability with a locking range of (τ_input±τ_input/2)) where τ _input is the input period     

Performance analysis of an all-digital BPSK direct-sequencespread-spectrum IF receiver architecture

A VLSI architecture for an all-digital binary phase shift keying (BPSK) direct-sequence (DS) spread spectrum (SS) intermediate frequency (IF) receiver is presented, and an in-depth performance analysis is given. The all-digital architecture incorporates a Costas loop for carrier recovery and a delay-locked loop for clock recovery. For the pseudorandom noise (PN) acquisition block, a robust energy detection scheme is proposed to reduce false PN locks over a broad range of signal-to-noise ratios. The proposed architecture is intended for use in the 902-928 MHz unlicensed spread spectrum radio band. A 100 kbs information rate and a 12.7 Mchips/second PN code rate are assumed. The IF center frequency is 12.7 MHz and the IF sampling rate is 50.8 Msamples/second, which is the Nyquist rate for the 25.4 MHz bandwidth signal. Finite wordlength effects have been simulated to optimize the architecture, thereby minimizing the chip area, and results of the finite wordlength simulations demonstrate that the chip architecture achieves a bit error rate performance within 1 dB of theory in an additive white Gaussian noise channel     

An all-digital phase-locked loop for high-speed clock generation

An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented. The proposed ADPLL architecture uses both a digital control mechanism and a ring oscillator and, hence, can be implemented with standard cells. The ADPLL implemented in a 0.3-/spl mu/m one-poly-four-metal CMOS process can operate from 45 to 510 MHz and achieve worst case frequency acquisition in 46 reference clock cycles. The power dissipation of the ADPLL is 100 mW (at 500 MHz) with a 3.3-V power supply. From chip measurement results, the P/sub k/-P/sub k/ jitter of the output clock is <70 ps, and the root-mean-square jitter of the output clock is <22 ps. A systematic way to design the ADPLL with the specified standard cell library is also presented. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for system-on-chip applications.