基板温度对氧化锌薄膜晶体管性能的影响

以ITO玻璃为衬底,利用射频磁控溅射制备了以氧化硅为绝缘层的氧化锌薄膜晶体管。研究了氧化锌薄膜制备过程中不同的衬底温度（衬底温度分别为室温、100℃ 和200℃）对于器件性能的影响。和室温下制备的氧化锌薄膜晶体管相比,衬底温度200℃条件下制备的器件的场效应迁移率提高了94% （从1.6cm2/Vs 提高至3.11cm2/Vs）,亚阈值摆幅 从2.5V/dec 降低至1.9 V/dec 而且阈值电压漂移也从18V 减小至3V （老化电压为25V的正栅压,老化时间为1小时）。实验结果表明,衬底加热对于氧化锌薄膜晶体管的迁移率、亚阈值摆幅和偏压稳定性有明显的影响。利用原子力显微镜AFM对氧化锌薄膜的特性就行了研究,器件性能提高的原因也在文中进行了阐述。     

高性能ZnSnO∶Li/ZnSnO双有源层TFT电学性能的研究

双有源层以迁移率高、开关比高、大面积均匀性好等优点成为近年研究热点。采用射频磁控溅射方法，制备了ZnSnO∶Li/ZnSnO薄膜晶体管(TFT),对其电学特性进行了测试，并研究了器件迁移率提高的原因及其内在的微观机制。研究发现，ZTO∶Li/ZTO TFT表现出了良好的电学特性，其场效应迁移为率为13.98 cm²/(V·s),亚阈值摆幅为0.84 V/dec,开关比为1.13×10⁹。通过XPS对其薄膜进行分析发现，Li的引入导致薄膜中氧和金属结合键的浓度增加，氧空位浓度减少，从而使得TFT的迁移率增大，开关比增大，亚阈值摆幅减小。     

基于柔性PI基底的氧化物IGZO TFT器件工艺及特性研究

讨论了基于柔性PI基底上的底栅型TFT器件工艺,通过工艺优化解决了双层结构干刻速率不同造成的下切角形状。本文TFT器件是基于氧化物IGZO为有源层,栅绝缘层采用Si3N4/SiO2双层结构,采用两次补偿曝光、干刻方式消除干刻引入的下切角形状,有效解决了薄膜沉积引入的断线风险。实验结果表明,经过SEM断面观察,干刻后双层结构taper角度适合TFT器件后续沉膜条件,柔性基底上制作的TFT器件迁移率达到14.8cm2/(V·s),阈值电压Vth约0.5V,亚域值摆幅SS约0.5V/decade,TFT器件的开关比Ion/Ioff106。通过此方法制作出的器件性能良好,满足LCD、OLED或电子纸的驱动要求。     

基于In-Zn-Ti-O氧化物半导体材料的薄膜晶体管

在室温下制备了基于In-Zn-Ti-O氧化物半导体的薄膜晶体管,氧化物沟道层中In、Zn、Ti的摩尔比为49∶49∶2。所制备的器件场致迁移率达到9.8cm2/V.s,开关比大于105,亚阈值摆幅0.61V/dec。和未掺Ti器件的比较表明,掺Ti能使器件阈值正向变化,对场致迁移率也有提高作用。     

浸渍提拉法制备有机介质层铝铟锌氧薄膜晶体管

利用溶液法的浸渍提拉工艺制备了以有机聚甲基丙烯酸甲酯(PMMA)为介质层、非晶铝铟锌氧化物(a-AIZO)为沟道层的顶栅共面结构薄膜晶体管(TFT),研究了沟道层退火温度对TFT性能的影响机理。结果表明:较低退火温度(如300和350℃)下处理的沟道层中存在未彻底分解的金属氢氧化物,其以缺陷态形式存在于TFT沟道层内或沟道层/介质层界面处,对导电沟道中电子进行捕获或散射,劣化TFT的迁移率、电流开关比以及亚阈值摆幅。综合来看,退火温度高于400℃下制备的a-AIZO适用于TFT器件的沟道层,相应的器件呈现出较高的迁移率(大于20cm2/(V·s))、较低的亚阈值摆幅(小于0.5V/decade)以及高于104的电流开关比。     

埋氧离子注入对P型部分耗尽SOI电学与低频噪声的影响

针对抗辐照SOI PMOS器件的直流特性与低频噪声特性展开试验与理论研究,分析离子注入工艺对PMOS器件电学性能的影响,并预测其稳定性的变化。首先,对离子注入前后PMOS器件的阈值电压、迁移率和亚阈摆幅进行提取。测量结果表明:埋氧化层离子注入后,器件背栅阈值电压由-43.39 V变为-39.2 V,空穴有效迁移率由127.37 cm2/Vs降低为80.45 cm2/Vs,亚阈摆幅由1.35 V/dec增长为1.69 V/dec;结合背栅阈值电压与亚阈摆幅的变化,提取得到埋氧化层内电子陷阱与背栅界面态数量的变化。随后,分析器件沟道电流噪声功率谱密度随频率、沟道电流的变化,提取γ因子与平带电压噪声功率谱密度,由此计算得到背栅界面附近的缺陷态密度。基于电荷隧穿机制,提取离子注入前后埋氧化层内陷阱态随空间分布的变化。最后,基于迁移率随机涨落机制,提取得到离子注入前后PMOS器件的平均霍格因子由6.19×10-5增长为2.07×10-2,这表明离子注入后器件背栅界面本征电性能与应力稳定性将变差。     

铁电负电容场效应晶体管器件的研究

铁电负电容场效应晶体管作为一种新型半导体器件,利用铁电材料的负电容效应可使晶体管的亚阈值摆幅突破理论极限值60 mV/dec,是未来低功耗晶体管领域最具有前途的器件之一。该文研究并建立了铁电负电容场效应晶体管的器件模型,采用Matlab软件对负电容场效应晶体管的器件特性进行了研究分析,获得了亚阈值摆幅为33.917 6 mV/dec的负电容场效应晶体管的器件结构,探究了铁电层厚度、等效栅氧化层厚度及不同铁电材料对负电容场效应晶体管亚阈值摆幅的影响。     

有源层厚度对氧化铟镓锌薄膜晶体管性能的影响

使用磁控溅射法制备了IGZO-TFT,研究有源层厚度对其电学性能的影响。实验结果表明,器件的阈值电压和开关比会随着有源层厚度的增大而减小,而器件的亚阈值摆幅和饱和迁移率则会随有源层厚度的增大而增大。此外,还研究了有源层厚度对器件偏压稳定性的影响。有源层厚度越大的器件,其阈值电压漂移也会越大。这主要与半导体层中所增加的缺陷态密度有关。     

基于FET结构的MoS2器件的研究进展

对带隙可调的二维层状半导体二硫化钼(MoS2)的材料特性以及基于MoS2薄膜的器件性能和应用进行了简单阐述,重点分析了多种MoS2场效应晶体管(FET)的结构特点,并对MoS2 FET的制备工艺、电学性能(载流子迁移率、电流开关比、亚阈值摆幅等)以及栅极介质层材料对器件性能的影响等进行了综述.在此基础上进一步总结了近年...     

质子辐照对AlGaN/GaN HEMT亚阈值摆幅特性的影响

研究了具有不同栅漏间距的AlGaN/GaN高电子迁移率晶体管(HEMT)的亚阈值摆幅特性在0.4 MeV质子辐照(质子总注量为2.16×10¹² cm^-2)后的变化规律。质子辐照前，各器件的亚阈值摆幅基本一致；质子辐照后，器件的亚阈值摆幅随着栅漏间距的减小而逐渐降低。基于辐照前后器件的电容-电压曲线和输出特性得到低场载流子输运特性，并据此分析了亚阈值摆幅的变化原因。发现与器件尺寸相关的极化散射效应是不同尺寸器件在辐照后亚阈值摆幅发生不同变化的主要原因。为AlGaN/GaN HEMT的性能优化提供了全新的视角与维度。     

不同溅射气体对a-IGZO TFT特性的影响

采用脉冲直流(Pulsed DC)方式和不同的单组份气体(Ar、O2、N2)溅射制作IGZO,研究了缺氧(Ar)、富氧(O2)、氧替代(N2)三种情形下的IGZO-TFT特性。通过AES、XRD、AFM等分析手段,考察了不同气体制备的IGZO膜以及相应靶材的成分及结构,发现不同的溅射气体对IGZO膜的成分比例和电学结构具有重要的影响。实验结果表明,Ar-IGZO TFT在退火后具有良好的特性,S值为1 V/dec,迁移率可达8.3 cm2/Vs,开关比Ion/Ioff≥105。     

IGZO thin film transistors with Al2O3 gate insulators fabricated at different temperatures

Thin film transistors (TFTs) with bottom gate and staggered electrodes using atomic layer deposited Al₂O₃ as gate insulator and radio frequency sputtered In–Ga–Zn Oxide (IGZO) as channel layer are fabricated in this work. The performances of IGZO TFTs with different deposition temperature of Al₂O₃ are investigated and compared. The experiment results show that the Al₂O₃ deposition temperature play an important role in the field effect mobility, I_on/I_off ratio, sub-threshold swing and bias stability of the devices. The TFT with a 250 °C Al₂O₃ gate insulator shows the best performance; specifically, field effect mobility of 6.3 cm²/Vs, threshold voltage of 5.1 V, I_on/I_off ratio of 4×10⁷, and sub-threshold swing of 0.56 V/dec. The 250 °C Al₂O₃ insulator based device also shows a substantially smaller threshold voltage shift of 1.5 V after a 10 V gate voltage is stressed for 1 h, while the value for the 200, 300 and 350 °C Al₂O₃ insulator based devices are 2.3, 2.6, and 1.64 V, respectively.     

Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity,short channel effects (SCEs),leakage currents,device variability and reliability etc.Nowadays,multigate structure has become the promising candidate to overcome these problems.SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs),because of its more effective gate-controlling capabilities.In this paper,our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length.Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility,electric field,electric potential,sub-threshold slope (SS),ON current (Ion),OFF current (Ioff) and Ion/Ioff ratio.The potential benefits of SOI FinFET at drain-to-source voltage,VDS =0.05 V and VDS =0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (Av),output conductance (gd),trans-conductance (gm),gate capacitance (Cgg),and cut-off frequency (fT =gm/2πCgg) with spacer region variations.     

Amorphous-silicon thin-film transistor with liquid phase depositionof silicon dioxide gate insulator

The liquid phase deposition of silicon dioxide (LPD-SiO₂) at 50°C has been successfully applied as the gate insulator for inverted, staggered amorphous silicon thin-film transistors (TFTs). The maximum field-effect mobility of the TFTs, estimated from the saturation region, was 0.53 cm²/V-s, comparable to that obtained for conventional, silicon nitride (SiN_x ) gate transistors. The threshold voltage and subthreshold swing were 6.2 V and 0.76 V/decade, respectively. Interface and bulk characteristics are as good as those obtained for silicon nitride (SiN _x) films deposited by plasma enhanced chemical vapor deposition     

Planarized copper gate hydrogenated amorphous-silicon thin-filmtransistors for AM-LCDs

We report the first fabrication of inverted-staggered back-channel-etch hydrogenated amorphous-silicon (a-Si:H) thin-film transistors (TFTs) with a planarized Cu gate electrode. The Cu gate-planarized (GP) a-Si:H TFTs, incorporating benzocyclobutene and a-SiN_x:H as a double-layer gate insulator, had a field-effect mobility of 0.75 cm²/V-s, a threshold voltage of 4.92 V, and a subthreshold swing (S) of 0.48 V/dec. These results demonstrate that the GP-TFTs can have an electrical performance comparable with the conventional TFTs without gate planarization. Thus, the gate planarization technology is suitable for application in large-area and high-resolution active-matrix liquid-crystal displays     

High-performance nonhydrogenated nickel-induced laterally crystallized P-channel poly-Si TFTs

High-performance nickel-induced laterally crystallized (NILC) p-channel poly-Si thin-film transistors (TFTs) have been fabricated without hydrogenation. Two different thickness of Ni seed layers are selected to make high-performance p-type TFTs. A very thin seed layer (e.g., 5 /spl Aring/) leads to marginally better performance in terms of transconductance (Gm) and threshold voltage (V/sub th/) than the case of a 60 /spl Aring/ Ni seed layer. However, the p-type poly-Si TFTs crystallized by the very thin Ni seeding result in more variation in both V/sub th/ and G/sub m/ from transistor to transistor. It is believed that differences in the number of laterally grown polycrystalline grains along the channel cause the variation seen between 5 /spl Aring/ NILC TFTs compared to 60-/spl Aring/ NILC TFTs. The 60 /spl Aring/ NILC nonhydrogenated TFTs show consistent high performance, i.e., typical electrical characteristics have a linear field-effect hole mobility of 156 cm/sup 2//V-S, subthreshold swing of 0.16 V/dec, V/sub th/ of -2.2 V, on-off ratio of >10/sup 8/, and off-current of <1/spl times/10/sup -14/ A//spl mu/m when V/sub d/ equals -0.1 V.     

A Site‐Specific Charge Carrier Control in Monolithic Integrated Amorphous Oxide Semiconductors and Circuits with Locally Induced Optical‐Doping Process

Amorphous oxide semiconductor (AOS) thin film transistors (TFTs) have found cutting‐edge applications in sensor technologies. To reduce manufacturing costs, sensors, analog front end, and digital signal processing circuits need to be integrated on the identical substrate. Unlike traditional silicon‐based devices, optimizations for locally controllable electrical parameters of the AOSs have rarely been investigated. Here, photoactivated combustion reduction is utilized as doping motivation for solution‐processed amorphous indium–gallium–zinc oxide (a‐IGZO) to tune their electrical performance. By controlling parameters of a‐IGZO TFTs, which can be partly doped with covering the desired area of the identical substrate, it is possible to match the particular threshold voltage for various circuits. For circuit optimization, automatic integrated circuit modeling spice is carried out to find the best match of the complementary metal–oxide semiconductor circuits. Finally, the site‐specific performance of switching TFTs, amplifiers, and ring oscillators implemented with low‐temperature solution‐processed a‐IGZO and p‐type single‐walled carbon nanotube TFTs is demonstrated. The optical‐doped a‐IGZO TFTs exhibiting a saturation mobility of >9.15 cm² V^?1 s^?1 with a locally tunable threshold voltage of ?5 – 1.5 V are realized, enabling monolithic integration of functional devices. The resultant circuits demonstrate excellent amplification of 24 dB and an oscillation frequency of 12 kHz for 7‐stage ring oscillators.     

On the intrinsic limits of pentacene field-effect transistors

Performance limits for pentacene based field-effect transistors are investigated using single- and polycrystalline devices. Whereas the charge transport in single crystalline devices is band-like with mobilities up to 10⁵ cm²/V s at low temperatures, temperature-independent or thermally activated charge transport can be observed in polycrystalline thin film transistors depending on the growth conditions. Trapping and grain boundary effects significantly influence the temperature dependence of the field-effect mobility. Furthermore, the device performance of p-channel transistors (mobility, on/off ratio, sub-threshold swing) decreases slightly with increasing trap densities. However, the formation of an electron accumulation layer (n-channel) is significantly stronger affected by trapping processes in the thin film devices. Single crystalline p-channel devices exhibit at room temperature mobilities as high as 3.2 cm²/V s, on/off-ratios exceeding 10⁹, and sub-threshold swings as low as 60 mV/decade. Slightly diminished values are obtained for transistors working as n-channel devices (2 cm²/V s, 10⁸, and 150 mV/decade).     

New selfalignment processes for amorphous silicon thin film transistors with polysilicon source and drain

New fabrication processes for selfaligned amorphous silicon TFTs are proposed. The TFTs have a polysilicon source and drain which are formed by ArF excimer laser annealing. They exhibit a field-effect mobility of 0.8 cm/sup 2//Vs, threshold voltage of 11 V, and on/off current ratio of higher than 10/sup 6/.<>     

Device architectures for improved amorphous polymer semiconductor thin-film transistors

In this letter, the performance characteristics of single-gate and dual-gate thin-film transistors (TFTs) with amorphous indenofluorene–phenanthrene copolymer semiconductor active layers are reported. Optimized single-gate devices possess mobilities up to 0.15 cm²/V-s and width-normalized contact resistance of 1275 Ωcm. These results were obtained through the combination of a recessed source/drain structure and suitable surface treatments of source/drain contact electrodes. The characteristics of dual-gate indenofluorene–phenanthrene copolymer TFTs with polymer gate insulators are also reported. This structure exhibits increased on-current, reduced threshold voltage, improved sub-threshold swing and increased on–off current ratio compared to single-gate architectures.