毫米波相控阵板级集成天线技术研究

随着毫米波雷达及通信系统的快速发展,有源相控阵天线日益成为当前研究的热门天线形式。然而,毫米波有源相控阵存在空间紧凑、结构复杂、装配繁琐等问题。本文介绍了一种可应用于毫米波相控阵的板级集成天线,并对其天线阵列、垂直过渡等关键结构的设计进行了讨论。该阵面将天线阵列、收发组件和馈电网络全部集成在一块基板上,具有结构简单易于量产的特点。文末给出了对所设计的有源阵面的暗室测试结果,结果表明该天线在毫米波雷达和通信系统中具有巨大的应用潜力。     

4.9 GHz小型化集成相控阵天线设计

设计了一种相位控制和馈电一体化的8×8相控阵天线。将多路微带线功分器和移相器芯片集成于同一片电路板作为馈电网络并压合于阵列天线背面,形成了单端口馈电的64单元集成相控阵天线。该相控阵天线整体厚度仅2.25 mm,馈电端口至天线单元之间没有任何连接电缆,具有低剖面小型化和一体化的显著优点。电磁仿真结果显示,4.9 GHz的回波损耗小于-25 dB,最大增益为22.5 dB。此外,主极化和交叉极化隔离度为30 dB,主波束可实现-58°~62°平面扫描,具有较好的交叉极化和波束宽角域连续扫描特性,可应用于5G移动通信小型基站。     

一种基于压控移相技术的低成本相扫天线

研制了一种基于铁电体压控移相技术的低成本相扫天线阵列,该天线采用空间馈电透镜型式,省去复杂的馈电网络,减少移相器/TR组件数量,能显著降低相控阵天线的制造成本。介绍了空馈铁电体透镜相控阵天线系统的组成及其特点。对透镜天线关键部件的设计作了详细阐述,给出了12列铁电体空馈透镜天线阵列的实验结果,结果表明:在X波段,研制的铁电体透镜天线阵列在10%频带内可实现天线波束±45°的电控扫描,各扫描状态的输入驻波比小于1.4。     

一种低成本星载宽角扫描相控阵天线设计

设计了一种工作于X频段的星载圆极化相控阵天线。相控阵天线单元的馈电探针与连接器进行了一体化设计,消除了焊点,提高了阵面的可靠性;同时阵列单元周围加载金属腔体结构,降低了单元间的耦合,展宽了天线波束,提高了阵列的扫描增益;阵面为全金属结构,可实现相控阵的均温性与内部热量的辐射,阵面自身具有较强的空间抗辐照能力,同时也能对相控阵内部的有源器件提供良好的辐照屏蔽。相控阵有源组件和合成网络采用瓦片架构,具有轻量化和低剖面的特点。所设计相控阵天线具有±60°宽角扫描能力和4%的工作带宽。     

SIW 耦合馈电阵列天线

提出一种新型宽带、结构紧凑的基片集成波导(SIW)背腔阵列天线的设计方法。所设计的SIW 阵列由紧密相连的背腔构成馈电网络,每个背腔上开宽缝作为辐射单元。SIW 背腔天线单元紧密排列,主要通过单元间感性耦合窗耦合馈电。SIW 背腔既是辐射单元又能实现能量分配,不需加载额外的馈电网络,因此该阵列结构十分紧凑。工作在20 GHz 频段的2×2 SIW 耦合馈电阵和4×4 SIW 耦合馈电阵已加工实现,仿真和测试结果表明所提出的SIW阵列设计方法简单、阵列结构紧凑、天线辐射性能良好。另外,本文研究了高增益大规模阵列天线的组阵方法。在2×2 SIW 耦合馈电阵的基础上,采用8×8 SIW 并联馈电网络加载天线子阵的方法设计了16×16 宽带高增益SIW 阵列天线并进行了加工测试。结果表明,采用这种组阵方法,天线阵阵元排布紧密,天线具有带宽宽、增益高、损耗低等优点。     

平面相控阵天线和差分布馈电网络设计

大型单脉冲相控天线馈电网络的接收波束存在"和差矛盾"问题,传统的解决方案需要相当复杂的馈电网络和硬件成本。因此提出一种馈电网络设计方法,在获得接收和波束、方位差波束以及俯仰差波束低副瓣电平的同时,降低大型单脉冲相控阵天线馈电网络的复杂性。用该方法设计的3 000单元二维相扫平面阵列天线馈电网络,仿真结果为:接收和波束副瓣电平<-28 d B,俯仰差波束副瓣电平<-22 d B,方位差波束副瓣电平<-22 d B,仿真结果验证了该设计方法的有效性。     

一种宽带低剖面高增益低副瓣定向平板天线北大核心CSCD

研究设计了一款低剖面、宽带、高增益、低副瓣的定向平板天线。为了实现低剖面,采用了宽带微带天线单元、馈电网络等设计,定向天线整体采用印制板;为了实现低副瓣,采用阵列天线与馈电网络的一体化设计,用多层印制板加工技术实现天线单元间不等幅度的馈电精度,尽可能减少人工装配步骤,以降低装配误差。文中对设计的低副瓣定向天线进行了加工测试。测试结果表明,所研制天线的阻抗带宽为26.1%。在阻抗带宽范围内,可以实现最大增益大于23.6 dBi、E面和H面的副瓣电平分别小于-27.4 dB和-28.3 dB、前后比小于-42.2 dB。     

一种三指形馈电的多层微带阵列天线

采用三指形微带馈电方式,设计了一种新型用于实际生产的高增益宽带小型化多层微带阵列天线,而阵列天线总厚度仅为2.5mm。该多层介质结构天线抑制了馈电网络电磁辐射,易于加工生产,增加了结构强度。测试结果表明,该阵列天线增益达到17.3d B,VSWR≤2的相对阻抗达到14%,具有良好的辐射和阻抗匹配特性,对设计宽带相控阵天线很有帮助。     

一种应用收发一体功分器设计收发馈电网络的方法

为了实现高密度的天线集成,通常会将多个天线单元紧密排列,因此需要设计连接各个单元的收发馈电网络。应用收发一体功分器级联成收发馈电网络,收发一体功分器在设计时就采用多层结构,并考虑网络层叠的影响,可以确保发射和接收互不干扰。此外,采用通孔结构,并将电阻置于底部可以降低加工难度和成本。应用该方法设计了一种收发一体双8路的馈电网络,在工作频带内,测试的反射系数小于-22 dB,隔离度高于61 dB,各个通道间的幅度一致性小于0.2 dB,相位一致性小于2.3°。该方法可缩短设计周期,提高研发效率,而且设计的馈电网络具有高隔离和低成本等优点,可用于平板阵列天线中。     

结构功能一体化相控阵天线高密度集成设计方法

提出了一种新的结构功能一体化相控阵天线的高密度集成设计方法。采用低温共烧陶瓷(LTCC)技术实现了有源相控阵天线的一体化设计,包括天线阵面、瓦式收发(TR)组件、热控装置、馈电网络的高密度集成。采用ANSYS等软件对天线的系统体系构架、总体性能评估、共形承载天线罩、天线阵面、瓦式TR组件以及系统热设计进行仿真分析并进行实物加工和测试。结果表明,该天线的等效全向辐射功率(EIRP)为23.6 dBw,噪声为3.57 dB,测试值与设计值吻合很好。     

Optimization of board-level thermomechanical reliability of high performance flip-chip package assembly

In this paper, we study board-level thermomechanical reliability of a high performance flip-chip ball grid array package assembly subjected to an accelerated thermal cycling test condition. Different control factors are considered for an optimal design towards enhancement of the thermal fatigue resistance of solder joints. These factors include solder composition, underfill, substrate size, lid thickness, stiffener ring width, test board size, soldermask opening on the substrate side, and pad size on the test board. The shape of solder joints after reflow is estimated using Surface Evolver. The optimal design is obtained using an L₁₈ orthogonal array according to the Taguchi optimization method. Importance of these control factors on the board-level thermomechanical reliability of the package is also ranked.     

数字化红外焦平面探测器光谱响应测试系统研究

由于目前没有可测试数字化红外探测器光谱响应的设备,研制了一种可将数字化红外探测器的输出转换为与模拟探测器一样形式的电路板装置,并利用原有的傅里叶光谱仪解决了无法测试数字化红外探测器光谱的问题。该方法成本低、易实现,不仅操作简单,而且测试性能稳定,因此适用于各种形式的数字化探测器。首先介绍了红外光谱响应测试系统,然后对研制的模数电路板装置的原理进行了分析,并对此电路板进行了硬件实现,接着编写了内部测试程序,最后完成了功能验证。结果表明,配有新研制模数电路板装置的红外光谱测试系统可以测试不同位宽输出的数字化面阵探测器或线列探测器的光谱数据,而且测试结果准确可靠。     

Environmental stress screening strategies for complex systems: A 3-level mixed distribution model

Environmental Stress Screening (ESS) is employed to reduce, if not eliminate, the occurrence of early field failures. In this paper, a three level ESS model is presented for a complex electronic system. Screening is performed at the component, board and system level. Components are screened for a specified duration before being assembled into printed circuit boards (PCBs). Defects introduced during the assembly of the PCBs are screened at the board level, while defects introduced during final assembly are screened at the system level. Components and connections are assumed to come from good and substandard populations and their times-to-failure distributions are modeled by mixed distributions. Mixed exponential distributions are used to model component timesto-failure and mixed Weibull distributions are used to model the times-to failure for board and system level connections. The mixed Weibull distributions are used to model wear-out characteristics at the board and system level. Optimal screen durations in the presence of wear-out are obtained by minimizing the systems life-cycle cost. ESS is shown to be a cost effective strategy when properly implemented. The optimal screening strategies are shown to be relatively robust to the system warranty period.     

小尺寸分立器件与嵌入聚合物厚膜电阻在移动电话中的应用比较

随着移动电话越来越多功能的嵌入,设计者们不得不持续地寻求节省基板面积的方法.嵌入无源器件和使用小尺寸的分立器件(02 01)是两种较为通用的解决方法.文章考察了小尺寸的分立器件与嵌入式聚合物厚膜电阻在降低成本与节省基板面积间的协调和平衡.实验中运用高产量组装和艺术板制作技术组装小离散或聚合物厚膜电阻的方案分析了三种典型的移动电话的设计,并列举了各种方案对基板尺寸和成本的影响.     

Package to board interconnection shear strength (PBISS): effect of surface finish, PWB build-up layer and chip scale package structure

The quality of the interconnection in a fine pitch, area array chip scale package (CSP) is evaluated at the system level using a new test method, the package to board interconnection shear strength (PBISS) technique. The influence of printed wiring board (PWB) sample finish, build-up layer and package structure are quantified after surface mount assembly. Clear differences were evident in the shear strength and fracture location data indicating that the PBISS method is sensitive to the presence of black pad, weak build-up layer and package stiffness. The PBISS value of the CSPs with OSP/RCC-FR4 pad/build-up layer combination were measured to be 37 /spl plusmn/ 6 MPa and 38 /spl plusmn/ 2 MPa for the two different structures investigated. The PBISS method is demonstrated to be a viable candidate technique to quantify interconnection quality at the system level due to issues such as black pad, etc. and this method can help identify weaknesses in the interconnection chain for effective assessment of supplier or product quality.     

Reduced thermal strain in flip chip assembly on organic substrateusing low CTE anisotropic conductive film

Flip chip assembly directly on organic boards offers miniaturization of package size as well as reduction in interconnection distances, resulting in a high performance and cost-competitive packaging method. This paper describes the usefulness of low cost flip-chip assembly using electroless Ni/Au bump and anisotropic conductive films on organic boards such as FR-4. As bumps for flip chip, electroless Ni/Au plating was performed as a low cost bumping method. Effect of annealing on Ni bump characteristics informed that the formation of crystalline nickel with Ni₃P precipitation above 300°C causes an increase of hardness and an increase of the intrinsic stress. As interconnection material, modified ACFs composed of nickel conductive fillers for conductive fillers, and nonconductive fillers for modification of film properties, such as coefficient of thermal expansion (CTE), were formulated for improved electrical and mechanical properties of ACF interconnection. Three ACF materials with different CTE values were prepared and bonded between Si chips and FR-4 boards for the thermal strain measurement using moire interferometry. The thermal strain of the ACF interconnection layer, induced by temperature excursion of 80°C, was decreased according to the decreasing CTEs of ACF materials. This result indicates that the thermal fatigue life of ACF flip chip assembly on organic boards, limited by the thermal expansion mismatch between the chip and the board, could be increased by low CTE ACF     

一种相控阵体制的抗干扰分析方法

从信干比角度考虑,传统的全向辐射体制系统很难实现远距离抗干扰通信,而相控阵体制的高增益、低旁瓣特征可以使系统获得一定的抗干扰能力。从信干比分析入手,引入干扰概率指标,给出了一种针对抗干扰能力的统计分析方法,并进行了仿真分析,结果表明,由于阵面规模直接决定了方向图特性,而天线阵的体积、重量、功耗、成本均随阵元数目的增多而增长,所以在总体设计时需要对阵面规模进行折中考虑。该方法已成功应用于系统硬件总体设计。     

Modified micro–macro thermo-mechanical modelling of ceramic ball grid array packages

The ceramic ball grid array (CBGA) packages are typically used for high I/O count area array assemblies. As the package size is large, the distance to neutral point is also high resulting in a large thermal deformation mismatch between the CBGA package and the printed circuit board (PCB). In order to cope with this problem, a special solder joint connection is used. As CBGA assemblies are used for high pin count assemblies, a full 3D thermo-mechanical modelling of an assembly to an FR4 board is not possible anymore. Therefore, a modified micro–macro methodology is proposed where only the critical solder joint is modelled in detail, while the other connections are replaced by equivalent connections. For several CBGA configurations, simulation results are correlated to thermal cycling test results. Finally, a parameter sensitivity study shows that the PCB properties have a significant influence on the solder joint reliability.     

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.     

Implementing ASIC/memory integration by system-on-package

A system-on-package (SOP) solution of an application specific integrated circuit (ASIC) chip integrating with an embedded data output (EDO) memory die has been realized. Both chips are assembled into a new form factor that appears as a standard plastic ball grid array (PBGA) with 90 balls and 1.27 mm ball pitch. Topically, size reduction of approximately 60% over the equivalent printed circuit board implementation is achieved. Other benefits include simplified board design and reduction in material cost. Assembly processes are expressed to indicate how this package is made. Reliability analyzes such as: pre-conditioning, temperature cycle test (TCT), and pressure cook test (PCT), are conducted