聚酰亚胺LB膜MIS结构C－V特性

本文报道了Ａｌ／ＬＢ聚酰亚胺膜／Ｐ－Ｓｉ（１００）ＭＩＳ结构的Ｃ一Ｖ特性研究结果．６７层ＬＢ膜样品Ｃ－Ｖ特性近乎理想，具有负的固定电荷密度约１０１１ｃｍ－２量级，平带时滞后小于０．３Ｖ对于ＭＩＳ隧道结，除了在－０．５—－１．５Ｖ间具有反型层箝位产生的电容峰外，在－１．５—－４Ｖ间还出现了另一电容峰值．假设在强电场下隧穿能力剧增，从而结构由隧穿限制区重新进入半导体限制区，可以解释这一峰值的出现，考虑到少子注入引入的扩散电容，正、反向扫描时电容峰值的差别可以得到解释     

立方A^4＋M^5＋2O7型化合物与新型负热膨胀材料

概述了立方Ａ＾４＋Ｍ＾５＋２Ｏ７型化合物的结构特点，讨论了ＡＶ２－ｘＰｘＯ７型（Ａ＝Ｚｒ或Ｈｆ；ｘ＝０．１～１．２）及其部分取代的Ａ＾４＋１－ｙＢ＾４＋ｙＶ２－ｘＰｘＯ７型（Ｂ＝Ｔｉ，Ｃｅ，Ｔｈ，Ｕ，Ｍｏ，Ｐｔ，Ｐｂ，Ｓｎ，Ｇｅ或Ｓｉ；ｙ＝０．１～０．４）和Ａ＾４＋１－ｙＣ＾１＋ｙＤ＾３＋ｙＶ２－ｘＰｘＯ７型（Ｃ为碱金属元素，Ｄ为稀土金属元素）材料的负热膨胀性能。     

高性能2.5Gb／s用的DFB—LD／EA单片集成器件

报导了采用全ＭＯＣＶＤ生长的１．５５μｍ的单片集成ＤＦＢ＝ＬＤ／ＥＡ组件的 在ＤＷＤＭ系统上的传输测试结果，出纤功率Ｐｆ≥２．５ｍＷ＠Ｉｆ＝７５ｍＡ，边模抑制比ＳＭＳＲ〉３５ｄＢ，调制器反向偏压为２．５Ｖ时的消光比为１４ｄＢ，该发射模块在２．５Ｇｂ／ｓＤＷＤＭ系统上进行了传输试验，传输２４０Ｋｍ后无误码，其通道代价≤１ｄＢ＠ＢＥＲ＝１０＾－１２。     

过硫酸钾—脲氧化还原引发的甲基丙烯酸乙酯基三甲基氯化铵反…

研究了以ｓｐａｎ－８０为乳化剂和过硫酸钾－脲引发体系下，甲基丙烯酸乙酯基三甲基氯化铵反相乳液聚合的动力学，得出在「Ｋ２Ｓ２Ｏ８」为１２．３－７３．８μｍｏｌ．Ｌ＾－１．「ＣＯ（ＮＨ２）２」ｏ为０－０．９５ｍｍｏｌＬ＾－１，乳化剂为４１．７５－６６．８０ｇ．Ｌ＾－１范围内的聚合速率表达式：Ｒｐ＾∞「ＤＭ．ＭＣ」＾１．７１「Ｋ２Ｓ２Ｏ８」＾０．２８「ＣＯ（ＮＨ２）２」＾０．０１「３」＾－１．１８，ＢＣ     

DBM-g-PE与PVC的相互作用研究EI

采用固相接枝法制备了ＤＢＭ－ｇ－ＰＥ，用红外光谱分析证明了接枝物确实存在。ＰＶＣ／ＣＰＥ＝１００／５合金性能测定结果表明，添加５份接枝物的合金（Ａ），缺口冲击强度、拉伸强度分别为１８．２ｋＪ／ｍ２和５３．０ＭＰａ；而添加５份ＰＥ的合金（Ｂ），其相应性能为５．１ｋＪ／ｍ２和３３．８ＭＰａ。不加接枝物的合金（Ｃ），虽有高韧性，但拉伸强度却由５３．０ＭＰａ降至５０．２ＭＰａ。ＤＳＣ、ＳＥＭ的结果均表明，ＰＥ接枝ＤＢＭ后与ＰＶＣ的相互作用增强，与ＣＰＥ协同作用能增韧、增强ＰＶＣ，并探讨了其机理。     

DMF中电沉积制备Yb-Co合金膜

研究了于室温下含有少量水的ＹｂＣｌ３－ＣｏＣｌ２－ＤＭＦ溶液中电沉积制备Ｙｂ－Ｃｏ合金膜。ＥＤＡＸ和ＸＲＤ分析表面：在０．１０ｍｏｌ／Ｌ ＹｂＣｌ３－０．１０ｍｏｌ／Ｌ ＣｏＣｌ２的ＤＭＦ电镀液中,以控制电位为－２．７５Ｖ（ＳＣＥ）进行恒电位电解,以控制电流密度为１００Ａ／ｍ＾２进行恒电流电解或以控制脉冲电流密度为１５０Ａ／ｍ＾２进行脉冲电解,可以得到不同形态和Ｙｂ含量的共沉积合金膜,且膜层光滑、     

AMT保护青铜的研究

采用电化学方法和ＸＰＳ、ＡＥＳ法研究５－氨基－２－巯基－１、３、４－噻二唑（ＡＭＴ）在青铜表面形成的保护膜。结果表明，ＡＭＴ溶液处理后的青铜试片在ｐＨ值为７的０．５ｍｏｌ／ＬＮａ２ＳＯ４和５％ＮａＣｌ溶液中，其腐蚀过程受到了明显抑制，是由于ＡＭＴ在青铜表面形成Ｃｕ（Ｉ）ＡＭＴ络合物膜，其结构为Ｃｕ｜Ｃｕ２Ｏ｜Ｃｕ（Ｉ）ＡＭＴ。     

HL—1M装置硼化膜的研究

ＨＬ－１Ｍ装置采用Ｃ２Ｂ１０Ｈ１２蒸汽等离子体增强沉积技术对第一壁进行了原位硼化，在第一壁表面上形成一层半透明、非晶ａ－Ｂ／Ｃ：Ｈ膜。在单电极、１．２Ａ／７５０Ｖ放电参数下，平均沉积速率为１１０ｎｍ／ｈ，膜厚不均匀度为８４％，Ｂ／Ｃ＝０．６－２．０，Ｂ－Ｃ的结合能为９７－９９ｅＶ，与Ｂ／Ｃ值有关。膜层中有２０－３０％的硼是以Ｂ－Ｃ的形式存在，７０－８０％碳是以ａ－Ｃ：Ｈ形式存在，这是ＨＬ－１Ｍ装置     

Fe73.5Cu1Mo3Si13.5B9微晶软磁合金的结构及其对磁性的影响

对Ｆｅ７３．５Ｃｕ１Ｍｏ３Ｓｉ１３．５Ｂ９微晶软磁合金的结构及其对合金磁性的影响了研究，结果表明，在最佳磁性能下，晶相点阵常数ａ＝０．２８４３ｎｍ，相当于Ｆｅ（Ｓｉ）固溶体中含Ｓｉ％（ｍｏｌ／ｍｏｌ）：１８－２０，体积百分数Ｖ＝７４．８％，晶粒尺寸Ｄ＝１４．６ｎｍ；残余非晶层厚度δ＝１．２３ｎｍ；当Ｔ退火≥５６０℃时明显有Ｆｅ－Ｂ化合物析出。Ｆｅ７３．５Ｃｕ１Ｍｏ３Ｓｉ１３．５Ｂ９合金的磁性不仅与     

在Ag基体上用MOCVD法连续制备YBCO超导带

用ＭＯＣＶＤ法在Ａｇ基体上以－１５ｃｍ／ｈ的带速连续制备ＹＢＣＯ超导带，在８００－８５０℃之间沉积的样品均呈强裂ｃ－轴取向；而在７５０－８００℃间，ｃ－轴取向明显减弱，前者为不规则排列的大片状晶结构，而后者为不规则排列的小棒状晶和发育不育的片状晶，或者为小粒状晶集，所制亲品的Ｊｃ（７８Ｋ，ｏ）一般在０．５－１×１０＾４Ａ／ｃｍ＾２之间，最好的达到１．４×１０＾４Ａ／ｃｍ＾２。     

一种改进的C-V主动轮廓模型

本文对C-V主动轮廓模型进行改进.依据曲线演化理论对C-V模型中的图像数据力驱动项进行简化,提出一种常微分方程(ODE)类型的模型.理论分析验证了该模型的水平集函数可初始化为零.与传统C-V模型相比,不但具有其特点,如可以自动检测带孔目标的内轮廓等,而且具有以下优点:抗噪性能较优;水平集函数无需重新初始化,可快速计算出全局最优分割;远离轮廓的边界可以被准确检测;时间迭代步长不受限制.对合成和真实图像的分割结果证明了本文模型具有稳健、快速的优点.     

Capacitance of Thin-Film Ferroelectrics Under Different Drive Signals

Thin-film ferroelectric capacitance can be obtained by 2 different methods. Capacitance obtained using the derivative of its hysteresis loop is related to large applied signals and can be called the large-signal capacitance. Capacitance measured directly with a small, applied ac signal together with a slow changing dc bias is called the small-signal capacitance. This paper investigated the voltage dependence of the large- and small-signal capacitances. Measurements show that the large-signal C-V curve of thin-film ferroelectrics has much sharper peaks and higher peak values than the small-signal C-V curve. Analyses based on the Landau-Khalatnikov model shows that practical small-signal capacitance is closer to the ideal capacitance. However, its C-V curve has clearance areas around the coercive voltage, and the polarization switching is not reflected in the small-signal capacitance. This causes the peaks of small-signal C-V curves to be lower than that of large-signal C-V curves.     

Gate electrostatics and quantum capacitance of graphene nanoribbons

Capacitance-voltage (C-V) characteristics are important for understanding fundamental electronic structures and device applications of nanomaterials. The C-V characteristics of graphene nanoribbons (GNRs) are examined using self-consistent atomistic simulations. The results indicate strong dependence of the GNR C-V characteristics on the edge shape. For zigzag edge GNRs, highly nonuniform charge distribution in the transverse direction due to edge states lowers the gate capacitance considerably, and the self-consistent electrostatic potential significantly alters the band structure and carrier velocity. For an armchair edge GNR, the quantum capacitance is a factor of 2 smaller than its corresponding zigzag carbon nanotube, and a multiple gate geometry is less beneficial for transistor applications. Magnetic field results in pronounced oscillations on C-V characteristics.     

Precipitation and hot ductility of low C-V and low C-V-Nb microalloyed steels during thin slab casting

Abstract

The as cast hot ductility of low C-V, low C-V-Nb, and niobium microalloyed steels has been investigated using in situ melted tensile specimens, which were subjected to cooling rates and strain rates found typically in thin slab casting. Stress relaxation tests were performed on in situ melted specimens to monitor the kinetics of strain induced precipitation in the above steels. Although the addition of niobium to low C-V and low C-V-N steels increased the temperature at which ductility began to deteriorate, ductility was improved in the low temperature region of the austenite. This was attributed to a delay in NbVC,N precipitation in V-Nb steels. Increasing the nitrogen content did not influence the temperature at the onset of ductility loss in low C-V and low C-V-Nb steels, but did increase the temperature marking the onset of the ductility trough. Faster cooling rates led to a deterioration of ductility in low C-V-N and low C-V-Nb-N steels. The as cast ductility of low C-V and low C-V-Nb steels was superior to that as of cast peritectic C-Nb steel as well as reheated peritectic C-V and peritectic C-V-Nb steels.     

MF(I)S结构设计对硅基铁电薄膜系统C-V特性的影响

为制备符合铁电场效应晶体管（ Ｆ Ｆ Ｅ Ｔ） 及铁电存储二极管（ Ｆ Ｍ Ｄ） 要求的高质量铁电薄膜,采用 Ｐ Ｌ Ｄ （ Ｐｕｌｓｅｄ Ｌａｓｅｒ Ｄｅｐｏｓｉｔｉｏｎ） 工艺, 制备了不同 Ｍ Ｆ （ Ｉ） Ｓ 结构的硅基铁电薄膜系统由 Ｃ－ Ｖ特性的对比分析可见, 影响 Ｃ－ Ｖ 特性的主要因素除了衬底类型、界面特性之外, 还有薄膜的结构设计在此基础上, 为改善铁电薄膜的 Ｃ－ Ｖ 特性提出了合理设想     

MF(I)S结构设计对硅基铁电薄膜系统C-V特性的影响

为制备符合铁电场效应晶体管（ Ｆ Ｆ Ｅ Ｔ） 及铁电存储二极管（ Ｆ Ｍ Ｄ） 要求的高质量铁电薄膜,采用 Ｐ Ｌ Ｄ （ Ｐｕｌｓｅｄ Ｌａｓｅｒ Ｄｅｐｏｓｉｔｉｏｎ） 工艺, 制备了不同 Ｍ Ｆ （ Ｉ） Ｓ 结构的硅基铁电薄膜系统由 Ｃ－ Ｖ特性的对比分析可见, 影响 Ｃ－ Ｖ 特性的主要因素除了衬底类型、界面特性之外, 还有薄膜的结构设计在此基础上, 为改善铁电薄膜的 Ｃ－ Ｖ 特性提出了合理设想.     

Ag/Bi4Ti3O12/p-Si异质结的制备及其C-V特性研究

为制备符合铁电存储器件要求的高质量铁电薄膜,采用溶胶-凝胶(Sol-Gel)工艺,制备了Si基Bi4Ti3O12铁电薄膜及MFS结构的Ag/Bi4Ti3O12/P-Si异质结,对Bi4Ti3O12薄膜的相结构特征及异质结的C-V特性进行了测试与分析.XRD图谱显示,Si基Bi4Ti3O12薄膜具有沿c-轴择优取向生长的趋势,而Ag/Bi4Ti3O12/p-Si异质结顺时针回滞的C-V特性曲线则表明,该异质结可实现电极化存储.此外,对该异质结C-V特性曲线的非对称及向负偏压方向偏移的产生原因也进行了分析.在此基础上,为提高铁电薄膜的铁电性能及改善其C-V特性提出了合理的结构设想.     

Nonvolatile memory devices based on ZnO/polyimide nanocomposite sandwiched between two C60 layers

The memory effects of a three-layer nonvolatile memory device Al/C₆₀/ZnO nanoparticles embedded in a polyimide (PI) layer/C₆₀/p-Si were investigated by using capacitance-voltage (C-V) measurements. Transmission electron microscopy and selected area electron diffraction pattern measurements showed that ZnO nanocrystals were formed inside the PI layer. The insertion of C₆₀ layer improved the charge trap state density in the ZnO nanoparticle. The density was estimated by the flatband voltage shift in the C-V hysteresis, which increases with the max sweep voltage. Possible operating mechanisms corresponding to the charging and discharging process in the structure are proposed on the basis of the C-V results.     

Variations in the memory capability of nonvolatile memory devices fabricated using hybrid composites of InP nanoparticles and a polystyrene layer due to the scale-down

InP nanoparticles were formed using a solution method, and the InP nanoparticles that were embedded in a polystyrene (PS) layer were formed using the spin-coating method. The transmission electron microscopy images showed that the InP nanoparticles were randomly distributed in the PS layer. The measured capacitance-voltage (C-V) of the Al/InP nanoparticles embedded in the PS layer/PS/p-Si(100) device at 300 K showed a clockwise hysteresis of the C-V curve. Based on the C-V results, the origin of variations in the memory storage of nonvolatile memory devices that were fabricated using InP nanoparticles embedded in a PS layer due to the scale-down was described.     

Determining adhesion and hermeticity of the interface between encapsulation polymer and insulating layer of micro-sensing chips via a capacitance-voltage technique

The successful application of micro-sensing chips based on ion-sensitive field effect transistor principles depends on preventing the penetration of electrolyte into the interface between the encapsulation polymer and the insulating layer. This study employs a capacitance-voltage (C-V) technique to evaluate the adhesion and hermeticity of the polymer-substrate interface in a liquid environment. Three-layered structures simulating micro-sensing chips were fabricated for the evaluation. Each three-layered structure comprises an upper epoxy layer (with or without a window opening), a middle dielectric layer, and a lower Si wafer substrate. Equivalent circuits were established to explain the C-V characteristics of the three-layered structures. The results show that by applying the C-V technique and using an appropriate equivalent circuit, the adhesion and hermeticity between the encapsulating epoxy layer and the insulating layer can be evaluated.