Direct sub-100-nm patterning of an organic low-k dielectric for electrical and optical interconnects

Low-k dielectric materials compatible with copper interconnect fabrication processes extending to the sub-50-nm technology nodes are desired for high speed integrated circuit (IC) fabrication. We demonstrate that bisbenzocyclobutene (BCB), an organic low-k dielectric material, can be patterned with sub-100-nm resolution using electron beam lithography, providing new avenues for nanoscale electrical and optical interconnect fabrication.     

聚甲基丙烯酸甲酯LB膜用作高分辨率电子束抗蚀层的研究

应用LB技术制备了厚度为20100nm的聚甲基丙烯酸甲酯(PMMA)超薄高分辨率电子束抗蚀层。应用改装的日立S-450扫描电子显微镜(SEM),研究了PMMALB膜的曝光特性和刻蚀条件。结果得到线宽0.15m的铝掩模光栅图形,表明此种超薄膜具有良好的分辨率和足够的抗蚀性。     

A novel approach for the patterning and high-volume production of sub-40-nm gates

A novel approach for the patterning and manufacturing of sub-40-nm gate structures is presented. Rather than using resist or an inorganic hardmask as the patterning layer, this gate patterning scheme uses an amorphous carbon (a:C) and cap hardmask to pattern small gates. Healthy and manufacturable gate lengths have been achieved below 35 nm with this scheme, and the potential exists for further extendibility.     

Accurate nano-EB lithography for 40-nm gate MOSFETs

Nanometer electron beam lithography has been used for fabrication of sub-0.1 μm MOSFETs. Chemically amplified resist as a single layer mask showed high resolution by optimizing the resist process. Proximity effect correction was applied and showed a good line width control. Operation of a 40nm-polysilicon gate NMOSFET was confirmed.     

UV enhanced substrate conformal imprint lithography (UV-SCIL) technique for photonic crystals patterning in LED manufacturing

The global LED (light emitting diode) market reached 5 billion dollors in 2008 and will be driven towards 9 billion dollors by 2011 [1]. The current applications are dominated by portable device backlighting, e.g. cell phones, PDAs, GPS, laptop etc. In order to open the general lighting market doors the luminous efficiency needs to be improved significantly. Photonic crystal (PhC) structures in LEDs have been demonstrated to enhance light extraction efficiency on the wafer level by researchers [2]. However, there is still a great challenge to fabricate PhC structures on LED wafers cost-effectively. Nanoimprint lithography (NIL) [3] has attracted considerable attentions in this field due to its high resolution, high throughput and low cost of ownership (CoO). However, the current NIL techniques with rigid stamps rely strongly on the substrate flatness and the production atmosphere. Those factors hinder the integration of NIL into high volume production lines. UV-NIL with flexible stamps [4], e.g. PDMS stamps, allows the large-area imprint in a single step and is less-sensitive to the production atmosphere. However, the resolution is normally limited due to stamp distortion caused by imprint pressure.A novel NIL technique developed by Philips Research and Süss MicroTec, substrate conformal imprint lithography (SCIL), bridges the gap between UV-NIL with rigid stamp for best resolution and soft stamp for large-area patterning. Based on a cost-effective upgrade on Süss mask aligner, the capability can be enhanced to nanoimprint with resolution of down to sub-10 nm on an up to 6 inch area without affecting the established conventional optical lithographic processes on the machine. Benefit from the exposure unit on the mask aligners, the SCIL process is now extended with UV-curing option, which can help to improve the throughput dramatically. In this paper, the fabrication of photonic crystal structures with SCIL technique on Süss MA6 mask aligner is demonstrated. In addition, the industrialization considerations of UV-SCIL process in high volume manufacturing are briefly discussed.     

Fabrication and characterization of PEDOT nanowires based on self-assembled peptide nanotube lithography

In this article we demonstrate the use of self-assembled peptide nanotube structures as masking material in a rapid, mild and low cost fabrication of polymerized p-toluenesulfonate doped poly(3,4-ethylenedioxythiophene) (PEDOT:TsO) nanowire device. In this new fabrication approach the PEDOT:TsO nanowire avoids all contact with any organic solvents otherwise traditionally used in clean room fabrication. This can be achieved due to the intriguing properties of the self-assembled peptide nanotubes utilized as a dry etching mask for the patterning of the PEDOT:TsO nanowire. The peptide nanotubes, despite remaining stable during the reactive ion etching procedure, can be dissolved rapidly in water afterwards. The fabricated PEDOT:TsO nanowire devices exhibit excellent electrical characteristics. Finally, the potential of PEDOT:TsO nanowires as temperature sensors has been demonstrated and the high resolution of the sensor was illustrated.     

Fabrication of Flexible Binary Amplitude Masks for Patterning on Highly Curved Surfaces

This paper describes soft lithography methods that expand current fabrication capabilities by enabling high‐throughput patterning on nonplanar substrates. These techniques exploit optically dense elastomeric mask elements embedded in a transparent poly(dimethylsiloxane) (PDMS) matrix by vacuum‐assisted microfluidic patterning, UV–ozone‐mediated irreversible sealing, and chemical etching. These protocols provide highly flexible photomasks exhibiting either positive‐ or negative‐image contrasts, which serve as amplitude masks for large‐area photolithographic patterning on a variety of curved (and planar) surfaces. When patterning on cylindrical surfaces, the developed masks do not experience significant pattern distortions. For substrates with 3D curvatures/geometries, however, the PDMS mask must undergo relatively large strains in order to make conformal contact. The new methods described in this report provide planar masks that can be patterned to compliantly compensate for both the displacements and distortions of features that result from stretching the mask to span the 3D geometry. To demonstrate this, a distortion‐corrected grid pattern mask was fabricated and used in conjunction with a homemade inflation device to pattern an electrode mesh on a glass hemisphere with predictable registration and distortion compensation. The showcased mask fabrication processes are compatible with a broad range of substrates, illustrating the potential for development of complex lithographic patterns for a variety of applications in the realm of curved electronics (i.e., synthetic retinal implants and curved LED arrays) and wide field‐of‐view optics.     

High-speed Schottky-barrier pMOSFET with f/sub T/=280 GHz

High-speed results on sub-30-nm gate length pMOSFETs with platinum silicide Schottky-barrier source and drain are reported. With inherently low series resistance and high drive current, these deeply scaled transistors are promising for high-speed analog applications. The fabrication process simplicity is compelling with no implants required. A sub-30-nm gate length pMOSFET exhibited a cutoff frequency of 280 GHz, which is the highest reported to date for a silicon MOS transistor. Off-state leakage current can be easily controlled by augmenting the Schottky barrier height with an optional blanket As implant. Using this approach, good digital performance was also demonstrated.     

Nanofabrication with proximal probes

In this paper, we describe the use of proximal probes, such as the atomic force microscope (AFM) and the scanning tunneling microscope (STM), for nanofabrication. A resistless proximal probe-based lithographic technique has been developed that uses the local electric field of an STM or conductive AFM tip that is operated in air to selectively oxidize regions of a sample surface. The resulting oxide, typically 1-10 nm thick, can be used either as a mask for selective etching or to directly modify device properties by patterning insulating oxides on thin conducting layers. In addition to this resistless approach, we also describe the use of the STM/AFM to modify the chemical functionality of self-assembling monolayer films. Such modified films are used as a template for the selective electroless plating of metal films. The above processes are fast simple to perform, and well suited for device fabrication. We apply the anodic oxidation process to the fabrication of both semiconductor and metal-oxide devices. In these latter structures, sub-10 nm-sized device features are easily achieved, and we describe the fabrication of the smallest possible device, a single, atomic-sized metallic point contact by using in situ-controlled AFM oxidation     

Transparent and Reusable Nanostencil Lithography for Organic–Inorganic Hybrid Perovskite Nanodevices

Organic—inorganic hybrid perovskites have attracted considerable attention for developing novel optoelectronic devices owing to their excellent photoresponses. However, conventional nanolithography of hybrid perovskites remains a challenge because they undergo severe damage in standard lithographic solvents, which prohibits device miniaturization and integration. In this study, a novel transparent stencil nanolithography (t-SL) technique is developed based on focused ion beam (FIB)-assisted polyethylene terephthalate (PET) direct patterning. The proposed t-SL enables ultrahigh lithography resolution down to 100 nm and accurate stencil mask alignment. Moreover, the stencil mask can be reused more than ten times, which is cost-effective for device fabrication. By applying this lithographic technique to hybrid perovskites, a high-performance 2D hybrid perovskite heterostructure photodetector is fabricated. The responsivity and detectivity of the proposed heterostructure photodetector can reach up to 28.3 A W⁻¹ and 1.5 × 10¹³ Jones, respectively. This t-SL nanolithography technique based on FIB-assisted PET direct patterning can effectively support the miniaturization and integration of hybrid-perovskite-based electronic devices.     

Rigorous electromagnetic simulation of mask magnification effects on the diffracted light for EUV binary mask

Extreme ultraviolet (EUV) lithography is expected to be the main candidate in the semiconductor manufacturing starting at 32 nm. As the CD is getting smaller, the aspect ratio of the patterns on the EUV mask is becoming larger. The shadowing effect will become much more significant when keeping the same 4× mask magnification. In this work, mask magnification effects on the diffracted light were explored with rigorous coupled-wave analysis (RCWA) for the sub-32 nm node. The simulated binary mask consists of 70-nm TaBN absorber and 2.5-nm Ru capping layer. The dependences of the diffraction efficiencies on mask pitches were calculated. The impacts of the absorber shadowing were observed from the near field distribution on the EUV mask. The aerial images formed by the diffracted light from the 4× and 8× masks were further evaluated.     

Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs

A simple process for the fabrication of shallow drain junctions on pillar sidewalls in sub-100-nm vertical MOSFETs is described. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The depth of the junction on the pillar sidewall is primarily determined by the thickness of the polysilicon spacer. This process is CMOS compatible and, hence, facilitates the integration of a sub-100-nm vertical MOSFET in a planar CMOS technology using mature lithography. The fabricated transistors have a subthreshold slope of 95 mV/dec (at V/sub DS/=1 V) and a drain-induced barrier lowering of 0.12 V.     

Modeling of in-plane distortions due to variations in absorber stress

The effort to achieve sub-0.25 μm X-ray lithography depends, in part, on the ability to maintain strict fabrication control leading to low distortion X-ray masks. This paper presents finite element (FE) models developed to identify sources of pattern in-plane distortions (IPD) during mask fabrication. In particular, mask fabrication processes inducing both uniform and non-uniform absorber stresses and the resulting distortions due pattern transferring through these stressed layers have been investigated.     

Fabrication of self-aligned 90-nm fully depleted SOI CMOS SLOTFETs

We have developed a novel sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS fabrication process, in which conventional 248-nm optical lithography and nitride spacer technology are used to define slots in a sacrificial layer (SLOTFET process). This process features a locally thinned SOI channel with raised source-drain regions, and a low-resistance T-shaped poly-Si gate; Both n- and p-channel MOSFETs with 90-nm gate length have been demonstrated. At a 0.5 V bias voltage, ring-oscillator propagation delay of less than 50 ps per stage has been measured     

Template fabrication for the 32 nm node and beyond

Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. Step and flash imprint lithography (S-FIL^™) is a unique method that has been designed from the beginning to enable precise overlay for creating multilevel devices. A photocurable low viscosity monomer is dispensed dropwise to meet the pattern density requirements of the device, thus enabling imprint patterning with a uniform residual layer across a field and across entire wafers. Further, S-FIL provides sub-100 nm feature resolution without the significant expense of multi-element, high quality projection optics or advanced illumination sources. However, since the technology is 1X, it is critical to address the infrastructure associated with the fabrication of templates.This paper addresses steps required to achieve resolution at or below 32 nm. Gaussian-beam writers are now installed in mask shops and are being used to fabricate S-FIL templates. Although the throughput of these systems is low, they can nevertheless be applied towards applications such as unit process development and device prototyping.Resolution improvements were achieved by optimizing the ZEP520A resolution and exposure latitude. Key to the fabrication process was the introduction of thinner resist films and data biasing of the critical features. By employing a resist thickness of 70 nm and by negatively biasing features as much as 18 nm, 28 nm half-pitch imprints were obtained. Further processing improvements show promise for achieving 20 nm half-pitch features on a template.     

Patterned magnetic nanostructures and quantized magnetic disks

Nanofabrication, offering unprecedented capabilities in the manipulation of material structures and properties, opens up new opportunities for engineering innovative magnetic materials and devices, developing ultra-high-density magnetic storage, and understanding micromagnetics. This paper reviews the recent advances in patterned magnetic nanostructures, a fast-emerging field, including (1) state-of-the-art technology for patterning of magnetic nanostructures as small as 10 nm; (2) engineering of unique magnetic properties (such as domain structures, domain switching, and magnetoresistance) by patterning and controlling the size, shape, spacing, orientation, and compositions of magnetic materials; (3) quantized magnetic disks-a new paradigm for ultra-high-density magnetic storage based on patterned single-domain elements that have demonstrated a storage density of 65 Gb/in² (nearly two orders of magnitude higher than that in current commercial magnetic disks) and a capability of 400 Gb/in² ; (4) novel magnetoresistance sensors based on unique properties of magnetic nanostructures; (5) other applications of nanoscale patterning in magnetics such as the quantification of magnetic force microscopy (MFM) and a new ultra-high-resolution MFM tip; and (6) sub-10-nm imprint lithography-a new low-cost, high-throughput technology for manufacturing magnetic nanostructures     

POLYMETHYLMETHACRYLATE LANGMUIR-BLODGETT FILMS FOR HIGH RESOLUTION ELECTRON BEAM RESIST

Ultra-thin (20-100nm) polymethylmethacrylate(PMMA) films prepared by Langmuir-Blodgett techniques have been explored as high resolution electron beam resists. A Hitachi S-450 Scanning Electron Microscope (SEM) has been refitted for a high resolution electron beam exposure system. The lithographic properties and exposure conditions of LB PMMA films were investigated. 0.15μm lines-and-spaces patterns were achieved by using the SEM as the exposure tool. The results demonstrate that the etch resistance of such films is sufficiently good to allow patterning of a 20 nm aluminum film suitable for mask fabrication.     

Phase-shifted Bragg grating filters in polymer waveguides

We fabricated a very narrow-band 0.03-nm (5-GHz) phase-shifted Bragg grating filter at 1290 nm on an LD-3 polymer ridge waveguide. The grating was post processed onto the waveguide by photobleaching using a 457-nm argon ion laser with a phase mask. We present the details of the fabrication process and a measurement of the filter spectrum with an analysis.     

Sub-100-nm vertical MOSFET with threshold voltage adjustment

Sub-100-nm vertical MOSFET has been developed for fabrication with low cost processing. This is the first vertical MOSFET design that combines 1) a vertical L_DD structure processed with implantation and diffusion steps, 2) high-pressure oxide growing at source/drain (S/D) regions to reduce the gate overlapped capacitances, and 3) threshold voltage adjustment with a doped APCVD film. The drive current per unit channel width and S/D punch-through voltage are higher than that of previously published vertical MOSFETs. Fabrication processes are well established, and equipment of the 1 μm CMOS generation can be used to fabricate sub-100-nm channel length MOSFETs with good electrical characteristics and high performance     

Development of metal etch mask by single layer lift-off for silicon nitride photonic crystals

We present a method for fabrication of nanoscale patterns in silicon nitride (SiN) using a hard chrome mask formed by metal liftoff with a negative ebeam resists (maN-2401). This approach enables fabrication of a robust etch mask without the need for exposing large areas of the sample by electron beam lithography. We demonstrate the ability to pattern structures in SiN with feature sizes as small as 50 nm. The fabricated structures exhibit straight sidewalls, excellent etch uniformity, and enable patterning of nanostructures with very high aspect ratios. We use this technique to fabricate two-dimensional photonic crystals in a SiN membrane. The photonic crystals are characterized and shown to have quality factors as high as 1460.