Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (bulk FinFETs)

In this paper,the operational six-transistor SRAM cell characteristic was demonstrated using body-tied triple-gate MOSFETs (bulk FinFETs). A cell size of 0.79 /spl mu/m/sup 2/ was achieved with 90-nm node technology, using four levels of W and Al interconnects. A static noise margin of 280 mV was obtained at V/sub CC/ of 1.2 V by applying bulk FinFETs, and compared with those of typical optimized control devices and nanoscale planar channel MOSFETs. The characteristics of the bulk FinFETs were compared with those of nanoscale planar channel MOSFETs, and analyzed in detail by changing nanoscale active width (or fin width). Fabrication process issues for the bulk FinFETs were explained in terms of poly-Si gate over-etching and silicidation on nanoscale fin bodies. Also, input and output characteristics of the individual and parallel arrayed transistors were shown and analyzed.     

A novel strained Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFET with an ALD TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack

Proof-of-concept pMOSFETs with a strained-Si/sub 0.7/Ge/sub 0.3/ surface-channel deposited by selective epitaxy and a TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack grown by atomic layer chemical vapor deposition (ALD) techniques were fabricated. The Si/sub 0.7/Ge/sub 0.3/ pMOSFETs exhibited more than 30% higher current drive and peak transconductance than reference Si pMOSFETs with the same gate stack. The effective mobility for the Si reference coincided with the universal hole mobility curve for Si. The presence of a relatively low density of interface states, determined as 3.3 /spl times/ 10/sup 11/ cm/sup -2/ eV/sup -1/, yielded a subthreshold slope of 75 mV/dec. for the Si reference. For the Si/sub 0.7/Ge/sub 0.3/ pMOSFETs, these values were 1.6 /spl times/ 10/sup 12/ cm/sup -2/ eV/sup -1/ and 110 mV/dec., respectively.     

Implementation and characterization of the double-gate MOSFET using lateral solid-phase epitaxy

In this paper, a simple high performance double-gate metal oxide semiconductor field effect transistor (MOSFET) using lateral solid-phase epitaxy (LSPE) is experimentally demonstrated and characterized. The thin channel of the double-gate MOSFET was obtained using the high quality LSPE crystallized layer. The fabricated double-gate MOSFET provides good current drive capability and steep subthreshold slope, and they are approximately 350 /spl mu/A//spl mu/m (@ V/sub ds/ = 2.5 V and V/sub gs/ - V/sub T/ = 2.5 V) and 78 mV/dec for the devices with 0.5 /spl mu/m channel length. Compared to the conventional single-gate transistor, the double-gate NMOSFET fabricated on the LSPE layer has better V/sub T/ roll-off characteristics, DIBL effect, and 1.72 times higher current drive. The peak effective electron mobility of the LSPE crystallized layer is approximately 382 cm/sup -2//V.s.     

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.     

Schottky-barrier source/drain MOSFETs on ultrathin SOI body with a tungsten metallic midgap gate

This letter presents a simple low-temperature process to fabricate Schottky-barrier (SB) MOSFETs that integrates a midgap metallic gate (tungsten). The device architecture is based on a thin (10 nm) and lowly doped silicon-on-insulator film that provides a threshold voltage of -0.3 V independent on the depletion charge and therefore not sensitive to variations in film thickness and doping. A gate encapsulation technique using an SiO/sub 2/-like hydrogen silsesquioxane capping layer features 15-nm-wide spacers and ensures the compatibility with the PtSi self-aligned silicide process. Long-channel devices present an ideal subthreshold swing of 60 mV/dec, over six decades of I/sub on//I/sub off/ without any sign of sublinear upward bending of the I/sub DS/--V/sub DS/ curves at low drain voltage.     

Ni fully GermanoSilicide for gate electrode application in pMOSFETs with HfSiON gate dielectrics

A study on using a novel metal gate-the Ni fully GermanoSilicide (FUGESI)-in pMOSFETs is presented. Using HfSiON high-/spl kappa/ gate dielectrics and comparing to Ni fully Silicide (FUSI) devices, this paper demonstrates that the addition of Ge in poly-Si gate (with Ge/(Si+Ge)/spl sim/50%) results in: 1) an increase of the effective work function by /spl sim/ 210 mV due to Fermi-level unpinning effect; 2) an improved channel interface; 3) a reduced gate leakage; and 4) the superior negative bias temperature instability characteristics. Low-frequency noise measurement reveals a decreased 1/f and generation-recombination noise in FUGESI devices compared to FUSI devices, which is attributed to the reduced oxygen vacancies (V/sub o/)-related defects in the HfSiON dielectrics in FUGESI devices. The reduced V/sub o/-related defects stemming from Ge at FUGESI /HfSiON interface are correlated with the Fermi-level unpinning effect and the improved electrical characteristics observed in FUGESI devices.     

Characterization of the ultrathin vertical channel CMOS technology

In this paper, an ultrathin vertical channel (UTVC) CMOS with self-aligned asymmetric lightly doped drain is experimentally demonstrated. In the structure, the UTVC was obtained using solid phase epitaxy, and the midgap material, boron-doped poly-Si/sub 0.5/Ge/sub 0.5/, was used as the gate electrode to obtain symmetrical threshold voltages for both the NMOS and PMOS devices. Due to the ultrathin channel, the fabricated CMOS devices offer good immunity to short channel effects, and the typical subthreshold slopes of the 80 nm NMOS and PMOS are 102 mV/dec and 120 mV/dec, respectively. The fabricated CMOS inverters also show reasonable transfer characteristics. The UTVC CMOS technology provides a simple way to implement sub-100 nm devices for ULSI applications.     

Suppression of corner effects in wide-channel triple-gate bulk FinFETs

This paper presents a method of eliminating corner effects in triple-gate bulk FinFETs. The parasitic device in FinFET’s corners can be turned off by increasing body doping in corner regions by corner implantation. Corner implantation described in this work does not require additional masks, rotation or tilt. This method is investigated in idealized (with rectangular cross-section of the fin) and realistic (with rounded top corners of the fin) triple-gate bulk FinFETs and has shown considerable improvements: kink effect in transfer characteristics is completely eliminated, threshold voltage increased by up to 0.43 V, subthreshold swing and drain-induced barrier-lowering decreased to values under 95 mV/dec and 16 mV/V, respectively. Optimization is performed on the realistic rounded-corner FinFET structure to find the proper body doping and corner implantation peak values for acceptable threshold voltage and on-state current.     

An experimental study on transport issues and electrostatics of ultrathin body SOI pMOSFETs

We present an experimental study of the transport properties (low field hole mobility /spl mu//sub h/) and electrostatics (threshold voltage V/sub th/, and gate-to-channel capacitance C/sub gc/) of ultrathin body (UTB) SOI pMOSFETs using a large RingFet structure. Body thicknesses were /spl sim/4.3 nm to 50 nm. We find that 1) hole mobility decreases significantly as T/sub Si/<10 nm, and tends to show negligible dependence on the transverse electric field for extremely thin T/sub Si/ (<6 nm) and 2) a V/sub th/ shift of /spl sim/150 mV occurs over the studied T/sub Si/ range, accompanied by enhancement of weak inversion capacitance in thin body devices. Simulations were performed to provide insight into the experimental observations.     

An ultrathin vertical channel MOSFET for sub-100-nm applications

An ultrathin vertical channel (UTVC) MOSFET with an asymmetric gate-overlapped low-doped drain (LDD) is experimentally demonstrated. In the structure, the UTVC (15 nm) was obtained using the cost-effective solid phase epitaxy, and the boron-doped poly-Si/sub 0.5/Ge/sub 0.5/ gate was adopted to adjust the threshold voltage. The fabricated NMOSFET offers high-current drive due to the lightly doped (<1/spl times/10/sup 15/ cm/sup -3/) channel, which suppresses the electron mobility degradation. Moreover, an asymmetric gate-overlapped LDD was used to suppress the offstate leakage current and reduce the source/drain series resistance significantly as compared to the conventional symmetrical LDD. The on-current drive, offstate leakage current, subthreshold slope, and DIBL for the fabricated 50-nm devices are 325 /spl mu/A//spl mu/m, 8/spl times/10/sup -9/ /spl mu/A//spl mu/m, 87 mV/V, and 95 mV/dec, respectively.     

Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode

This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.     

Improved independent gate N-type FinFET fabrication and characterization

N-type independent gate FinFETs (IGFinFETs) have been fabricated and characterized. Previous published results for this structure highlighted processing deficiencies. Several process enhancements have improved device results beyond those previously reported. These process improvements are presented, and the resulting device is demonstrated. Device results for 2 micron channel length devices are shown. Six decades of drain current suppression and low gate leakage currents are achieved. Subthreshold slope of 200 mV/dec and a threshold voltage tuning range of 1.7 V are demonstrated. This device combines the behavioral characteristics of independent-double-gate MOSFETs with the processing advantages and integration of FinFETs.     

The effect of gate metal interdiffusion on reliability performance in GaAs PHEMTs

While Ti metal interdiffusion of Ti-Pt-Au gate metal stacks in GaAs pseudomorphic HEMT (PHEMTs) has been explored, the effect of Ti metal interdiffusion on the reliability performance is still lacking. We use a scanning transmission electron microscopy technique to correlate Ti-metal-InGaAs-channel-separation and Ti-sinking-depth with a threshold voltage V/sub T/. It has been found that Ti-sinking-depth is insensitive to V/sub T/. However, Ti metal interdiffusion reduces the separation of the gate metal and InGaAs channel, thus affecting the I/sub dss/ degradation rate. Accordingly, we observe the dependence of /spl Delta/I/sub dss/ on V/sub T/. Devices with less negative V/sub T/ exhibit inferior reliability performance to those devices with more negative V/sub T/. The results provide insight into a critical device parameter, V/sub T/, for optimizing reliability performance based on I/sub dss/ degradation.     

high-performance and high-reliability 80-nm gate-length DTMOS with indium super steep retrograde channel

In this paper, we demonstrate for the first time a high-performance and high-reliability 80-nm gate-length dynamic threshold voltage MOSFET (DTMOS) using indium super steep retrograde channel implantation. Due to the steep indium super steep retrograde (In SSR) dopant profile in the channel depletion region, the novel In-SSR DTMOS features a low V/sub th/ in the off-state suitable for low-voltage operation and a large body effect to fully exploit the DTMOS advantage simultaneously, which is not possible with conventional DTMOS. As a result, excellent 80-nm gate length transistor characteristics with drive current as high as 348 /spl mu/A//spl mu/m (off-state current 40 nA//spl mu/m), a record-high Gm=1022 mS/mm, and a subthreshold slope of 74 mV/dec, are achieved at 0.7 V operation. Moreover, the reduced body effects that have seriously undermined conventional DTMOS operation in narrow-width devices are alleviated in the In-SSR DTMOS, due to reduced indium dopant segregation. Finally, it was found for the first time that hot-carrier reliability is also improved in DTMOS-mode operation, especially for In-SSR DTMOS.     

Demonstration of short-channel self-aligned Pt/sub 2/Si-FUSI pMOSFETs with low threshold voltage (-0.29 V) on SiON and HfSiON

Short gate-length Pt full-silicidation (FUSI) (PtSi and Pt/sub 2/Si) pMOSFETs were fabricated for the first time using a self-aligned Pt-FUSI process, demonstrating scalability (with no linewidth effects) down to /spl sim/ 60-nm gate lengths. The electrical results are compared to the Ni-FUSI (NiSi and Ni/sub 31/Si/sub 12/) pMOSFET devices. A low threshold voltage /spl les/|-0.29 V| was obtained for the Pt/sub 2/Si-FUSI pMOSFETs on SiON and HfSiON indicating that the Pt/sub 2/Si FUSI does not suffer from the Fermi-level pinning or gate-dielectric-charge effects on the HfSiON.     

铁电负电容场效应晶体管器件的研究

铁电负电容场效应晶体管作为一种新型半导体器件,利用铁电材料的负电容效应可使晶体管的亚阈值摆幅突破理论极限值60 mV/dec,是未来低功耗晶体管领域最具有前途的器件之一。该文研究并建立了铁电负电容场效应晶体管的器件模型,采用Matlab软件对负电容场效应晶体管的器件特性进行了研究分析,获得了亚阈值摆幅为33.917 6 mV/dec的负电容场效应晶体管的器件结构,探究了铁电层厚度、等效栅氧化层厚度及不同铁电材料对负电容场效应晶体管亚阈值摆幅的影响。     

Vg=Vd/2)应力模式下宽度变窄对HALO-pMOSFETs退化的影响

讨论了最差应力模式下(V_g=V_d/2)宽沟和窄沟器件的退化特性.随着器件沟道宽度降低可以观察到宽度增强的器件退化.不同沟道宽度p MOSFETs的主要退化机制是界面态产生.沟道增强的器件退化是由于沟道宽度增强的碰撞电离率.通过分析电流拥挤效应,阈值电压随沟道宽度的变化,速度饱和区特征长度的变化和HAL O结构串联阻抗这些可能原因,得出沟道宽度增强的热载流子退化是由宽度降低导致器件阈值电压和串联阻抗降低的共同作用引起的.     

Correlating drain-current with strain-induced mobility in nanoscale strained CMOSFETs

The correlation between channel mobility gain (/spl Delta//spl mu/), linear drain-current gain (/spl Delta/I/sub dlin/), and saturation drain-current gain (/spl Delta/Idsat) of nanoscale strained CMOSFETs are reported. From the plots of /spl Delta/I/sub dlin/ versus /spl Delta/I/sub dsat/ and ballistic efficiency (Bsat,PSS), the ratio of source/drain parasitic resistance (R/sub SD,PSS/) to channel resistance (R/sub CH,PSS/) of strained CMOSFETs can be extracted. By plotting /spl Delta//spl mu/ versus /spl Delta/I/sub dlin/, the efficiency of /spl Delta//spl mu/ translated to /spl Delta/I/sub dlin/ is higher for strained pMOSFETs than strained nMOSFETs due to smaller RSD,PSS-to-RCH,PSS ratio of strained pMOSFETs. It suggests that to exploit strain benefits fully, the RSD,PSS reduction for strained nMOSFETs is vital, while for strained pMOSFETs the /spl Delta/I/sub dlin/-to-/spl Delta//spl mu/ sensitivity is maintained until R/sub SD,PSS/ becomes comparable to/or higher than R/sub CH,PSS/.     

Impact ionization MOS (I-MOS)-Part I: device and circuit simulations

One of the fundamental problems in the continued scaling of transistors is the 60 mV/dec room temperature limit in the subthreshold slope. In part I this work, a novel transistor based on the field-effect control of impact-ionization (I-MOS) is explored through detailed device and circuit simulations. The I-MOS uses gated-modulation of the breakdown voltage of a p-i-n diode to switch from the OFF state to the ON state and vice-versa. Device simulations using MEDICI show that the I-MOS has a subthreshold slope of 5 mV/dec or lower and I/sub ON/>1 mA//spl mu/m at 400 K. Simulations were used to further explore the characteristics of the I-MOS including the transients of the turn-on mechanism, the short-channel effect, scalability, and other important device attributes. Circuit mode simulations were also used to explore circuit design using I-MOS devices and the design of an I-MOS inverter. These simulations indicated that the I-MOS has the potential to replace CMOS in high performance and low power digital applications. Part II of this work focuses on I-MOS experimental results with emphasis on hot carrier effects, germanium p-i-n data and breakdown in recessed structure devices.     

Germanium MOSFETs With CeO2/HfO2/ TiN Gate Stacks

Long-channel Ge pMOSFETs and nMOSFETs were fabricated with high-kappa CeO₂/HfO₂/TiN gate stacks. CeO₂ was found to provide effective passivation of the Ge surface, with low diode surface leakage currents. The pMOSFETs showed a large I _ON/I_OFF ratio of 10⁶, a subthreshold slope of 107 mV/dec, and a peak mobility of approximately 90 cm² /Vmiddots at 0.25 MV/cm. The nMOSFET performance was compromised by poor junction formation and demonstrated a peak mobility of only ~3 cm²/Vmiddots but did show an encouraging I_ON/I _OFF ratio of 10⁵ and a subthreshold slope of 85 mV/dec