On the loop noise bandwidth of SCCL

SCCL, a new bit tracking loop based on the sample-correlate-choose-largest design principle, was shown to be an effective bit synchronizer. However, the analysis common in analyzing digital phase locked loops, proceeds on the assumption that the noise samples are independent which is not necessarily true in practice. The performance of SCCL, is analyzed without the independence assumption by considering the second-order statistics to complete the analysis. This approach is also useful to analyze other digital phase-locked loops or baseband digital signal processing schemes in digital communication systems     

A Family of Pure Digital Signal Processing Bit Synchronizers

A sample-correlate-choose-largest (SCCL) algorithm is generalized to design a family of efficient baseband digital signal processing (DSP) bit synchronizers. The common feature among maximal likelihood, minimal likelihood, and zero crossing in designing SCCL type DSP bit synchronizers gives us a possible unified point of view in the general design of synchronizers. Optimal signal waveform of “+---” and “-+++” has been derived for this family of bit synchronizers under the signal bandwidth constraint of four times bit rate along with the performance analysis     

一种全数字位同步检测算法

位同步检测是实现全数字接收机开环定时恢复的关键技术。本文推导了基带PAM(脉冲幅度调制)信号的互相关函数,指出基带PAM信号的互相关函数中含有位同步信息,以此为依据得到了一种位同步检测算法。该算法可采用递归结构实现,且与载波相位误差无关。     

Reduced complexity delay-locked loop

In spread spectrum synchronisation the delay-locked loop (DLL) is widely used for PN-code tracking. A new DLL configuration using only one correlator to generate the timing error signal is presented. This reduces the hardware complexity of the code synchronisation. The structure of the new loop is described and performance results are shown     

伪码测距雷达中的伪码跟踪环路设计

提出了一种适用于伪码测距雷达的伪码跟踪环设计方法,重点对伪码跟踪环的跟踪精度和动态性能进行了分析,讨论了一种最小跟踪误差意义下的最优环路带宽确定方法。仿真结果表明伪码跟踪环跟踪精度高,对动态运动的适应能力强。     

Improved Acquisition in Phase-Locked Loops with Sawtooth Phase Detectors

Phase-locked loops are frequently used to estimate bit timing in baseband digital transmission systems. The investigation reported here examines the applicability of a frequency-sensitive phase detector to timing estimation of randomized data. A new edge-triggered sawtooth phase detector is described. The reduced magnitude of circuit-induced imperfections made possible by the new detector, in conjunction with the little-known frequency discrimination characteristic of the sawtooth detector, is shown to allow significant improvements to acquisition performance. A potential problem with this and other phase-locked loops, falselock, is studied experimentally, and techniques for avoiding it are discussed.     

基于FPGA的数字基带传输位同步恢复

提出了一种基于全数字锁相环提取数字基带传输位同步时钟的设计方案,该方案采用环路鉴相器产生误差信号控制本地位同步电路的添加/扣除门在时钟输出的脉冲序列中附加或扣除1个或几个脉冲实现同步。给出了该方案的整体电路,并经VHDL程序设计,在MaxplusⅡ环境下做了时序仿真,从仿真结果分析了设计方法可实现数字基带传输位同步时钟的提取。     

Resynchronising delay-locked loop

The delay-locked loop (DLL) is a device that is often used for PN-code tracking to synchronise direct sequence spread spectrum (DS-SS) systems. A DLL with resynchronising capability, which is more robust against loss of lock, is presented. The new scheme has two modes: a normal tracking mode and a resynchronising mode. The structure of the new loop and its function are described     

Statistical Properties of Timing Jitter in a PAM Timing Recovery Scheme

A new technique is presented for evaluating the performance of a popular type of timing recovery circuit for baseband synchronous pulse amplitude modulation (PAM) data signals. The timing circuit consists of a square-law device followed by a narrowband filter tuned to the pulse repetition frequency along with provision for reshaping the pulses entering the timing path (prefiltering). The output of the timing circuit is a nearly sinusoidal timing wave whose zero crossings indicate the appropriate sampling instants for demodulation of the PAM signal. For a random data sequence, the timing wave exhibits phase fluctuations which are strongly dependent on the pulse shapes entering the timing path and the passband shape of the narrow-band filter. Expressions for rms phase fluctuation in the timing wave as a function of the prefiltering and postfiltering characteristics of the filters preceding and following the square-law device are presented. These expressions have a form which is especially suitable for studying the case where the baseband PAM signal is band-limited to frequencies less than the pulse repetition frequency. A condition on prefiltering and postfiltering which gives error-free timing recovery is presented. Results obtained from some specific examples serve to illustrate several aspects of the timing recovery problem.     

基于高阶累积量的MPSK识别方法

提出一种不需要载波同步的调制识别方法,能够实现二进相移键控（BPSK）、正交相移键控（QPSK）和八进相移键控（8PSK）的识别。其方法是：首先对带有残余载波的基带信号进行定时抽样,计算抽样点的点积及叉积,并将点、叉积复合成一个复基带调相信号,其特点是调制阶数与原信号相同,而残余载波转换为固定相位;然后,利用这个复基带信号的四阶累积量构造分类向量进行分类。首先介绍四阶累积量的基本概念;然后给出相移键控（PSK）信号的表达形式,点叉积计算方法及其组合而成的复基带信号的形式;其次介绍识别算法;最后进行仿真分析,并考察了符号长度、定时误差及成形因子对分类性能的影响。     

低功耗低误码率的传感器网络节点芯片数字基带设计

本文针对无线传感器网络节点片上系统特点和需求,研究一种低功耗、高性能、低误码率的数字基带(Easibaseband),提出了一种复用加法器和乘法器的设计方法,实现了匹配滤波器,可节省硬件资源并提高系统性能;提出了一种自适应门限的自动增益控制方法,可配合软硬件协同的工作方式,节省接收机的功耗;提出了采用自适应门限的施密特触发器方式进行信号相位判决的方法,降低了解调误码率.本设计在Xilinx的Spartan-3E FPGA上验证并实现,测试结果表明,本收发机的数据传输率可达到111kb/s并支持ISM2.4GHz频段的射频芯片,比传统的并行滤波器节省了5/6的硬件资源,比不采用自动增益控制节省了10.8%的接收机功耗,在信噪比13dB时,误码率在10-4以下,远低于WiseNET的接收误码率.     

Noncoherent detection of coherent lightwave signals corrupted byphase noise

Waves are treated that modulate by either on-off keying (OOK) or binary frequency-shift keying (FSK) and are further impaired by additive Gaussian noise. Heterodyne detection of such a waveform produces an electronic bandpass signal, which, to ease demodulation in the presence of phase noise, is noncoherently demodulated to extract the baseband pulse stream. The treatment goes beyond previous bit error rate (BER) analyses of optical heterodyne receivers for OOK and FSK. First, there is full adherence to the standard (Brownian motion) model of phase noise. Also, the receiver structure is formulated in such a way that the probability density function of the receiver output samples can be accurately determined. This permits calculations of the additive noise and phase noise tolerable when achieving bit error rates as small as 10 ^-9. Finally, the study is comprehensive regarding the range of parameters explored. Filtering at an intermediate frequency (IF) alone, as well as IF filtering plus postdetection low-pass filtering, is considered. When the receiver parameters decision threshold (for OOK) and IF filter bandwidth are optimized, large amounts of phase noise can be accommodated with only minor increases in required signal-to-noise ratio. This is especially important when the bit rate is moderate compared to the laser linewidth     

Feedforward joint phase and timing estimation with OQPSK modulation

We propose an algorithm for joint carrier phase and timing estimation with offset quadriphase modulation (OQPSK) signaling. The derivation is based on maximum-likelihood arguments and leads to a feedforward structure that operates on signal samples taken at the bit rate. Phase and timing algorithms operate in parallel-not sequentially-and provide their estimates in a fixed time. The synchronizer is readily implemented in digital form and is particularly suitable for burst mode transmissions. Its performance is analytically assessed and verified by simulations. Comparisons are made with other methods described in the literature     

Synchronization of quadrature-quadrature phase-shift keying signals

The key synchronization aspects in the system design of a QQPSK (quadrature-quadrature phase-shift-keying) modem are addressed. The sensitivity of the data demodulator to synchronization errors is discussed, and contextually the performances of some IF and baseband carrier phase and symbol timing recovery schemes are evaluated both theoretically and by computer simulations. In particular, a fourth-power IF carrier/clock regenerator and two baseband clock recovery schemes, with and without the aid of data decisions, respectively, are taken into account. The analysis shows on the one hand the substantial robustness of QQPSK to carrier phase errors and the adequacy of the examined carrier extraction scheme. On the other hand, the remarkable sensitivity of QQPSK to symbol timing inaccuracy is stressed and the need to resort to the newly proposed decision-aided baseband clock recovery scheme is pointed out     

Simple baseband synchronisation scheme for tamed frequencymodulation

A novel carrier and clock synchronisation scheme for tamed frequency modulation is presented. It requires one complex sample per bit, like the digital Costas loop for offset in-phase and quadrature modulations, and is based on processing baseband samples of the phase of the received signal. The performance of the synchroniser is assessed by S-curves and simulated acquisition trajectories     

Variable bandwidth DPLL bit synchronizer with rapid acquisitionimplemented as a finite state machine

A digital PLL bit synchronizer with variable loop bandwidth for rapid acquisition and good tracking performance is proposed, and its performance analyzed using Markov chain techniques. Results are presented for the distributions of acquisition time and time to first bit slip in terms of state transition probabilities. For burst mode data, results for the timing error and bit error rate as a function of the preamble bit number are obtained. All results are evaluated by repeated matrix products and verified by simulation. Comparison of the variable bandwidth DPLL to a fixed bandwidth DPLL shows significantly faster acquisition for a given tracking performance     

Clock synchronization for wavelet-based multirate transmissions

This paper deals with symbol timing recovery for multirate transmission systems employing wavelets as signaling pulses either at baseband or with linear bandpass modulation. Our analysis is twofold. First, we investigate the impact of clock errors on the bit-error rate of the optimum receiver for a wavelet-based multirate signal. Second, we consider a nondata-aided maximum-likelihood clock synchronization scheme implemented as a multiple delay-locked loop. We derive a linearized loop model and assess its performance in terms of tracking jitter variance. The analytical results are contrasted with those obtained by simulation and with the relevant modified Cramer-Rao bound     

基于OFDM技术的软比特解码系统

提出了基于OFDM基带系统的软比特译码方法,该方法以Viterbi软比特译码为中心,改善传统OFDM基带系统接收端的解映射、解交织、解删余模块,使得各个模块兼容软比特判决。软判决采用3比特的量化作为数据处理单位,提高Viterbi译码的性能。该方法从解映射模块入手,将接收到的数据信号解映射为3比特量化数据,送入改进后兼容3比特量化数据的解交织模块和解删余模块。实验结果表明,对比硬比特解码,所提出的软比特解码系统在性能上有很大的提升。     

Single-chip baseband waveform generator CMOS-LSI for quadrature-type GMSK modulator

A single-chip baseband waveform generator CMOS-LSI has been fabricated for use in the quadrature-type GMSK modulator, which is suitable for application to digital mobile communications. The LSI employs digital signal processing in realising such functions as Gaussian baseband filtering and phase integration. Digital/analogue convertors and auxiliary circuits, such as an internal-clock generator and carrier frequency adjuster, are also integrated onto the same chip. The LSI operates well below a bit rate of 110 Kbit/s when the power supply voltage is 5 V.     

Digital burst mode clock recovery technique for fiber-optic systems

We present a clock recovery technique for burst mode systems that performs the functions of clock phase recovery, burst synchronization (to determine the first data bit in the burst), and timing alarm generation (to maintain bursts within their designated time slots). The method is based on the use of a correlation algorithm in which the incoming preamble containing a `0 1 0' bit sequence is sampled with multiple clock phases and correlated with stored, time delayed versions of the same sequence. The method was implemented in a 0.7 μm CMOS Application Specific Integrated Circuit (ASIC). Measurements of the phase tracking characteristics over the frequency range of 38 to 90 MHz are presented. Bit error rate measurements made using the device in a burst mode fiber-optic receiver operating at 51.84 Mb/s were also performed, where it was found that the device performed well and was able to perform clock extraction with a penalty of approximately 2 dB with respect to an ideal clock extraction system