TWFBD的浮点数编码遗传算法

近年来,有关浮点数编码遗传算法的消噪变异研究有了一定的进展,取得了一些成果。浮点数编码消噪变异的理论和方法研究一直是该领域研究的重点,需要有更新更有理论和应用价值的研究成果出现。有界域的紧小波框架用于浮点数编码消噪变异尚处于无人问津的研究领域。着重分析了有界域的紧小波框架的性质,用有界域的紧小波框架在算法中进行消噪变异操作,提出了基于有界域紧小波框架的遗传算法,并进行了实验。研究和实验结果表明,将有界域的紧小波框架用于浮点数编码消噪变异,具有可靠的理论基础,与其他方法相比,其效果也十分明显。     

Parallel algorithms for the rounding exact summation of floating point numbers

Pichat and Bohlender studied an algorithm for the rounding exact summation of floating point numbers which can be executed on any floating point arithmetic unit. We propose parallel versions of this algorithm, namely a pipeline version, an algorithm similar to the exchange methods for sorting and a tree-like algorithm, associating a tree to the sum. For all these algorithms we discuss the properties, a multiprocessor architecture should have for an efficient implementation of an algorithm without restricting us to a special architecture.     

2-Adic MRA的浮点数编码遗传算法

通过2-Adic多分辨率分析,构造正交小波基;证明所构造正交小波用于浮点数编码消噪的正确性;提出用正交小波在浮点数编码遗传算法中进行消噪变异操作,以消除浮点数编码在遗传环境中所产生的噪音对算法性能的影响;构建基于2-Adic多分辨率分析的遗传算法,并进行了实验。仿真实验表明,提出的算法可明显提高浮点数编码遗传算法的收敛速度和精度,具有较高的可靠性。     

基于小波阈值收缩消噪的浮点数编码遗传算法研究

浮点数编码具有精度高、便于高维大空间搜索的优点,在函数优化和约束优化领域明显有效于其他编码。但浮点数编码遗传算法在运行环境中产生的噪音对算法性能的影响并未引起人们的重视。传统的浮点数编码遗传算法采用的是有界随机变异,不能消除噪音对算法性能的影响。提出了基于小波阈值收缩消噪的浮点数编码遗传算法,建立滤波器,采用不同的阈值消噪取代变异操作,并进行了实验。该研究和实验结果表明,这种方法理论上是可靠的,方法上是可行的,选择适当的阈值,可明显提高算法的全局最优解精度,具有较高的稳定性。     

Optimal floating point multiplication processor for signal processing

The design of a floating point matrix- vector multiplication processor array for VLSI, which has an optimal area-time complexity product, is presented. This processor array is capable of performing the function (where n = 1,…, N) and can be applied in many digital signal processing applications, by simply changing the matrix coefficients stored in that array. Each N-bit mantissa, M-bit exponent (N, M) processor element of the array comprises a mantissa multiplier/adder circuit and hardware to handle the floating point control. The multiplier/adder circuit is implemented by a new optimal algorithm, which is regular, recursive and fast. Secondly, the algorithm offers a highly local and regular interconnection network, which is a fundamental requirement in VLSI circuit design methodology.     

Distributions of floating point numbers

The logarithmic distribution is commonly used to model mantissae of floating point numbers. It is known that floating point products of logarithmically distributed mantissae are logarithmically distributed, while floating point sums are not. In this paper a distribution for floating point sums is derived, and for a special case of logarithmically distributed mantissae the deviation of this distribution from the logarithmic distribution is determined.     

Continuous-time system representation with exact macro-difference expressions

A macro-difference equation representation is proposed which is a mixture of finite-difference quotients and integrals over finite time intervals. The choice of the micro or sampling interval length (for the numerical integration accuracy and representation bandwidth) and the choice of the macro interval length (for numerical conditioning/accuracy of the difference quotients and of the resulting equations) are independent. This approach does not need the assumption (which in practical situations is quite unnatural) of zero initial conditions.     

Fast exact shortest distance queries for massive point clouds

This paper describes a new efficient algorithm for the rapid computation of exact shortest distances between a point cloud and another object (e.g. triangulated, point-based, etc.) in three dimensions. It extends the work presented in Eriksson and Shellshear (2014) where only approximate distances were computed on a simplification of a massive point cloud. Here, the fast computation of the exact shortest distance is achieved by pruning large subsets of the point cloud known not to be closest to the other object. The approach works for massive point clouds even with a small amount of RAM and is able to provide real time performance. Given a standard PC with only 8GB of RAM, this resulted in real-time shortest distance computations of 15 frames per second for a point cloud having 1 billion points in three dimensions.     

基于FPGA的高精度数字移相低频正弦波发生器设计

文章介绍了基于FPGA和数字频率合成技术,利用VHDL编制程序并下载至Xilinx公司的SpartanⅡ系列XC2S100E-6PQ208FPAG芯片上,加以简单的外围电路,构成了高精度数字式移相正弦波信号发生器。该装置能够产生频率、相位、幅度均可数字式预置并可调节的两路正弦波信号,相位差范围为0～359°,步进为1°。     

A floating point conversion algorithm for mixed precision computations

The floating point number is the most commonly used real number representation for digital computations due to its high precision characteristics. It is used on computers and on single chip applications such as DSP chips. Double precision (64-bit) representations allow for a wider range of real numbers to be denoted. However, single precision (32-bit) operations are more efficient. Recently, there has been an increasing interest in mixed precision computations which take advantage of single precision efficiency on 64-bit numbers. This calls for the ability to interchange between the two formats. In this paper, an algorithm that converts floating point numbers from 64- to 32-bit representations is presented. The algorithm was implemented as a Verilog code and tested on field programmable gate array (FPGA) using the Quartus II DE2 board and Agilent 16821A portable logic analyzer. Results indicate that the algorithm can perform the conversion reliably and accurately within a constant execution time of 25 ns with a 20 MHz clock frequency regardless of the number being converted.     

Loop invariants in floating point algorithms

It will be shown that by using directed roundings resp. enclosure sets for the exact values, the loop conditions and loop invariants of numerical algorithms can be generalized for computing in a discrete screen. On this way, in spite of rounding errors, it is possible to verify the received results. Thereby only inherent properties of the algorithms are used, which moreover guarantee that the loops terminate.     

Layer-based representation of polyhedrons for point containment tests

This paper presents the layer-based representation of polyhedrons and its use for point-in-polyhedron tests. In the representation, the facets and edges of a polyhedron are sequentially arranged, and so, the binary search algorithm is efficiently used to speed up inclusion tests. In comparison with conventional representation for polyhedrons, the layer-based representation that we propose greatly reduces the storage requirement because it represents much information implicitly though it still has a storage complexity O(n). It is simple to implement and robust for inclusion tests because many singularities are erased in constructing the layer-based representation. By incorporating an octree structure for organizing polyhedrons, our approach can run at a speed comparable with Binary space partitioning (BSP)-based inclusion tests and, at the same time, greatly reduce storage and preprocessing time in treating large polyhedrons. We have developed an efficient solution for point-in-polyhedron tests, with the time complexity varying between O(n) and O(logn), depending on the polyhedron shape and the constructed representation, and less than O(log³n) in most cases. The time complexity of preprocess is between O(n) and O(n²), varying with polyhedrons, where n is the edge number of a polyhedron.     

Decimal addition on FPGA based on a mixed BCD/excess-6 representation

Decimal arithmetic has recovered the attention in the field of computer arithmetic due to decimal precision requirements of application domains like financial, commercial and internet. In this paper, we propose a new decimal adder on FPGA based on a mixed BCD/excess-6 representation that improves the state-of-the-art decimal adders targeting high-end FPGAs. Using the proposed decimal adder, a multioperand adder and a mixed binary/decimal adder are also proposed. The results show that the new decimal adder is very efficient improving the area and delay of previous state of the art decimal adders, multioperand decimal addition and binary/decimal addition.     

Gabor transform of time-varying systems: exact representation andapproximation

Approximate modeling of discrete-time linear time-varying systems is studied based on a representation of linear systems in the Gabor time-frequency space. The time-varying system is assumed to be given in input-output or kernel representation. This representation has previously received attention because of its applicability in frozen-time analysis and design of optimal control for time-varying systems but requires a large number of coefficients. Motivated by its application to signal analysis, the Gabor transform is considered as a tool for the representation and approximation of linear time-variant systems. In order to show the main results, the class of systems considered is restricted to the one usually considered in the frozen-time approach. An example is included to illustrate the potential application of the technique     

Some models of error in floating point multiplication

New results are given on error in floating point multiplication. Certain choices of the base minimize the mean multiplicative error. These choices depend on which measure of error is selected. Some measures are included which were not in earlier studies. Some of the results have application to computer design.