A low EVM zero-IF RF transmitter for cognitive radio application

A zero-IF transmitter for Cognitive Radio (CR) application is presented. To effectively reduce the interference between Power Amplifier (PA) and Voltage Controlled Oscillator (VCO), two VCOs are adopted, one is 450 MHz and the other is from 1148 MHz to 1252 MHz with an 8 MHz step, so the frequency of them are different from the operational frequency of PA. The Local Oscillator (LO) of the modulator generated by mixing the signals of the two VCOs has a low phase noise of −82 dBc/Hz with an offset of 1 kHz. The measurement result of the transmitter shows that the Adjacent Channel Power Ratio (ACPR) is less than −47.5 dBc at 27 dBm output, and the Error Vector Magnitude (EVM) is less than 1.7%.     

Ultra-Wideband, Low-Power, Inductorless, 3.1�C4.8?GHz, CMOS VCO

A low-power, inductorless, UWB CMOS voltage controlled oscillator is designed in 0.18 μm CMOS technology targeting to a UWBFM transmitter application. The VCO is a Double-Cross-Coupled Multivibrator and generates output frequencies ranging from 1.55 GHz to 2.4 GHz. A low-power frequency doubler based on a Gilbert cell, which operates in weak inversion, doubles the VCO tuning range from 3.1 GHz to 4.8 GHz. The proportionality between the oscillation frequency and the bias current is avoided in this case for the entire achieved tuning range resulting in a low-power design. The selected architecture provides high suppression, over 45 dB, for the 1^st and 3^rd harmonics, while enabling high-frequency operation and conversion gain due to the unbalanced structure and the single-ended output. The proposed VCO draws 4 mA from a 1.8 V supply, it has a phase noise of −76.7 dBc/Hz at 1 MHz offset from the center frequency, while it exhibits a very high ratio of tuning range (43%) over power consumption equal to 7.76 dB.     

用于434/868MHz FSK/OOK CMOS发射机的锁相环设计

一种可输出434/868MHz信号的Σ-Δ分数分频锁相环在0.35μmCMOS工艺中集成。该发射机系统采用直接调制锁相环分频比的方式实现FSK调制,OOK的调制则通过功率预放大器的开-关实现。为了降低芯片的成本和功耗,发射机采用了电流数字可控的压控振荡器(VCO),以及片上双端-单端转换电路,并对分频器的功耗设计进行研究。经测试表明,锁相环在868MHz载波频偏为10kHz、100kHz和3MHz处的相位噪声分别为-75dBc/Hz、-104dBc/Hz和-131dBc/Hz,其中的VCO在100kHz频偏处的相位噪声为-108dBc/Hz。在发送模式时,100kHz相邻信道上的功率与载波功率之比小于-50dB。在直流电压2.5V的工作条件下,锁相环的电流为12.5mA,包括功率预放大器和锁相环在内的发送机总面积为2mm2。     

Ultra wideband, low-power, 3-5.6 GHz, CMOS voltage-controlled oscillator

In this paper, a low-power inductorless ultra wideband (UWB) CMOS voltage-controlled oscillator is designed in TSMC 0.18 μm CMOS technology as a part of a ultra wideband FM (UWBFM) transmitter. The VCO includes a current-controlled oscillator (CCO) which generates output frequencies between 1.5 and 2.8 GHz and a voltage-to-current (V-to-I) converter. A low-power frequency doubler based on a Gilbert cell, which operates in weak inversion, doubles the VCO tuning range achieving oscillation frequencies between 3 and 5.6 GHz. Thus, the well-known proportionality between the oscillation frequency and the bias tuning current in CCOs is avoided for the entire achieved tuning range, resulting in a lower power design. The employed architecture provides high suppression, over 45 dB, of the 1st and 3rd harmonics, while enabling high-frequency operation and conversion gain due to the unbalanced structure and the single-ended output. The current consumption is 5 mA at a supply voltage of 1.8 V. The VCO exhibits a phase noise of −80.56 dBc/Hz at 1 MHz frequency offset from the carrier and a very high ratio of tuning range (60.4%) over power consumption equal to 8.26 dB which is essential for a UWBFM transmitter.     

Low-Voltage Direct I/Q-Modulator and Power Amplifier for 2-GHz Transmitter

An integrated 1–;2 GHz GaAs MESFET direct conversionI/Q-modulator and a power amplifier operating at a supply voltage of 3 Vhave been designed and fabricated. The core of the I/Q-modulator, a 90°phase shifter, is realized with a 2-section 4-phase RC-filter. TheI/Q-modulator converts a baseband signal directly to the 1.1–;2.0 GHzRF frequency. Without any external adjustment, the carrier rejection and thesideband rejection are better than 30 dBc and 26 dBc, respectively. Theoutput power of the modulator is – 6.5 dBm at a LO frequency of 1.75GHz and for a baseband signal level of 180 mV (100 kHz). The powerconsumption of the I/Q-modulator is 200 mW at 3-V supply voltage. The 3-Vpower amplifier is a three stage amplifier having the first two stagesbiased to class A and the last stage to class AB. The maximum output powerof the three stage MESFET power amplifier is +27 dBm and the maximumavailable power gain is 32 dB. An external output matching circuit is usedto feed the output to a 50 load. The die sizes of the modulator andpower amplifier are 2.7 x 1.3mm ² and 2.0 x 2.0mm², respectively. The circuits have been processed withGEC-Marconi GaAs F20 process.     

A PLL based WSN transmitter and I/Q LO signal generator at 430–435 MHz

A fully integrated Phase-Locked Loop (PLL) based transmitter and I/Q Local Oscillating (LO) signal generator used for half-duplex Wireless Sensor Networks (WSN) transceivers is proposed. Instead of one 430–435 MHz PLL for frequency synthesizing, a 1.72–1.74 GHz PLL is designed together with a 1/4 frequency divider. Then the chip area of the inductors in the Voltage-Controlled Oscillator (VCO) is decreased to about 1/16, and I/Q dual-path LO signals can be obtained without additional power consumption. A Gray-code controlled prescaler is proposed to avoid the glitches and uncertain states, and then the frequency dividing accuracy is improved by 17%. A Gauss Frequency Shift Keying (GFSK) transmitter with a pipeline modulator is proposed, the 1st and 2nd Adjacent Channel Power Ratio (ACPR) are −19.9 and −20.7 dBc, respectively. A mathematical spur model of 1/4 frequency dividers is built here, and then a low-spur 1/4 frequency divider composed of our proposed improved Current Mode Logic (CML) latches is designed. The testing results show that the reference spurs are −61.2 dBc@20 MHz and −57.7 dBc@40 MHz at the output of the PLL, and −70.5 dBc@20 MHz and −66.6 dBc@40 MHz at the output of our 1/4 divider. With 2.6-mW power consumption, our proposed 1/4 frequency divider has a phase-noise contribution of only 0.5 dBc/Hz@500 kHz and 0.2 dBc/Hz@1 MHz.     

A 1.83 GHz 28.5 dBm CMOS Power Up-Mixer

A power up-mixer is proposed in this letter. A merged CMOS linear power amplifier (PA) and mixer allows low current consumption and smaller chip size than a conventional integrated transmitter including a mixer and a CMOS linear PA. The chip is fabricated in a 0.18 $mu{rm m}$ CMOS process and in an integrated-passive-device. Measurements show a drain efficiency of 27% at 27.2 dBm of 1 dB compression point (P1dB) output power from 1.75 to 1.95 GHz. Power conversion gain is 26.4 dB and LO leakage is $-$43 dBc.      

A Wide Tuning Range Voltage Controlled Oscillator with a High Tunable Active Inductor

This paper presents a wide tuning range CMOS voltage controlled oscillator (VCO) with a high-tunable active inductor circuit. In this VCO circuit, the coarse frequency is achieved by tuning the integrated active inductor circuit. The VCO circuit is designed in 0.18  \(\upmu \hbox {m}\) CMOS process and simulated with Cadence Spectra. The simulation results show the frequency tuning range from 120 MHz to 2 GHz resulting in a tuning range of 94 %. The phase noise variation is from \(-\) 80 to \(-\) 90 dBc/Hz at a 1 MHz frequency offset, and output power variation is from \(-\) 4.7 to \(+\) 11.5 dBm. The active inductor power consumption is 2.2 mW and the total power dissipation is 7 mW from a 1.8 V DC power supply. By comparing the proposed VCO circuit with the general VCO topology, the results show that this VCO architecture by using the novel, high-tunable and low power active inductor circuit, presents a better performance regarding low chip size, low power consumption, high tuning range and high output power.     

A 98/196 GHz Low Phase Noise Voltage Controlled Oscillator With a Mode Selector Using a 90 nm CMOS Process

A 98/196 GHz low phase noise voltage controlled oscillator (VCO) with a fundamental/push-push mode selector using a 90 nm CMOS process is presented in this letter. An innovative concept of the VCO with the mode selector is proposed to switch the fundamental or second harmonic to the RF output. The VCO demonstrates a fundamental frequency of up to 98 GHz with an output power of greater than $-8~{rm dBm}$. The phase noise of the VCO is better than $-100.8~{rm dBc}/{rm Hz}$ at 1 MHz offset frequency, and its figure-of-merit is better than $-186~{rm dBc}/{rm Hz}$. Moreover, the output frequency of the work is up to 196 GHz with a fundamental suppression of greater than $-30~{rm dBc}$ as the VCO is operated in push-push mode.      

Single-VCO multi-band DTV frequency synthesizer with a divide-by-3 frequency divider for quadrature signal generation

A multi-band frequency synthesizer for In-phase and Quadrature (I/Q) LO signal generation in Digital TV tuners is presented. Using divisor numbers other than powers of 2 (2 ⁿ ) for quadrature generation, reduces the required frequency range of the VCO, hence the number of VCO circuits, in multi-band frequency synthesizers. In the proposed synthesizer, VHF, UHF and L-band frequencies are covered with only one VCO. This is achieved by using a novel divide-by-3 circuit which produces precise I/Q LO signals. The VCO tuning range in this design is 2,400–3,632 MHz which is covered by a 6-bit switched-capacitor bank. A fast adaptive frequency calibration block selects the closest VCO frequency to the target frequency by setting the coarse-tuning code prior to the start of phase lock. A programmable charge pump is used to reduce variations in PLL characteristics over the frequency range. The synthesizer has been fabricated in a 0.18 μm CMOS technology and the die area is 1.7 × 1.6 mm². It consumes 27 mA from a 1.8 V power supply. Measurement results show operation of the proposed divide-by-3 circuit over the entire VCO frequency range. The synthesizer quadrature output phase noise for UHF and VHF bands is <−131dBc/Hz at 1.45 MHz offset.     

A 2.5 V, 10 GHz Fully Integrated LC-VCO with Integrated High-Q Inductor and 30% Tuning Range

A 10 GHz fully integrated Voltage Controlled Oscillator is presented. A 29.7% tuning range is achieved from a 2.5 V power supply. The phase noise is –113 dBc/Hz at 600 kHz and –127 dBc/Hz at 3 MHz. The VCO is implemented in a 0.25 m 4 metal layer standard CMOS technology. This design will be used to discuss design and layout issues for high frequency LC-oscillators. A thorough analysis will be made of the contribution of the different building blocks to the performance of the total circuit.     

具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.     

Dual-band transmitters using digitally predistorted frequency multipliers for reconfigurable radios

Two methods for reconfigurable transmitters using frequency multipliers in conjunction with digital predistortion linearizers are developed. One method utilizes a circuit topology that can be switched between a fundamental-mode in-phase combined amplifier, and a push-push frequency doubler using input phasing. Investigation to maximize output harmonics out of regular power amplifiers (PAs) was performed, and the implementation of the device was successful for the amplifier- and doubler-mode operation. To satisfy optimal load-line conditions for the operation in both modes, a bi-tuned output-combining technique is introduced as well. Measurement results indicate that the circuit is able to transmit 28 dBm of output power at 900 MHz in the amplifier mode, and 22 dBm at 1800 MHz in the doubler mode. In combination with predistortion linearization, the reconfigurable transmitter was shown to be capable of amplifying IS-95B code-division multiple-access (CDMA) signals with an adjacent-channel power ratio (ACPR) up to -58dBc/30kHz. The second suggested method utilizes a fundamental-frequency PA followed by a varactor multiplier that can be bypassed with an RF switch. A varactor-diode doubler with a saturated conversion loss of 1.3 dB was built and tested. Using predistortion linearization techniques on both the PA and doubler, an ACPR of -53dBc/30kHz at 885-kHz offset was achieved for a CDMA signal transmitted at 1850 MHz.     

A CMOS RF Polar Transmitter of a UHF Mobile RFID Reader for High Power Efficiency

A CMOS radio frequency (RF) polar transmitter architecture for a UHF (860–960 MHz) RF identification (RFID) reader is proposed, which consists of a switch-mode CMOS power amplifier (PA) and an analog pulse-shaping filter implemented in 0.25-$mu$ m CMOS process. The amplitude modulation of a amplitude shift keying signal is performed by simply switching the common gate transistor of a cascode power amplifier. Extremely low power consumption is achieved when the PA is switched off. The power efficiency of the transmitter is enhanced not only by using switching power amplifier but also by employing this architecture.      

A 925–960 MHz I/Q modulator in a 8 GHz 1.2 μm BiCMOS process

An integrated I/Q modulator has been implemented in a commercially available 8 GHz 1.2 m double metal double poly BiCMOS process. The circuit converts baseband signals from 60 kHz to 500 kHz directly to a carrier frequency which can be selected between 925 MHz and 960 MHz. It has an internal 90° phase shifter for the LO signal, the phase shift of which can be adjusted automatically using a control signal generated inside the circuit. The size of the circuit is 2.9 mm×2.9 mm and it consumes about 50 mA. Measurements suggest that the specified LO suppression and image rejection of 35 dBc can be achieved under optimal operating conditions.     

A low local input 1.9 GHz Si-bipolar quadrature modulator with noadjustment

A 1.9 GHz quadrature modulator with an onchip 90° phase-shifter was fabricated using a silicon bipolar technology. This paper investigates error factors caused by a limiter amplifier. It is found that a gain enhancement technique in a phase-shifter circuit is effective in realizing an adjustment free quadrature modulator; we propose a new high-gain phase shifter circuit for this purpose. This technique employs a current mode interface and an on-chip inductor. An image-rejection ratio of over 45 dBc and a carrier feedthrough of below -40 dBc were attained at -15 dBm local oscillator power. This quadrature modulator operates at 2.7 V supply voltage. The operating frequency ranges from 1.2 GHz to 2.3 GHz. The die size of the quadrature modulator IC is 2.49 mm×2.14 mm     

A Novel Broad-Band MMIC VCO Using an Active Inductor

This paper proposes a novel broad-band MMIC VCO using an active inductor. This VCO is composed of a serial resonant circuit, in which the capacitor is in series with an active inductor that has a constant negative resistance. Since the inductance value of this active inductor is inversely proportional to the square of the transconductance and can vary widely with the FETs gate bias control, a broad-band oscillation tuning range can be obtained. Furthermore, since this active inductor can generate a constant negative resistance of more than 50 , the proposed VCO can oscillate against a 50- output load immediately without using additional impedance transformers. We have fabricated the VCO using a GaAs MESFET process. A frequency tuning range of more than 50%, from 1.56 to 2.85 GHz, with an output power of 4.4±1.0 dBm, was obtained. With a carrier of 2.07 GHz, the phase noise at 1-MHz offset was less than –110 dBc/Hz. The chip size was less than 0.61 mm², and the power consumption was 80 mW. This broad-band analog design can be used at microwave frequencies in PLL applications as a compact alternative to other types of oscillator circuits.     

A Dual-Band CMOS Voltage-Controlled Oscillator Implemented With Dual-Resonance LC Tank

A new fully integrated, dual-band CMOS voltage controlled oscillator (VCO) is presented. The VCO is composed of n-core cross-coupled Colpitts VCOs and was implemented in 0.18 $mu$m CMOS technology with 0.8 V supply voltage. The circuit allows the VCO to operate at two resonant frequencies with a common LC tank. The VCO has two control inputs, one for continuous control of the output frequency and one for band switching. This VCO is configured with 5 GHz and 12 GHz frequency bands with differential outputs. The dual-band VCO operates in 4.78–5.19 GHz and 12.19–12.61 GHz. The phase noises of the VCO operating at 5.11 and 12.2 GHz are ${-}117.16$ dBc/Hz and ${-}112.15$ dBc/Hz at 1 MHz offset, respectively, while the VCO draws 3.2/2.72 mA and 2.56/2.18 mW consumption at low/high frequency band from a 0.8 V supply.      

A low power consumption CMOS differential-ring VCO for a wireless sensor

This paper describes a new three-stage voltage controlled ring oscillator (VCO) based on 0.35???m standard CMOS technology. The VCO was designed for a transmitter operating in the 863?C870?MHz European band for wireless sensor applications. The transmitter is designed for binary frequency-shift keying (BFSK) modulation, communicating a maximum data rate of 20?kb/s. In addition to the VCO, the transmitter combines a BFSK modulator, an up conversion mixer, a power amplifier and an 863?C870?MHz band pass filter. The modulator uses the frequency hopping spread spectrum and it is intended for short range wireless applications, such as wireless sensor networks. The oscillation frequency of the VCO is controlled by a voltage V_CTRL. Simulation results of the fully differential VCO with positive feedback show that the estimated power consumption, at desired oscillation frequency and under a supply voltage of 3.3?V, is only 7.48?mW. The proposed VCO exhibits a phase noise lower than ?126?dBc/Hz at 10?MHz offset frequency.     

A CMOS Offset Phase Locked Loop for a GSM Transmitter

This paper describes a CMOS offset phase locked loop (OPLL) for a global system for mobile communications (GSM) transmitter. The OPLL is a PLL with a down-conversion mixer in the feedback path and is used in the transmit (Tx) path as a frequency converter. It has a tracking bandpass filter characteristic in such a way that the OPLL can suppress the noise in the GSM receiving band (Tx noise) without a duplexer. When the loop bandwidth of the OPLL was 1.0 MHz, the Tx noise level of –163.5 dBc/Hz, the phase error of 0.66° rms, and the settling time of 40 s were achieved. The IC was implemented by using 0.35-m CMOS process. It takes 860 m×620 m of total chip area and consumes 17.6 mA with a 3.0 V power supply.