A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers

An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-/spl mu/m 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7/spl plusmn/0.8 dB power gain with a good input match (S11<-9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets.     

A 24-GHz CMOS front-end

This paper reports the first 24-GHz CMOS front-end in a 0.18-/spl mu/m process. It consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24 GHz to an IF of 5 GHz. It has a power gain of 27.5 dB and an overall noise figure of 7.7 dB with an input return loss, S/sub 11/ of -21 dB consuming 20 mA from a 1.5-V supply. The LNA achieves a power gain of 15 dB and a noise figure of 6 dB on 16 mA of dc current. The LNA's input stage utilizes a common-gate with resistive feedthrough topology. The performance analysis of this topology predicts the experimental results with good accuracy.     

Design of a fully differential CMOS LNA for 3.1-10.6 GHz UWB communication systems

A fully differential complementary metal oxide semiconductor （CMOS） low noise amplifier （LNA） for 3.1-10.6 GHz ultra-wideband （UWB） communication systems is presented. The LNA adopts capacitive cross-coupling common-gate （CG） topology to achieve wideband input matching and low noise figure （NF）. Inductive series-peaking is used for the LNA to obtain broadband flat gain in the whole 3.1-10.6 GHz band. Designed in 0.18 um CMOS technology, the LNA achieves an NF of 3.1-4.7 dB, an Sll of less than -10 dB, an S21 of 10.3 dB with ±0.4 dB fluctuation, and an input 3rd interception point （IIP3） of -5.1 dBm, while the current consumption is only 4.8 mA from a 1.8 V power supply. The chip area of the LNA is 1×0.94 mm^2.     

Design of a Sub-mW 960-MHz UWB CMOS LNA

This paper presents a sub-mW ultra-wideband (UWB) fully differential CMOS low-noise amplifier (LNA) operating below 960 MHz for sensor network applications. By utilizing both nMOS and pMOS transistors to boost the transconductance, coupling the input signals to the back-gates of the transistors, and combining the common-gate and shunt-feedback topologies, the LNA achieves 13 dB of power gain, a 3.6 dB minimum noise figure, and -10 dBm of IIP3 with only 0.72 mW of power consumption from a 1.2 V supply     

A 5.2-GHz LNA in 0.35-/spl mu/m CMOS utilizing inter-stage series resonance and optimizing the substrate resistance

A current-reused two-stage low-noise amplifier (LNA) topology is proposed, which adopts a series inter-stage resonance and optimized substrate resistance of individual transistors. The characteristics of the series inter-stage resonance in gain enhancement are analyzed and compared with other alternatives. The contradicting effects of substrate resistance on common-source and common-gate amplifiers are analyzed and proposed guidelines for high-gain operation. The LNA is implemented based on a 0.35-/spl mu/m CMOS technology for 5.2-GHz wireless LAN applications. Measurements show 19.3dB of power gain, 2.45 dB of noise figure, and 13.2 dBm of output IP3, respectively, for the dc power supply of 8 mA and 3.3 V.     

A low-power and high-gain fully integrated CMOS LNA

In this paper, we present the design of a fully integrated CMOS low noise amplifier (LNA) with on-chip spiral inductors in 0.18 μm CMOS technology for 2.4 GHz frequency range. Using cascode configuration, lower power consumption with higher voltage and power gain are achieved. In this configuration, we managed to have a good trade off among low noise, high gain, and stability. Using common-gate (CG) configuration, we reduced the parasitic effects of C_gd and therefore alleviated the stability and linearity of the amplifier. This configuration provides more reverse isolation that is also important in LNA design. The LNA presented here offers a good noise performance. Complete simulation analysis of the circuit results in center frequency of 2.4 GHz, with 37.6 dB voltage gain, 2.3 dB noise figure (NF), 50 Ω input impedance, 450 MHz 3 dB power bandwidth, 11.2 dB power gain (S₂₁), high reverse isolation (S₁₂)<−60 dB, while dissipating 2.7 mW at 1.8 V power supply.     

Generating all two-MOS-transistor amplifiers leads to new wide-bandLNAs

This paper presents a methodology that systematically generates all 2-MOS-transistor wide-band amplifiers, assuming that MOSFET is exploited as a voltage-controlled current source. This leads to new circuits. Their gain and noise factor have been compared to well-known wide-band amplifiers. One of the new circuits appears to have a relatively low noise factor, which is also gain independent. Based on this new circuit, a 50-900 MHz variable-gain wide-band LNA has been designed in 0.35-μm CMOS. Measurements show a noise figure between 4.3 and 4.9 dB for gains from 6 to 11 dB. These values are more than 2 dB lower than the noise figure of the wide-band common-gate LNA for the same input matching, power consumption, and voltage gain. IIP2 and IIP3 are better than 23.5 and 14.5 dBm, respectively, while the LNA drains only 1.5 mA at 3.3 V     

1.5-6GHz增益和噪声系数稳定的两级超宽带CMOS低噪声放大器设计与性能模拟

 针对UWB应用设计实现了一个1.5-6GHz的两级CMOS低噪声放大器(LNA). 通过引入共栅(CG)和共源(CS)结构以获得宽范围内的输入匹配,采用电流镜和峰化电感进行电流复用,所提出的LNA实现了非常平坦化的功率增益和噪声系数(NF). 经标准0.18μm CMOS工艺实现后,版图后模拟结果表明在1.5-5GHz频率范围内功率增益(S21)为11.45±0.05dB,在2-6GHz频率范围内噪声系数(NF)为5.15±0.05dB,输入损耗(S11)小于-18dB. 在5GHz时,模拟得到的三阶交调点(IIP3)为-7dBm,1dB压缩点为-5dBm.在1.8V电源电压下,LNA消耗6mA的电流,版图实现面积仅为0.62mm^2.     

A Highly Linear Wideband CMOS Low-Noise Amplifier Based on Current Amplification for Digital TV Tuner Applications

A differential wideband low-noise amplifier (LNA) based on the current amplification scheme is presented for digital TV tuners. In order to highly improve the linearity and exploit the noise cancellation, a common-gate stage with positive current feedback is integrated in parallel with a common-source stage using the current mirror amplifier. The proposed 0.18-mum CMOS LNA exhibits a power gain of 20.5 dB, an IIP3 of 2.7 dBm, an IIP2 of 43 dBm, and an average noise figure of 3.3 dB with 32.4 mW power consumption at a 1.8-V power supply and 0.12 mm² area.     

Low power LNA using the MOSFETs in moderate inversion

This paper presents an integrated complementary metal oxide semiconductor (CMOS) low power low noise amplifier (LNA) for global positioning system (GPS) receivers.To achieve low power dissipation,the MOS transistors in the proposed LNA are biased in moderate inversion region.It is implemented by SMIC 180 nm 1P6M CMOS process.The experiment results show that a gain of 12.14 dB@1.57 GHz is achieved with low noise figure (NF) of 1.62 dB.The power consumption of the circuit is 1.5 mW at supply voltage of 1.8 V.The ratio of gain to dc power consumption is 8 dB/mW.The size of the LNA is only 980μm× 720μm including the pads.     

An Ultra-Wide-Band 0.4–10-GHz LNA in 0.18-μm CMOS

A two-stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. With the common-gate configuration employed as the input stage, the broad-band input matching is obtained and the noise does not rise rapidly at higher frequency. By combining the common-gate and common-source stages, the broad-band characteristic and small area are achieved by using two inductors. This LNA has been fabricated in a 0.18-mum CMOS process. The measured power gain is 11.2-12.4 dB and noise figure is 4.4-6.5 dB with -3-dB bandwidth of 0.4-10 GHz. The measured IIP3 is -6 dBm at 6 GHz. It consumes 12 mW from a 1.8-V supply voltage and occupies only 0.42 mm²     

A 40-GHz Low-Noise Amplifier With a Positive-Feedback Network in 0.18-$mu{hbox{m}}$ CMOS

A novel circuit topology for a CMOS millimeter-wave low-noise amplifier (LNA) is presented in this paper. By adopting a positive-feedback network at the common-gate transistor of the input cascode stage, the small-signal gain can be effectively boosted, facilitating circuit operations at the higher frequency bands. In addition, $LC$ ladders are utilized as the inter-stage matching for the cascaded amplifiers such that an enhanced bandwidth can be achieved. Using a standard 0.18-$mu{hbox{m}}$ CMOS process, the proposed LNA is implemented for demonstration. At the center frequency of 40 GHz, the fabricated circuit exhibits a gain of 15 dB and a noise figure of 7.5 dB, while the return losses are better than 10 dB within the 3-dB bandwidth of 4 GHz. Operated at a 1.8-V supply, the LNA consumes a dc power of 36 mW.      

Design of Full Band UWB Common-Gate LNA

A two-stage, common-gate in cascade with cascode, ultra wideband low noise amplifier (LNA) topology is proposed for 3.1 to 10.5 GHz full band application. The common-gate first stage is adopted and optimized for low noise figure (NF) at high frequencies. The LNA implemented in 0.18 mum CMOS shows more than 10 dB input return loss, maximum gain of 16 dB, and NF of 3.8~4.0 dB over the full frequency band while dissipating 5.3 mA from 1.8 V supply.     

A Low-Noise Amplifier With Tunable Interference Rejection for 3.1- to 10.6-GHz UWB Systems

An ultrawideband common-gate low noise amplifier with tunable interference rejection is presented. The proposed LNA embeds a tunable active notch filter to eliminate interferer at 5-GHz WLAN and employs a common-gate input stage and dual-resonant loads for wideband implementation. This LNA has been fabricated in a 0.18-$mu$m CMOS process. The measured maximum power gain is 13.2 dB and noise figure is 4.5–6.2 dB with bandwidth of 3.1–10.6 GHz. The interferer rejection is 8.2 dB compared to the maximum gain and 7.6 dB noise figure at 5.2 GHz , respectively. The measured input P1dB is ${-} $11 dBm at 10.3 GHz. It consumes 12.8 mA from 1.8-V supply voltage.      

2.4GHz可变增益CMOS低噪声放大器设计

设计了一款工作在2.4GHz的可变增益CMOS低噪声放大器,电路采用HJKJ0.18μm CMOS工艺实现。测试结果表明,最高增益为11.5dB,此时电路的噪声系数小于3dB,增益变化范围为0～11.5dB。在1.8V电压下,电路工作电流为3mA。     

A 5.7-GHz 0.18-/spl mu/m CMOS gain-controlled differential LNA with current reuse for WLAN receiver

This letter presents a 5.7 GHz 0.18 /spl mu/m CMOS gain-controlled differential LNA for an IEEE 802.11a WLAN application. The differential LNA, fabricated with the 0.18 /spl mu/m 1P6M standard CMOS process, uses a current-reuse technology to increase linear gain and save power consumption. The circuit measurement is performed using an FR-4 PCB test fixture. The LNA exhibits a noise figure of 3.7 dB, linear gain of 12.5 dB, P/sub 1dB/ of -11 dBm, and gain tuning range of 6.9 dB. The power consumption is 14.4 mW at V/sub DD/=1.8 V.     

A new CMOS wideband low noise amplifier with gain control

In this paper, a new CMOS wideband low noise amplifier (LNA) is proposed that is operated within a range of 470 MHz-3 GHz with current reuse, mirror bias and a source inductive degeneration technique. A two-stage topology is adopted to implement the LNA based on the TSMC 0.18-μm RF CMOS process. Traditional wideband LNAs suffer from a fundamental trade-off in noise figure (NF), gain and source impedance matching. Therefore, we propose a new LNA which obtains good NF and gain flatness performance by integrating two kinds of wideband matching techniques and a two-stage topology. The new LNA can also achieve a tunable gain at different power consumption conditions. The measurement results at the maximum power consumption mode show that the gain is between 11.3 and 13.6 dB, the NF is less than 2.5 dB, and the third-order intercept point (IIP3) is about −3.5 dBm. The LNA consumes maximum power at about 27 mW with a 1.8 V power supply. The core area is 0.55×0.95 mm².     

A dual mode 2.4-GHz CMOS low noise amplifier employing body biasing

This paper presents a dual mode CMOS low noise amplifier (LNA) suitable for Worldwide Interoperability for Microwave Access applications, at 2.4?GHz. The design concept is based on body biasing. An off chip Digital to Analog Converter is used to generate the proper body bias voltage to control the LNA gain and linearity. Measurement results show that in the high gain mode, for V _BS?=?0.3?V, the cascode LNA, implemented in a 0.13???m CMOS standard process, exhibits a 14?dB power gain, a 3.6?dB noise figure (NF) and ?4.6?dBm of third order intercept point (IIP3) for a 4?mA current consumption under 1?V supply. Tuning V _BS to ?0.55?V, switches the LNA into the low gain mode. It achieves 8.6?dB power gain, 6.2?dB NF and 6?dBm IIP3 under a constrained power consumption of 1.7?mW.     

A High Gain and Low Supply Voltage LNA for the Direct Conversion Application With 4-KV HBM ESD Protection in 90-nm RF CMOS

A 2.4-GHz low noise amplifier (LNA) for the direct conversion application with high power gain, low supply voltage and plusmn4 KV human body model (HBM) electrostatic discharge (ESD) protection level implemented by a 90-nm RF CMOS technology is demonstrated. At 12.9 mA of current consumption with a supply voltage of 1.0 V, the LNA delivers a power gain of 21.9 dB and the noise figure (NF) of 3.2 dB, while maintaining the input and output return losses below -11 dB and -18.3 dB, respectively. The power gain and NF are only 0.2 dB lower and 0.64 dB higher than those of LNA without ESD protection     

CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits

A tuned-input tuned-output (TITO) VCO utilizes two resonant-tanks to achieve a low measured phase noise of 130.5 dBc/Hz @ 1 MHz offset from 2.5 GHz center frequency. Improvement in phase noise is achieved with comparable power consumption and tuning range compared to a cross-coupled VCO topology. A TITO cell similar to that in the VCO is used as a common-source amplifier in a current-reuse configuration cascaded with a -boosted common-gate amplifier to realize a high gain (20 dB), low power (2.7 mW) LNA. A technique to improve the linearity of the current-reuse LNA is also presented.