Performance of GaAs JFET at a cryogenic temperature for application to readout circuit of high-impedance detectors

A GaAs junction field effect transistor (JFET) is a promising candidate for the cryogenic electronics of high-impedance sensitive photoconductors because of its low-noise at low frequencies. This GaAs JFET has advantages compared with other type of FETs, such as no kink phenomena or hysteresis in its current-voltage (I-V) characteristics, small gate leakage currents, and minute capacitance. We report on the noise spectra and leakage current of a SONY n-type GaAs FET in a high-impedance configuration where the gate terminal was surrounded by high-impedance devices at a cryogenic temperature, i.e., 4.2 K. In the high-impedance configuration, we obtained a low noise level and low leakage current of 0.5 /spl mu/V/Hz/sup 1/2/ at 1 Hz and 4.6/spl times/10/sup -19/ A. This result implies that the GaAs JFET is suitable for cryogenic readout electronics. We also discuss the source of the random telegraph signal and the 1/f noise in the GaAs JFET at cryogenic temperatures.     

SiC和GaN电力电子器件的研究进展

与传统的Si基器件相比,SiC和GaN器件具有工作温度高、击穿电压高、开关速度快等优势,因此SiC和GaN材料是制备电力电子器件的理想材料。总结了近年来SiC和GaN电力电子器件的研究进展,包括二极管,MOSFET,JFET和BJT结构的SiC器件,以及SBD,PN结二极管,HEMT和MOSFET结构的GaN器件。     

Proposal of preliminary device model and scaling scheme of cross-current tetrode SOI MOSFET aiming at low-energy circuit applications

This paper describes a preliminary attempt with a semi-analytical model and a scaling scheme of the cross-current tetrode (XCT) silicon-on-insulator (SOI) MOSFET aiming at low energy-dissipation circuit applications. The channel-current model for XCT MOSFET is separated into an intrinsic MOSFET part and a parasitic junction-gate field-effect transistor (JFET) part. Models for MOSFET and JFET are proposed by taking the potential coupling between MOSFET and JFET. The later part of the paper introduces experiments on the original SOI nMOSFET and XCT nMOSFET. This paper stresses the fundamental operations and features of the XCT device structure. Calculation results of I-V characteristics from the semi-analytical model are compared with the measurement values. It is shown that the proposed model reproduces the measured values successfully. In addition, design guidelines for XCT devices and scaling issues are discussed from the viewpoint of performance control aiming at low energy-dissipation circuit applications. Finally, preliminary circuit simulation results of XCT CMOS devices are revealed to demonstrate the definite low-energy performance.     

Investigation of temperature variations on analog/RF and linearity performance of stacked gate GEWE-SiNW MOSFET for improved device reliability

In this paper, reliability issues of Stacked Gate (SG)-Gate Electrode Workfunction Engineered (GEWE)-Silicon Nanowire (SiNW) MOSFET is examined over a wide range of ambient temperatures (200–600 K) and results so obtained are simultaneously compared with conventional SiNW and GEWE-SiNW MOSFET using 3D-technology computer aided design quantum simulation. The results indicate that two temperature compensation points (TCP) are obtained: one for drain current (I_ds) and other for cut-off frequency (f_T) where device Figure Of Merits (FOMs) become independent of temperature, and it is found at 0.65 V in SG-GEWE-SiNW in comparison to other devices, hence will open opportunities for wide range of temperature applications. Furthermore, significant improvement in Analog/RF performance of SG-GWEW-SiNW is observed in terms of I_on/I_off, Subthreshold Swing (SS), device efficiency, f_T, noise conductance and noise figure as temperature reduces. It is also observed that at low temperature SG-GEWE-SiNW unveils highly stable linearity performance owing to reduced distortions. These results explain the improved reliability of SG-GEWE-SiNW at low temperatures over GEWE-SiNW MOSFET.     

Temperature dependent threshold behavior of depletion mode MOSFETs: Characterization and simulation

During the study of depletion mode MOSFET behavior at low temperatures, unusual changes in the threshold characteristics of the devices were observed. First, the effectiveness of the donor implantation in producing a negative threshold voltage shift was significantly reduced. At the same time the substrate sensitivity was found to be substantially reduced. A third observation was the existence of an unusual structure in the subthreshold region of the device at low temperatures. Computer simulation is used to explore these observations and to demonstrate that they are caused by impurity freezeout as temperature is reduced. The computer simulation program, usable over the temperature range 50–350 K, is discussed, and a threshold definition suitable for numerical analysis of devices with arbitrary channel structures is developed.     

Temperature behavior of insulated gate transistor characteristics

The Insulated Gate Transistor (IGT) is a new power semiconductor device with the high input impedance features of the power MOSFET and the ability to operate at high current densities even exceeding that of power bipolar transistors. The high temperature operating characteristics of the device are discussed here. Unlike the power MOSFET whose operating current density decreases by over a factor of 2 when the ambient temperature is raised to 150°C, the IGT is found to maintain its high operating current density at elevated temperatures. The temperature coefficient of the output current is found to be positive at forward drops below 1.5 V and negative at forward drops above 1.5 V. These characteristics make the IGT suitable for applications with high ambient temperatures. The results also indicate that these devices can be paralleled without current hogging problems if the forward conduction occurs at forward voltage drops in excess of 1.5 V.     

High temperature characteristics of bipolar mode power JFET operation

The high-temperature operating characteristics of high-voltage JFET devices operated in the bipolar mode are evaluated. Good forward blocking capability with no degradation in blocking gain is observed at up to 200°C. The on-resistance and gate turnoff time of the devices was found to double from 25°C to 200°C, and the current gain was found to decrease by 30 percent. Despite the increase in gate drive requirements with increasing temperature, these devices should still be attractive for high-speed power switching applications because their on-resistance per unit area is at least 10 time lower than that of the power MOSFET.     

Switching times variation of MOSFET devices with temperature and high-field stress

Switching times of power MOSFET devices are investigated as function of temperature and high-field stress. Measurements show that important variations are obtained on the devices turn-on time. The threshold voltage is decreasing with temperature and varies with stress, especially at low temperatures. The oxide leakage current is found to be having safe values even at high temperatures, stressing the devices does not increase the leakage current to unsafe values except for very high temperatures.     

GaAs MESFET低温性能实验

本文介绍了在低温下,对GaAs MESFET(包括12GHz低噪声器件、双栅器件、功率器件及振荡用器件)所进行的性能测量与分析。在218K(-55℃)下,上述各类器件的跨导g_m相对于室温可增加5～8％,器件的C_(gs)可减少20～50％,器件的寄生电阻R_s和R_d可减少15～40％,R_g也存在缓慢下降的趋势。 文章还给出了低温下低噪声GaAs MESFET放大器的噪声、增益—温度曲线。在218K下,放大器的噪声相对室温可下降1dB左右,单级增益相对室温可增加1～1.5dB,即在低温表现出良好的微波性能。     

Low-temperature CMOS 8 × 8 bit multipliers with sub-10-ns speeds

Low-temperature (77, 4.2 K) operation is proposed for bulk CMOS devices for use in super-fast VLSI applications. Symmetrical variations of both types of MOSFET parameters with respect to temperature and latchup immunity make CMOS a very promising device technology at low temperatures. To demonstrate the performance advantage of circuit operation at low temperatures, multipliers with two different circuit configurations are designed and fabricated with a gate length of 1.3 µm. Multiplication speeds of 8.0 and 6.6 ns are obtained with CMOS circuit configurations at 4.2 K and with pulsed-p-load/CMOS circuit configurations at 77 K, respectively.     

Temperature dependency of 0.1 μm partially depleted SOI CMOSFET

This work investigates the floating body effect (FBE) on the partially depleted SOI devices at various temperatures for high-performance 0.1 μm MOSFET. The thermal effect on the device's characteristics was investigated with respect to the body contacted MOSFET (BC-SOI) and floating body MOSFET without body contacted (FB-SOI). It is found that the threshold voltage (Vth) and the off state drain current (I_OFF) of the BC-SOI devices are more temperature sensitive than those of the FB-SOI devices. For operation at higher temperatures, there is no apparent difference in driving capability between the BC-SOI and FB-SOI MOSFETs     

SiC JFET与SiC MOSFET失效模型及其短路特性对比

建立了两种碳化硅（SiC）器件JFET和MOSFET的失效模型.失效模型是在传统的电路模型的基础上引入了额外附加的泄漏电流,其中,SiC JFET是在漏源极引入了泄漏电流,SiC MOSFET是在漏源极和栅极引入了泄漏电流;同时,为了体现温度和电场强度与失效的关系,用与温度和电场强度相关的沟道载流子迁移率代替了传统电路模型所采用的常数迁移率.有关文献的实验结果和半导体器件的计算机模拟（Technology Computer Aided Design,TCAD）验证了两种SiC器件失效模型的准确性.所建立的失效模型能够对比SiC JFET和SiC MOSFET的短路特性.     

Temperature dependence of 1/f noise in Hg1-xCdxTe MIS infrared detectors

We measured 1/f noise on Hg_0.71Cd_0.29Te Metal-Insulator-Semiconductor (MIS) infrared detectors operated over the temperature range of 40 K to 90 K under 300 K Infrared (IR) radiation. The purpose of the study was to identify the sources of 1/f noise, especially in relation to the dark current. The devices were operated in the correlated double sampling mode where the voltage across the MIS capacitor was sampled at empty potential well and right after the accumulation of minority carriers in the well due to IR radiation generation. The noise power spectral density for the charge integrated in the MIS well was investigated in relation to the dominant component of dark current. At lower temperatures T⩽65 K, the charge noise power spectral density was found to depend quadratically on the dark current. At higher temperatures, this quadratic dependence did not exist. We attribute the dark current to a mixture of tunneling and depletion-region-originated minority carrier generation which seems to be responsible for 1/f fluctuations in these structures for temperatures below 65 K     

Cryogenic noise performance of HEMTs and MESFETs between 300 and700 MHz

The authors present the noise performance of amplifiers using HEMTs and MESFETs at room temperature and cryogenic temperatures, in the frequency range 300-700 MHz. Results demonstrate that these microwave devices can be applied at frequencies down to at least 300 MHz, giving amplifier noise temperatures below 2 K at 20 K ambient temperature     

Attojoule MOSFET logic devices using low voltage swings and low temperature

Previous estimates of the performance limits of MOSFET logic devices, including the possibility of low temperature operation, have used the conventional static electrical behavior as a starting point. Typically, such studies conclude that the minimum voltage swing is ～ 200 mV, leading to practical limits on power dissipation and switching speed that prohibit the combination of very low-power dissipation and very high speed achieved in Josephson junction logic. At such low voltages, the device behavior becomes very sensitive to fabrication, making high yields difficult. Here we consider the conditions which must be met to achieve high speed and low power VLSI logic devices through voltage swings ～ 25 mV. Dynamic logic through bulk conduction devices operating at T ? 30K represents the major requirements. At such low temperatures, nonequilibrium processes provide a new basis for device action, and a novel relaxation mode MOSFET operating under carrier freezeout conditions is suggested as a possible low-voltage swing logic switch with power-delay products in the attojoule range.     

Modeling of circuits with strongly temperature dependent thermal conductivities for cryogenic CMOS

When designing and studying circuits operating at cryogenic temperatures understanding local heating within the circuits is critical due to the temperature dependence of transistor and noise behavior. Local heating effects of a CMOS ring oscillator and current comparator were investigated at T=4.2 K. In two cases, the temperature near the circuit was measured with an integrated thermometer. A lumped element equivalent electrical circuit SPICE model that accounts for the strongly temperature dependent thermal conductivities and special 4.2 K heat sinking considerations was developed. The temperature dependence on power is solved numerically with a SPICE package, and the results are typically within 3σ of the measured values for local heating ranging from to over 100 K.     

N-channel enhancement-mode MOSFET characteristics from 10 to 300 K

Operation of MOSFET circuits at the liquid nitrogen temperature (77 K) has been suggested as a means of improving circuit and system performance. Previously reported work emphasizes mobility and threshold voltage at 77 K. However, small MOSFET's require several (≳10) parameters for circuit design. Since a full set of MOSFET model parameters have not been previously reported, it has not been established whether conventional models can be applied for MOSFET circuit design at 77 K. We present here the temperature dependence of a full set of MOSFET circuit model parameters for channel lengths from 2.5 to 8.5 µm and for temperatures ranging from 10 to 300 K. Temperatures below 77 K are of interest in evaluating effects of impurity freezeout and temperatures above 77 K are important since actual device temperatures will be above the ambient. Overall, we find that the mobility and the threshold voltage are the dominant temperature dependent parameters and that conventional I-V characteristics persist down to 77 K. Below 77 K, some new features appear in the I-V characteristics. However, the conventional behavior down to 77 K suggests that standard (circuit models can be used for circuits operating at 77 K. Such circuits would be about four times faster than at room temperature and, with liquid nitrogen cooling, would provide an order of magnitude higher power density for VLSI.     

Noise of field-effect transistors at very high frequencies

The minimum noise factor of a field-effect transistor has been computed at high frequencies on the basis of the thermal noise of the real parts of the equivalent circuit. A treatment of the intrinsic FET is followed by a consideration of the influence of feedback, parasitic output impedance and parasitic impedance in series with the source on the noise factor. Moreover, the difference between common-gate and common-source configuration has been considered. For frequencies smaller than the gain-bandwidth product fgbthe factorF_{min} - 1varies linearly with the frequency, whereas at higher frequencies this factor varies with f². The computed results are compared with measurements on both JFETs and MOSFETs in the frequency range 100-1500 MHz at different conditions of operation. The agreement is rather good. For the JFET the value ofF_{min}(f_{gb}) approx 2.5; for the MOSFET somewhat higher values are found due to the presence of substrate depletion effects.     

Short-channel effects in MOSFET's at liquid-Nitrogen temperature

Short-channel or high-field effects in MOSFET devices are a continuing area of research in room-temperature devices. Much has been learned in the past several years about the physical origins of these effects, and new or modified device structures have been proposed to minimize them. Because of the improved device and circuit performance possible at liquid-nitrogen temperature (LN2), there has been considerable recent interest in low-temperature device physics. While large-geometry MOSFET behavior has been discussed in the literature at LN2, very little has been quantified regarding short-channel effects at low temperature. This paper addresses the physical origins of short-channel effects at these temperatures. It is concluded that while the physical mechanisms are similar to those at room temperature, quantitative differences exist that favor LN2operation.     

Criteria for setting the width of CCD front end transistor to reachminimum pixel noise

The paper gives the criteria to calculate the width of the front end transistor integrated next to the charge sensing electrode of CCDs or, in general, of semiconductor detectors, in order to reach the minimum noise in the readout of the signal charge. It accounts for white, series and parallel, and 1/f noise contributions. In addition, it points out two different design criteria depending whether a JFET or a MOSFET is used. The attention given to the JFET is due to a lower 1/f noise component, which makes these transistors more appealing as input devices in very high resolution detectors. The paper shows that there is a characteristic width of the FET gate that practically does not depend on the noise sources but depends only on the capacitance seen by the charge sensing electrode of the detector, making possible the optimum design of the transistor prior to knowledge of the real values of the spectral density of the noise sources, which are usually precisely known only at the end of the fabrication process. The paper shows that the pixel noise raises sharply as the transistor gate width departs from its optimum value