Removal of stacking faults in Ge grown on Si through nanoscale openings in chemical SiO2

Nucleation and eventual coalescence of Ge islands, grown out of 5 to 7 nm diameter openings in chemical SiO₂ template and epitaxially registered to the underlying Si substrate, have been shown to generate a low density of threading dislocations (?10⁶ cm^− 2). This result compares favorably to a threading dislocation density exceeding 10⁸ cm^− 2 in Ge films grown directly on Si. However, the coalesced Ge film contains a relatively high density of stacking faults (5 × 10⁷ cm^− 2), and subsequent growth of GaAs leads to an adverse root-mean-square roughness of 36 nm and a reduced photoluminescence intensity at 20% compared to GaAs grown on Ge or GaAs substrates. Herein, we find that annealing the Ge islands at 1073 K for 30 min before their coalescence into a contiguous film completely removes the stacking faults. However, the anneal step undesirably desorbs any SiO₂ not covered by existing Ge islands. Further Ge growth results in a threading dislocation density of 5 × 10⁷ cm^− 2, but without any stacking faults. Threading dislocations are believed to result from the later Ge growth on the newly exposed Si where the SiO₂ has desorbed from areas uncovered by Ge islands. The morphology and photoluminescence intensity of GaAs grown on the annealed Ge is comparable to films grown on GaAs or Ge substrates. Despite this improvement, the GaAs films grown on the annealed Ge/Si exhibit a threading dislocation density of 2 × 10⁷ cm^− 2 and a minority carrier lifetime of 67 ps compared to 4 to 5 ns for GaAs on Ge or GaAs substrates. A second oxidation step after the high temperature anneal of the Ge islands is proposed to reconstitute the SiO₂ template and subsequently improve the quality of Ge film.     

Effect of layer thickness on structural quality of Ge epilayers grown directly on Si(001)

A study of Ge epilayer growth directly on a Si(001) substrate is presented, following the two temperature Ge layer method. In an attempt to minimize the overall thickness while maintaining a good quality Ge epilayer, we have investigated the effect of varying the thickness of both the low and high temperature Ge layers, grown at 400 °C and 670 °C, respectively, by reduced pressure chemical vapor deposition. We find that the surface of the low temperature (LT) seed layer has a threading dislocation density (TDD) to the order of 10¹¹ cm^− 2. On increasing the LT layer thickness from 30 nm to 150 nm this TDD decreases by a factor of 2, while its roughness doubles and degree of relaxation increases from 82% to 96%. Growth of the high temperature (HT) layer reduces the TDD level to around 10⁸ cm^− 2, which is also shown to decrease with increasing layer thickness. Both the surface roughness and degree of relaxation reach stable values for which increasing the thickness beyond about 700 nm has no effect. Finally, annealing the HT layer is shown to reduce the TDD, without affecting the degree of relaxation. However, unless a thick structure is used the surface roughness increases significantly on annealing.     

Nanoscale interfacial engineering to grow Ge on Si as virtual substrates and subsequent integration of GaAs

We have demonstrated the scalability of a process previously dubbed as Ge “touchdown” on Si to substantially reduce threading dislocations below 10⁷/cm² in a Ge film grown on a 2 inch-diameter chemically oxidized Si substrate. This study also elucidates the overall mechanism of the touchdown process. The 1.4 nm thick chemical oxide is first formed by immersing Si substrates in a solution of H₂O₂ and H₂SO₄. Subsequent exposure to Ge flux creates 3 to 7 nm-diameter voids in the oxide at a density greater than 10¹¹/cm². Comparison of data taken from many previous studies and ours shows an exponential dependence between oxide thickness and inverse temperature of void formation. Additionally, exposure to a Ge or Si atom flux decreases the temperature at which voids begin to form in the oxide. These results strongly suggest that Ge actively participates in the reaction with SiO₂ in the void formation process. Once voids are created in the oxide under a Ge flux, Ge islands selectively nucleate within the void openings on the newly exposed Si. Island nucleation and growth then compete with the void growth reaction. At substrate temperatures between 823 and 1053 K, nanometer size Ge islands that nucleate within the voids continue to grow and coalesce into a continuous film over the remaining oxide. Coalescence of the Ge islands is believed to result in the creation of stacking faults in the Ge film at a density of 5 × 10⁷/cm². Additionally, coalescence results in films of 3 µm thickness having a root-mean-square roughness of 8 to 10 nm. We have found that polishing the films with dilute H₂O₂ results in roughness values below 0.5 nm. However, stacking faults originating at the Ge-SiO₂ interface and terminating at the Ge surface are polished at a slightly reduced rate, and show up as 1 to 2 nm raised lines on the polished Ge surface. These lines are then transferred into the subsequent growth morphology of GaAs deposited by metal-organic chemical vapor deposition. Room temperature photoluminescence shows that films of GaAs grown on Ge-on-oxidized Si have an intensity that is 20 to 25% compared to the intensity from GaAs grown on commercial Ge or GaAs substrates. Cathodoluminescence shows that nonradiative defects occur in the GaAs that spatially correspond to the stacking faults terminating at the Ge surface. The exact nature of these nonradiative defects in the GaAs is unknown, however, GaAs grown on annealed samples of Ge-on-oxidized Si, whereby annealing removes the stacking faults, have photoluminescence intensity that is comparable to GaAs grown on a GaAs substrate.     

Growth and characterization of germanium epitaxial film on silicon (001) using reduced pressure chemical vapor deposition

High quality germanium (Ge) epitaxial film is grown directly on silicon (001) substrate using a “three-step growth” approach in a reduced pressure chemical vapor deposition system. The growth steps consist of sequential low temperature (LT) at 400 °C, intermediate temperature ramp (LT-HT) of ~ 6.5 °C/min and high temperature (HT) at 600 °C. This is followed by post-growth anneal in hydrogen at temperature ranging from 680 to 825 °C. Analytical characterizations have shown that the Ge epitaxial film of thickness ~ 1 μm experiences thermally induced tensile strain of 0.20% with a threading dislocation density of < 10⁷ cm^− 2 under optical microscope and root mean square roughness of ~ 0.9 nm. Further analysis has shown that the annealing time at high temperature has an impact on the surface morphology of the Ge epitaxial film. Further reduction in the RMS roughness can be achieved either through chemical mechanical polishing or to insert an annealing step between the LT-HT ramp and HT steps.     

Fabrication of high quality Ge virtual substrates by selective epitaxial growth in shallow trench isolated Si (001) trenches

To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench isolated Si substrates for pMOSFET fabrication. However, the high threading dislocation densities (TDDs) in epitaxial Ge layers on Si cause mobility degradation and increase in junction leakage. In this work, we studied the fabrication of Ge virtual substrates with low TDDs by Ge selective growth and high temperature anneal followed by chemical mechanical polishing (CMP). With this approach, the TDDs in both submicron and wider trenches were simultaneously reduced below 1 × 10⁷ cm^− 2 for 300 nm thick Ge layers. The resulting surface root-mean-square (RMS) roughness is about 0.15 nm. This fabrication scheme provides high quality Ge virtual substrates for pMOSFET devices as well as for III-V selective epitaxial growth in nMOSFET areas. A confined dislocation network was observed at about 50 nm above the Ge/Si interface. This dislocation network was generated as a result of effective threading dislocation glide and annihilation. The separation between the confined threading dislocations was found in the order of 100 nm.     

The effects of low temperature buffer layer on the growth of pure Ge on Si(001)

We investigated the effects of low temperature (LT) Ge buffer layers on the two-step Ge growth by varying the thickness of buffer layers. Whereas the two-step Ge layers using thin (< 40 nm) Ge buffer layers were roughened due to the formation of SiGe alloy, pure and flat Ge layers were grown by using thick (> 50 nm) LT Ge buffer layers. The lowest threading dislocation density of 1.2 × 10⁶ cm⁻² was obtained when 80-nm-thick LT Ge buffer layer was used. We concluded that the minimum thickness of buffer layer was required to grow uniform two-step Ge layers on Si and its quality was subject to the thickness of buffer layer.     

Epitaxy of In0.01Ga0.99As on Ge/offcut Si (001) virtual substrate

In_0.01Ga_0.99As thin films free of anti-phase domains were grown on 7° offcut Si (001) substrates using Ge as buffer layers. The Ge layers were grown by ultrahigh vacuum chemical vapor deposition using ‘low/high temperature’ two-step strategy, while the In_0.01Ga_0.99As layers were grown by metal-organic chemical vapor deposition. The etch-pit counting, cross-section and plane-view transmission electron microscopy, room temperature photoluminescence measurements are performed to study the dependence of In_0.01Ga_0.99As quality on the thickness of Ge buffer. The threading dislocation density of Ge layer was found to be inversely proportional to the square root of its thickness. The threading dislocation density of In_0.01Ga_0.99As on 300 nm thick Ge/offcut Si was about 4 × 10⁸ cm^− 2. Higher quality In_0.01Ga_0.99As can be obtained on thicker Ge/offcut Si virtual substrate. We found that the threading dislocations acted as non-radiative recombination centers and deteriorated the luminescence of In_0.01Ga_0.99As remarkably. Secondary ion mass spectrometry measurement indicated as low as 10¹⁶ cm^− 3 Ge unintended doping in In_0.01Ga_0.99As.     

Low threading dislocation Ge on Si by combining deposition and etching

Blanket and selective Ge growth on Si is investigated using reduced pressure chemical vapor deposition. To reduce the threading dislocation density (TDD) at low thickness, Ge deposition with cyclic annealing followed by HCl etching is performed. In the case of blanket Ge deposition, a TDD of 1.3 × 10⁶ cm^− 2 is obtained, when the Ge layer is etched back from 4.5 μm thickness to 1.8 μm. The TDD is not increased relative to the situation before etching. The root mean square of roughness of the 1.8 μm thick Ge is about 0.46 nm, which is of the same level as before HCl etching. Further etching shows increased surface roughness caused by non-uniform strain distribution near the interface due to misfit dislocations and threading dislocations. The TDD also becomes higher because the etchfront of Ge reaches areas with high dislocation density near the interface. In the case of selective Ge growth, a slightly lower TDD is observed in smaller windows caused by a weak pattern size dependence on Ge thickness. A significant decrease of TDD of selectively grown Ge is also observed by increasing the Ge thickness. An about 10 times lower TDD at the same Ge thickness is demonstrated by applying a combination of deposition and etching processes during selective Ge growth.     

High quality Ge epitaxial layers on Si by ultrahigh vacuum chemical vapor deposition

Flat, relaxed Ge epitaxial layers with low threading dislocation density (TDD) of 1.94 × 10⁶ cm^− 2 were grown on Si(001) by ultrahigh vacuum chemical vapor deposition. High temperature Ge growth at 500 °C on 45 nm low temperature (LT) Ge buffer layer grown at 300 °C ensured the growth of a flat surface with RMS roughness of 1 nm; however, the growth at 650 °C resulted in rough intermixed SiGe layer irrespective of the use of low temperature Ge buffer layer due to the roughening of LT Ge buffer layer during the temperature ramp and subsequent severe surface diffusion at high temperatures. Two-dimensional Ge layer grown at LT was very crucial in achieving low TDD Ge epitaxial film suitable for device applications.     

High-quality epitaxial Bi(111) films on Si(111) by isochronal annealing

Bi(111) films grown on Si(111) at room temperature show a significantly higher roughness compared to Bi films grown on Si(100) utilizing a kinetic pathway based on a low-temperature process. Isochronal annealing steps of 3 min duration each with temperatures up to 200 °C cause a relaxation of the Bi films' lattice parameter toward the Bi bulk value and yield an atomically flat Bi surface. Driving force for the relaxation and surface reordering is the magic mismatch of 11 Bi atoms to 13 Si atoms that emerges at annealing temperatures above 150 °C and reduces the remaining strain to less than 0.2%.     

Growth of high Ge content SiGe on (110) oriented Si wafers

Growth of high (above 40%) Ge content SiGe by applying silane and dichlorosilane as Si precursors on (110) Si is investigated. In the case of silane based processes Ge concentration is ~ 20% higher, whereas for dichlorosilane based processes it is ~ 30% lower on (110) Si compared to (100) Si. The morphology of the grown layers is found to be dependent on Ge concentration, layer thickness and process temperature. Use of optimized deposition parameters and adequate thickness results in high quality strained SiGe layers. Integration of high Ge content SiGe layers in multiple gate filed-effect transistor structures shows the expected differences in Ge content on the different Si planes forming Si fin. These differences can be avoided by adjusting the fin orientation on the Si wafer resulting in equal planes on the fin's top and sidewalls. When the investigated SiGe layers are incorporated in the buried channel field effect transistor structures on (110) Si wafers a significant thickening at the active windows edge is observed. It is speculated that this effect is connected with elastic SiGe relaxation caused by a non optimized process temperature.     

Ion assistance in epitaxial growth as a strategy to suppress twinning

Homoepitaxy on Ir(111) at 350 K through physical vapor deposition without and with ion assistance is compared in a scanning tunneling microscopy study. During growth without ion assistance thin Ir films on Ir(111) rapidly develop stacking faults such that for films of more than 50 atomic layers thickness the majority of the film surface displays twins. Ion assistance with 100 eV Ar⁺ at normal incidence as well as with 500 eV Ar⁺ at grazing incidence both effectively suppress stacking fault formation and twinning in the growing film. The mechanisms of twin suppression are identified.     

Low-temperature epitaxy of silicon by electron beam evaporation

In this paper we report on homoepitaxial growth of thin Si films at substrate temperatures T_s = 500-650 °C under non-ultra-high vacuum conditions by using electron beam evaporation. Si films were grown at high deposition rates on monocrystalline Si wafers with (100), (110) and (111) orientations. The ultra-violet visible reflectance spectra of the films show a dependence on T_s and on the substrate orientation. To determine the structural quality of the films in more detail Secco etch experiments were carried out. No etch pits were found on the films grown on (100) oriented wafers. However, on films grown on (110) and (111) oriented wafers different types of etch pits could be detected. Films were also grown on polycrystalline silicon (poly-Si) seed layers prepared by an Aluminum-Induced Crystallisation (AIC) process on glass substrates. Electron Backscattering Diffraction (EBSD) shows that the film growth proceeds epitaxially on the grains of the seed layer. But a considerably higher density of extended defects is revealed by Secco etch experiments.     

Growth of 3C-SiC on Si(111) using the four-step non-cooling process

A modified four-step method was applied to grow a 3C-SiC thin film of high quality on the off-axis 1.5° Si(111) substrate in a mixed gas of C₃H₈, SiH₄ and H₂ using low pressure chemical vapor deposition. The modified four-step method adds a diffusion step after the carburization step and removes the cooling from the traditional three-step method (clean, carburization, and growth). The X-ray intensity of the 3C-SiC(111) peak is enhanced from 5 × 10⁴ counts/s (the modified three steps) to 1.1 × 10⁵ counts/s (the modified four steps). The better crystal quality of 3C-SiC is confirmed by the X-ray rocking curves of 3C-SiC(111). 3C-SiC is epitaxially grown on Si(111) supported by the selected area electron diffraction patterns taken at the 3C-SiC/Si(111) interface. Some {111} stacking faults and twins appear inside the 3C-SiC, which may result from the stress induced in the 3C-SiC thin film due to lattice mismatch. The diffusion step plays roles in enhancing the formation of Si-C bonds and in reducing the void density at the 3C-SiC/Si(111) interface.     

Development of analytical model for strained silicon relaxation on (100) fully relaxed Si0.8Ge0.2 pseudo-substrates

Early stages of strained silicon (sSi) relaxation during the growth on (100) Si_0.8Ge_0.2 pseudo-substrates with low threading dislocation density (3 · 10^+ 4/cm²) have been studied. Threading dislocations are only observed in sSi layers at early stages of growth whereas Shockley partial dislocations appear at thicknesses of sSi above 18 nm. By analyzing the dislocation types in different sSi layers we observed three different regimes of relaxation:

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for sSi thickness below 15 nm, no dislocation generation is observed,

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for sSi thickness between 15 nm and 18 nm, threading dislocation density increases but no stacking faults are generated,

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for sSi thickness above 18 nm, threading dislocation density decreases as well as Shockley partial dislocation density increases due to the splitting of threading dislocations into partial dislocations. In this regime the stacking fault linear density has a logarithmic dependence with sSi thickness.

We developed an analytical model to describe stacking fault linear density evolution with sSi thickness and we showed that 18 nm threshold thickness for dislocation splitting corresponds to an intrinsic stacking fault energy of 90 mJ/m² in sSi.     

Structural properties of the formation of yttrium germanides thin films on the Si(111) surface

We have performed first principles total energy calculations to investigate the deposit of yttrium digermanide on the Si(111) surface. We have used the periodic density functional theory as implemented in the Quantum-ESPRESSO package. For the adsorption of a monolayer of yttrium digermanide on the Si(111)-(1 × 1) surface, we have found that the most stable geometry corresponds to a configuration with Y atoms occupying the T4 site above a second layer Si atom, and with a Ge bilayer on top of the structure. The atomic structure of the Ge bilayer is similar to that of Si (Ge) in the bulk but rotated 180° with respect to the crystal. For the three dimensional growth of a few layers of yttrium digermanide on Si(111) we have considered a hexagonal structure with (√3 × √3) periodicity, similar to the one found in the growth of few layers of YSi₂ on Si(111): graphite-like Ge planes (with vacancies) intercalated with yttrium planes. As in the case of a single layer of YGe₂, there is a formation of a Ge bilayer on top of the structure. In this case, the Ge_down atoms of the bilayer, which are on top the vacancies, move down towards the vacancy, while Ge atoms in the graphitic layer, which are below the Ge_up atoms of the bilayer, are displaced towards the vacancy.     

Electronic structure of Co islands grown on the √3 × √3-Ag/Ge(111) surface

By means of room temperature scanning tunneling spectroscopy (RT STS), we have studied the electronic structure of two different Ag/Ge(111) phases as well as Co islands grown on the √3 × √3-Ag/Ge (111) forming either √13 × √13 or 2 × 2 patterns. The spectrum obtained from 4 × 4-Ag/Ge(111) structure shows the existence of a shoulder at 0.7 V which is also present in the electronic structure of the Ge(111)-c2 × 8 and indicates donation of Ge electrons to electronic states of the Ag-driven phase. However, this fact is not supported by the electronic spectrum taken from the √3 × √3-Ag/Ge (111). The complexity of the Co-√13 × √13 islands bonding with the substrate is mirrored by a large number of peaks in their electronic spectra. The spectra obtained from the Co-2 × 2 islands which had grown on the step differ from those taken from Co-2 × 2 islands located along the edge of the terrace by a number of peaks at negative sample bias. This discrepancy is elucidated in terms of dissimilarities of Co-substrate interaction accompanying Co islands growth on different areas of the stepped surface.     

Single-crystalline Si grown on single-crystalline Gd2O3 by modified solid-phase epitaxy

We investigate molecular beam epitaxial overgrowth of Si template layers produced by different approaches on single-crystalline oxide grown on Si(111). Three approaches based on modified solid-phase epitaxy were found to be suitable for the subsequent Si epitaxial overgrowth. The crystalline quality and interface properties of single-crystalline silicon on single-crystalline oxide grown on Si(111) make the obtained structures suitable for silicon-on-insulator applications. First measurements of electrical properties of p-type samples indicate good electrical properties of the top Si layer. Supplemental investigations demonstrate that Si layers with thickness in the range of 10 nm remain stable during thermal annealing up to 900 °C in an ultra-high vacuum.     

Reverse graded strain relaxed SiGe buffers for CMOS and optoelectronic integration

Reverse terrace graded buffers are proposed for high quality high Ge content Si_0.23Ge_0.77 buffers. The buffer structure allows the effects of applied thermal budget and grading rate to be separated and compared to previously reported reverse linearly graded virtual substrates. A reduction in threading dislocation density to 2.1 × 10⁶ cm^− 2 and an enhanced relaxation is found for these terrace graded structures of almost identical thickness and twice the strain gradient of the linear graded structures, whilst a smooth surface is retained with an rms roughness of just 1.9 nm.