An 8/10 bit 200/100MS/s configurable asynchronous SAR ADC

This paper presents an asynchronous 8/10 bit configurable successive approximation register analog-to-digital converter (ADC). The proposed ADC has two resolution modes and can work at a maximal sampling rate of 200 and 100MS/s for 8 bit mode and 10 bit mode respectively. The ADC uses a custom-designed 1 fF unit capacitor to reduce the power consumption and settling time of capacitive DAC, a dynamic comparator with tail current to minimize kickback noise and improve linearity. Moreover, asynchronous control technique is utilized to implement the ADC in a flexible and energy-efficient way. The proposed ADC is designed in 90 nm CMOS technology. At 100MS/s and 1.0 V supply, the ADC consumes 1.06 mW and offers an ENOB of 9.56 bit for 10 bit mode. When the ADC operates at 8 bit mode, the sampling rate is 200MS/s with 1.56 mW power consumption from 1.0 supply. The resulted ENOB is 7.84 bit. The FOMs for 10 bit mode at 100MS/s and 8 bit mode at 200MS/s are 14 and 34 fJ/conversion-step respectively.     

An 8 bit, 100 kS/s,switch-capacitor DAC SAR ADC for RFID applications

An 8 bit switch-capacitor DAC successive approximation analog to digital converter (SAR-ADC) for sensor-RFID application is presented in this paper. To achieve minimum chip area, maximum simplicity is imposed on capacitive DAC; replacing capacitor bank with only a one switch-capacitor circuit. The regulated dynamic current mirror (RDCM) design is introduced to provide stabilized current. This invariable current from RDCM, charging or discharging the only capacitor in circuit is controlled by pulse width modulated signal to realize switch capacitor DAC. The switch control scheme is built using basic AND gates to generate the control signals for RDCM. Only one capacitor and reduced transistor count in digital part reduces the silicon area occupied by the ADC to only 0.0098 mm². The converter, designed in GPDK 90 nm CMOS, exhibits maximum sampling frequency of 100 kHz & consumes 6.75 µW at 1 V supply. Calculated signal to noise and distortion ratio (SNDR) at 1 V supply and 100 kS/s is 48.68 dB which relates to ENOB of 7.79 bits. The peak values of differential and integral nonlinearity are found to be +0.70/−0.89 LSB and +1.40/−0.10 LSB respectively. Evaluated figure of merit (FOM) is 3.87×10²⁰, which show that the proposed ADC acquires minimal silicon area and has sufficiently low power consumption compared to its counterparts in RFID applications.     

一种8位100 MS/s的低功耗流水线型ADC

基于0.35 μm CMOS工艺,设计并制作了一种低功耗流水线型ADC。分析了ADC结构对功耗的影响,采用1.5位/级的流水线结构来最小化功耗,并提升速度。为进一步降低功耗,设计了一种不带补偿并可调节相位裕度的共源共栅跨导放大器(OTA)和改进的比较器。测试结果显示,该ADC在3 V电源电压、100 MS/s采样速率下,功耗为65 mW,面积为0.73 mm²,在模拟输入频率为70.1 MHz和141 MHz下的无杂散动态范围(SFDR)分别为59.8 dBc和56.5 dBc。该ADC可应用于需要欠采样的通信系统中。     

An 8-b 100-MSample/s CMOS pipelined folding ADC

Although cascading reduces the number of folders used in folding analog-to-digital converters (ADCs), it demands wider bandwidth. The pipelining scheme proposed in this work greatly alleviates the wide bandwidth requirement of the folding amplifier. The pipelining is implemented with simple differential-pair folders. The key idea is to use odd multiples of folders with distributed interstage track/holds cooperatively with an algorithm for coding and digital error correction for the nonbinary system. The pipelined folding ADC prototyped using 0.5-μm CMOS exhibits a differential nonlinearity (DNL) of ±0.4 LSB and an integral nonlinearity (INL) of ±1.3 LSB at 100 MSample/s. The chip occupies 1.4 mm×1.2 mm in active area and consumes 165 mW at 5 V     

基于比较器亚稳态抑制技术的8位320 MS/sSAR ADC

提出一种比较器亚稳态抑制技术,并将其应用于一个8位320 MS/s 的逐次逼近型模数转换器(SAR ADC)。该技术抑制了比较器在高速工作情况下可能出现的亚稳态现象,从而降低了比较器出现错误结果的概率。同时,提出一种转换时间复用技术,使ADC能在转换与采样模式之间快速切换。与传统技术相比,随着工艺角、电源电压和温度(PVT)的变化,ADC的采样时间会被最大化。基于65 nm CMOS工艺,设计了一种8位320 MS/s SAR ADC。芯片测试结果表明,在1 V电源电压下,功耗为1 mW,信号噪声失真比(SNDR)>43 dB,无杂散动态范围(SFDR)>53.3 dB。SAR ADC核的芯片面积为0.021 mm²,在Nyquist采样率下,优值为29 fJ/step。     

一种全集成8位2.16 GS/s SAR ADC

设计了一种8位2.16 GS/s四通道、时间交织逐次逼近型模数转换器(TI-SAR ADC).单通道SAR ADC采用数据环、异步时钟环的双环结构实现高速工作.采用带复位开关的动态比较器缩短量化时间,提高比较精度.结合反向单调切换时序,逐步增大共模电压,提升量化速度.基于55 nm CMOS工艺设计,后仿真结果表明,在...     

8 bit 400 MS/s CMOS折叠插值结构ADC的设计

折叠插值结构是高速ADC设计中的常用结构。提出了一种新的在折叠插值结构ADC中只对THA进行时间交织的技术,可以在基本不增加芯片功耗和面积的情况下,使ADC的系统速度提高近1倍。位同步技术可以保证粗分和细分通路之间的同步,在位同步的基础上设计了新的编码方式。基于上述技术设计了8 bit 400 MS/s CMOS折叠插值结构ADC,核心电路电流为110mA,面积仅1mm×0.8mm,Nyquist采样频率下SNDR为47.2dB,SFDR为57.1dB。     

单通道8bit1.4GS/s折叠内插ADC

基于0.18 μm CMOS工艺设计并实现了一种8 bit 1.4 GS/s ADC.芯片采用多级级联折叠内插结构降低集成度,片内实现了电阻失调平均和数字辅助失调校准.测试结果表明,ADC在1.4GHz采样率下,有效位达6.4bit,功耗小于480 mW.文章所提的综合校准方法能够有效提高ADC的静态和动态性能,显示出...     

5 V, 8 bit, 100 MS/s fully differential CMOS sample-and-holdamplifier

A 5 V, 100 MS/s fully differential CMOS sample-and-hold amplifier (SHA) with 8 bit accuracy is proposed. Based on the stability limitations of closed-loop SHAs studied in a previous paper (see Int. J. Electron., vol. 78, no. 5, p. 907-910, 1995), the proposed SHA is implemented by an open-loop structure using the `gain-enhanced unity-gain amplifier' to avoid the stability problem and achieve higher operation speed. Simulation results which agree well with experimental results have been obtained to demonstrate the accuracy of the proposed circuit     

采用SAR结构的8通道12位ADC设计

本文设计实现了一个8通道12位逐次逼近型ADC。转换器内部集成了多路复用器、并/串转换寄存器和复合型DAC,实现了数字位的串行输出。整体电路采用HSPICE进行仿真,转换速率为133KSPS,转换时间为7.5μs。通过低功耗设计,工作电流降低为2.8mA。芯片基于0.6μmBiCMOS工艺完成版图设计,版图面积为2.5×2.2mm2。     

An 8-bit 12.5-GSample/s SiGe ADC

This paper describes the design of a high-speed 8-bit Analog to digital converter (ADC) used in direct IF sampling receivers for satellite communication systems in a 0.25 μm, 190 GHz SiGe BiCMOS process. A high resolution front-end track-and-hold amplifier (THA), a low impedance reference and interpolation resistive ladder and high resolution comparators enable the ADC to achieve good performance for input frequencies of up to one-quarter of the sampling rate. The final post layout simulated system features an ENOB of 7.2-bits at an input frequency of 3.125 GHz and a sampling rate of 12.5 GS/s with a FOM of 12.9 pJ per conversion. Both DNL and INL are within 0.5 and 1 LSB, respectively. The converter occupies 10 mm² and dissipates 14 W from a 3.3 V supply. The THA and the comparator, as the most critical building blocks affecting the overall performance of the ADC, were implemented experimentally and fully characterized in order to verify their performance and to ascertain the possibility of implementing the complete ADC. The THA occupies an area of 0.5 mm². It features a SNDR of 47 dB or 7.5-bits ENOB for a 3 GHz bandwidth, a hold time of 21 ps with a droop rate of 11 mV/80 ps and a power dissipation of 230 mW from a 3.3 V supply. The comparator occupies an area of 0.38 mm² and exhibits an input sensitivity of ±2 mV, an input offset voltage of 1.5 mV, latch and recovery times of 19 and 21 ps, respectively, and a power dissipation of 150 mW from a 3.3 V supply. The experimental results are in good agreement with simulation and expected specifications and indicate that both circuits are suitable for the implementation of the ADC and help to validate that the 8-bit 12.5 GS/s ADC is feasible for implementation in a 0.25 μm SiGe process.     

一种1.5 V 8位100 MS/s电流舵D/A转换器

基于新型的低压与温度成正比(PTAT)基准源和PMOS衬底驱动低压运算放大器技术,采用分段温度计译码结构设计了一种1.5V8位100MS/s电流舵D/A转换器,工艺为TSMC0.25μm2P5MCMOS。当采样频率为100MHz,输出频率为20MHz时,SFDR为69.5dB,D/A转换器的微分非线性误差(DNL)和积分非线性误差(INL)的典型值分别为0.32LSB和0.52LSB。整个D/A转换器的版图面积为0.75mm×0.85mm,非常适合SOC的嵌入式应用。     

10 bit 80 Msample/s流水线ADC的电路级设计

实现了0.18μmCMOS模拟工艺、1.8V电源电压下10位分辨率、80MHz采样率的流水线ADC的电路级设计,采用栅压自举的采样开关和增益提升运放保证ADC的精度;采用复位结构的SHC和MDAC消除运放失调电压的影响;采用动态比较器并优化每级电容以降低功耗.当输入信号幅度为1Vpp时,ADC在整个量化范围内无失码,当输入信号频率为39MHz时,可获得71.6dB的无失真动态范围和60.56dB的信噪失真比.     

14 bit 50 ms/s 0.18 μm CMOS pipeline ADC based on digital error calibration

Described is a 14 bit 50 MS/s CMOS four-stage pipeline A/D converter (ADC)-based on a digital code-error calibration. The proposed calibration technique measures the capacitor mismatch errors of the front-end multiplying DAC (MDAC) with the back-end pipeline stages while the measured code errors are stored in memory and corrected in the digital domain during normal conversion. The calibration needs the increased power dissipation and chip area of 1.4 and 10.7 , respectively, compared to a 14 bit uncalibrated conventional pipeline ADC. The prototype ADC fabricated in a 0.18 um CMOS process occupies an active die area of 4.2 mm² and consumes 140 mW at 1.8 V and 50 MS/s. After calibration, the measured DNL and INL of the ADC are improved from 0.69 to 0.39 LSB and from 33.60 to 2.76 LSB, respectively.     

一种10位160 kS/s的循环型模数转换器

提出了一种应用于图像传感器的10位160 kS/s的循环型模数转换器(ADC)。采用1.5位的流水线ADC结构,经过10次循环后,得到10位数字码输出。采用输入端自级联结构的两级运算放大器,提高了运放的增益。采用运放共享技术,实现单转双电路与ADC运放共享,降低了面积和功耗,实现了电平平移。基于0.13 μm CMOS工艺,在3.3 V电源电压和160 kHz采样速率下对ADC进行仿真。后仿真结果表明,该ADC的有效位数为9.45位,SNR为59.1 dB,SFDR为61.26 dB,DNL为±0.625 LSB,INL为±1.5 LSB。     

一种12位20 kS/s功耗调制算法SAR ADC

针对时域稀疏信号中的心电信号(ECG)、脑电信号(EEG)在大部分时间内幅度变化缓慢且周期性变化的特性,提出了一种带信号区间预测窗口的功耗调制型逐次逼近模数转换算法。采用该算法,可大幅减少SAR ADC中稀疏信号在低频部分的平均量化功耗,实现整体功耗的降低。在此理论基础上,设计了一种非二进制冗余校正、功耗调制型12位20 kS/s SAR ADC。该ADC采用55 nm CMOS工艺进行流片,在0.6 V电源电压下,功耗低至204 nW,功耗优值FoM最低为6.28 fJ/(conv·step)。     

A 5 V, 6-b, 80 Ms/s BiCMOS flash ADC

A 5 V single supply, 6-bit flash A/D converter (ADC) has been developed that supports sampling rates of up to 80 Ms/s. The converter is optimized to operate in undersampling applications where the ADC has to deliver greater than 5.2 Effective Number Of Bits (ENOB's) with input frequencies well beyond Nyquist. Excellent dynamic linearity performance has been achieved with input frequencies up to 75 MHz and a gain flatness of better than 0.1 dB is obtained over the input signal spectrum of 50 MHz-95 MHz. This ADC is fabricated on a 1.0 μm advanced BiCMOS process that features trench-isolated bipolar devices with an f_t of 10 GHz     

1.8 V 10 bit 40 MS/s的流水线模数转换器

设计了一个10 bit,40 MS/s流水线模数转换器,适用于无线传感器网络(WSN)嵌入式芯片中.基于对电容失配的非线性影响的分析,提出了每级多比特的结构,使ADC具有很好的线性度.片内集成了参考电压源,大大减少了外围电路的数量.芯片采用SMIC 0.18μm CMOS工艺实现,在40 MS/s采样率下,电路微分非线性(DNL)最大0.42 LSB,积分非线性(INL)最大0.93 LSB,有效精度(ENOB)最高达9 bit.电路使用1.8 V电压供电,核心面积1.5mm2,核心电路功耗73 mW.     

一款12位5 kS/s逐次逼近型模数转换器的设计

提出了一种模拟域的前台校准技术,据此设计了一款12位精度的模数转换器(ADC)。芯片采用全定制叉指电容来实现电容阵列,并在TSMC 65nm工艺下进行了流片验证。芯片的内核面积仅为0.2 mm2,测试数据显示,在5kHz转换速率时信噪失真比(SNDR)为62dB,无杂散动态范围(SFDR)为76dB,在1.2V电源电压下功耗仅为112nW。     

A 14-bit 100-Msample/s subranging ADC

This paper describes a 14-b analog-to-digital converter designed in a complementary bipolar process. Although it uses a fairly traditional three-stage subranging architecture, several nontraditional techniques are incorporated to achieve 14 bits of performance at a clock rate of 100 MHz. For linearity, the most critical of these is wafer level trimming of the first subrange digital-to-analog converter. Prototype silicon exhibits a spurious-free dynamic range of 90 dB through the Nyquist frequency and a signal-to noise ratio of 74 dB while dissipating 1.25 W