一种高速低功耗ECL多模分频器的设计

本文介络一种高速低功耗ECL多模分频器的电路原理、电路和版图设计特点、工艺技术及研制结果。该分频器设计了0.5mA的内部开关电流和350mV的内部逻辑摆幅,输入输出均采用互补驱动。电路分频模数多,频率高,功耗低,典型功耗75mW,为相同集成度的普通ECL电路功耗的1/30～1/40。该电路广泛用于通讯、仪器仪表和频率合成器等领域。     

1.5GHz CMOSECL输入接口的设计与测试

对一种高速CMOS ECL输入接口进行了分析研究,该接口包含一种双镜补偿的CMOS差分放大电路,采用0.18 μm CMOS工艺研制,实现了PECL电平兼容.经测试,该接口最高工作频率达1.5 GHz.     

低温ECL电路的瞬态特性分析

本文对ECL电路的瞬态特性进行了较详尽的分析,给出了适于全温区的较精确的电路延迟时间表达式,并对影响tpd的主要参数的温度特性进行了分析。该模型可用于各种温度下高速器件和电路的优化设计。     

低温ECL电路的直流特性分析

本文在对低温双极晶体管的直流特性的分析基础上,推导出ECL电路在低温下的直流解析模型,并与实验结果和计算机模拟结果进行了比较,还对SPICEⅡ模型在低温下的修正和低温ECL电路的设计进行了一些探讨。     

基于多值逻辑的高速ECL模糊控制表查询电路

该文指出了硬件实现模糊控制表查询电路存在结构复杂、用数字式实现时设计困难等问题,提出了将模糊控制表转换为多值K图,利用K图从开关级设计模糊控制表查询电路的方法,并用此方法具体设计了一个论域元素个数为5的ECL模糊控制表查询电路。从设计实例看,该文提出的设计方法简单易行,而设计的ECL查询电路具有结构简单和高速推理的优点。     

基于开关信号理论的四值ECL电路

从一个有效的多值代数系统应能反映多值电路中的物理过程的这一原则出发,本文提出了一组可以描写多值ECL电路中信号与开关元件间相互作用的运算。讨论了这些运算的物理对应及有关性质,并由此建立了适用于ECL电路的开关信号理论。本文设计了若干基本四值ECL电路,用SPICE程序模拟证明了它们均具有正确的逻辑功能与理想的DC特性。     

一种ECL可编程分频器的研制

本文在分析TTL可编程分频器逻辑功能的基础上,设计了模数在1～16之间任意可变的ECL可编程分频器,利用SPICE电路模拟程序对电路进行了直流和瞬态分析。同时,针对超高速ECL电路的特点,完成了电路版图及工艺设计,并进行了工艺试制。做出了工作频率可达50MHz以上的ECL可编程分频器,比原TTL可编程分频器的工作频率提高了5倍之多。     

GaAs BFL电路输入输出接口电路的研究

讨论了与ECL兼容的GaAs BFL电路的输入输出接口电路的要求,设计并研究了几种能使GaAs BFL电路与ECL电路相兼容的输入输出接口电路,对它们进行了计算机模拟、投片制作和测试。     

构成便携式快速光脉冲发生器的电路

由于整个TTL系列中缺少高速单稳态多谐振荡器,又由于ECL要求电压摆幅小和供电范围宽,从而驱使我们采用具有快速过渡时间和小传输延时的F系列门电路.这就需要制作一个小巧便携式快速光脉冲发生器,用以对伽玛射线天文研究中使用的高速光电倍增器进行现场测试.仅使用两块集成电路有助于缩小体积,降低功耗(图1).     

高性能硅双极器件的发展

以ECL电路为主,讨论了硅双极器件近期的发展。简述了VLSI中ECL电路结构和性能之后,着重讨论双极器件的按比例缩小、结构的改进以及相关的工艺技术的发展,最后分析了双极器件的低温工作性能。     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V     

低电压低功耗ECL电路设计

首先指出了 ECL电路随着集成度和速度的提高 ,存在着功耗太大的问题 ,进而提出了采用低电压电源以降低功耗 ,为此发展了将串联开关转换成并联开关的技术 ,保证了电路能在低电压下正常工作 ,并由此实现了适合于低电压工作的 ECL电路的开关级设计。从对设计的电路进行的计算机模拟结果表明 ,采用文中提出的并联开关技术设计的电路 ,在电源电压为 -2 .5 V时 ,不仅具有正确的逻辑功能和较高的工作速度 ,且比采用-5 .0 V电源的电路节约了 80 %以上的功耗     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

基于混合电压一电流表示的ECL电路综合方法

基于混合电压-电流的信号表示及对电流、电压信号定义的运算,本文提出了一种ECL电路的混合综合技术。所提出的方法已用一位全加器的设计实例予以演示。本文最后提出了一个适用于电流信号表示和电流运算的代数系统。     

2.5-V bipolar/CMOS circuits for 0.25-μm BiCMOS technology

An ECL circuit with an active pull-down device, operated from a CMOS supply voltage, is described as a high-speed digital circuit for a 0.25-μm BiCMOS technology. A pair of ECL/CMOS level converters with built-in logic capability is presented for effective intermixing of ECL with CMOS circuits. Using a 2.5-V supply and a reduced-swing BiNMOS buffer, the ECL circuit has reduced power dissipation, while still providing good speed. A design example shows the implementation of complex logic by emitter and collector dottings and the selective use of ECL circuits to achieve high performance     

ANALYSIS OF TRANSIENT CHARACTERISTICS OF ECL CIRCUIT AT LOW TEMPERATURE

Detailed analysis on transient characteristics of ECL circuits are performed in this paper, then a relatively exact propagation delay expression applied for all temperatures is presented. The cryogenic characteristics of some dominant parameters contributed to propagation delay are also discussed. The model achieved is suitable for optimum designs of high speed devices and circuits at all temperatures.     

Complementary current-mirror logic

A logic family which operates primarily on current rather than voltage levels is proposed. This family can perform with the high speed of emitter-coupled logic (ECL), and so is a suitable candidate for mainframe computer use. In addition, the inherent gate power dissipation in the absence of an input signal resembles CMOS, making large-scale integration a possibility. Simulated results using 12-GHz n-p-n and 1.2-GHz p-n-p devices show that 120-ps gate delay is possible at a 1-mW power level. The performance of a basic logic cell and ways of forming several types of logic circuits are discussed. Line-driving capability is compared with ECL, and in many situations it is found to compare very favorably in terms of energy requirements as well as line-to-line noise coupling. The potential for multilevel applications is briefly discussed     

A synthesis methodology for ECL circuits based on mixed voltage-current representation

This paper presents a synthesis methodology for ECL circuits based on a mixed voltage-current signal representation and operation defined on the voltage and current signals. The ideas presented in this paper are then demonstrated on the design of an BCL 1-bit full adder. The paper concludes by presenting an algebraic system which is suitable for current signal representation and operation on currents.     

BiCMOS nonthreshold logic for high-speed low-power applications

New high-speed low-power BiCMOS nonthreshold logic (BNTL) circuits are presented. These circuits offers a built-in CMOS and bipolar level conversion and are suitable for reduced power supply voltage. A 4-b carry lookahead generator (CLG) circuit is designed in BNTL, ECL, and CMOS using 0.8-μm BiCMOS technology. Circuit simulations show that this new logic provides speed comparable to or better than that provided by emitter-coupled logic (ECL) for lower power dissipation