Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization

Three-dimensional (3-D) IC physical design problems are usually of higher complexity, with a greatly enlarged solution space due to multiple device structure. In this paper, a new 3-D floorplanning algorithm is proposed for wirelength optimization. Our main contributions and results can be summarized as follows. First, a new hierarchical flow of 3-D floorplanning with a new inter-layer partitioning method. The blocks are partitioned into different layers before floorplanning. A simulated annealing (SA) engine is used to partition blocks with the objective of minimizing the statistical wirelength estimation results. The solution quality is not degraded by the hierarchical flow. Second, floorplans of all the layers are generated in a SA process. Original 3-D floorplanning problem is transformed into solving several 2-D floorplanning problems simultaneously. The solution space is scaled down to maintain a low design complexity. Finally, Experimental results show that our algorithm improves wirelength by 14%-51% compared with previous 3-D floorplanning algorithms. The hierarchical approach is proven to be very efficient and offers a potential way for high-performance 3-D design     

Shortest path planning of a data mule in wireless sensor networks

Data mules are extensively used for data collection in wireless sensor networks (WSNs), which significantly reduces energy consumption at sensor nodes but increases the data delivery latency. In this paper, we focus on minimizing the length of the traveling path to reduce the data delivery latency. We first model the shortest path planning of a data mule as an optimization problem, and propose an optimal model and corresponding solving algorithm. The optimal model solution has high time complexity, mainly due to the parallel optimization of node visit arrangements and data access point (DAP) settings during the solution process, which is to obtain the shortest path result. In order to improve the computational efficiency, we next give the approximate model and its solving algorithm, which is mainly to decompose the path planning problem into the Traveling Salesman Problem (TSP) and nonlinear optimization problem, and optimize the two parts separately. The proposed approach is capable of expressing the influence of the communication range of each sensor node, which is suitable for more general application scenarios than the existing methods. Theoretical analysis and simulation results show that the solution has good performances in terms of path length and computational efforts.

     

Automatic layout synthesis of analog ICs using circuit recognition and constraint analysis techniques

A systematic method for automatic layout synthesis of analog integrated circuit modules is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. These layout constraints are analyzed and prioritized according to the recognized analog circuit topologies and classified net sensitivities. The weighted constraints are then used to drive the physical layout generation process to obtain a high-quality custom circuit layout. An efficient, constraint-driven analog floorplanning technique based on a zone-sensitivity partitioning algorithm is specially developed to generate a slicing floorplan incorporating the layout constraints. This layout synthesis approach has three key advantages. First, it can produce a satisfactory analog circuit performance with negligible degradation due to the layout-introduced parasitic effects. Second, it allows a complete automation for netlist-to-layout synthesis so that the layout tool can be used by VLSI system designers. Finally, this method is quite general and can be applied to handle a wide variety of analog circuits. Experimental results in CMOS operational amplifiers and a comparator are presented.     

基于细胞神经网络的从阴影恢复形状的新方法

细胞神经网络(CNN)是一种实时处理信号的大规模非线性模拟电路,它的连续时间特点以及局部互连特点使其可以进行并行计算,并且非常适用于超大规模集成电路(VLSI)的实现.本文针对从阴影恢复形状(SFS)问题,提出了一种基于硬件退火CNN的能量函数优化方法,并对该方法进行了详细分析,给出了实例的仿真结果,验证了该方法的有效性.该方法为并行处理算法,具有运算量小、易于大规模VLSI集成实现,且能够克服局部极小等优点,可以使SFS问题得到实时的处理.     

Optimal interconnect diagnosis of wiring networks

Interconnect diagnosis is an important problem in very large scale integration (VLSI), multichip module (MCM) and printed circuit board (PCB) production. The problem is to detect and locate all the shorts, opens and stuck-at faults among a set of nets using the minimum number of parallel tests. In this paper, we present worst-case optimal algorithms and lower bounds to several open problems in interconnect diagnosis     

Model for yield and manufacturing prediction on VLSI designs foradvanced technologies, mixed circuitry, and memories

A yield model has been developed and validated for use in optimizing VLSI floorplanning in next generation products. The model successfully predicts yields and costs on a variety of products in CMOS, bipolar, and BiCMOS process flows from low cost DIP's and QFP's to more complex PGAs and flip chip package solutions. This paper discusses how the model was developed for use in evaluating the viability of next generation VLSI solutions. The model takes into account variables such as layout sensitivity, circuit redundancy, and learning curves in wafer, assembly, and test processing in determining the total manufacturing cost     

基于遗传算法的VLSI布图规划方法

提出了一种有效的基于遗传算法的VLSI布图规划方法.在染色体的表达中,对软模块不同形状和硬模块的布局方向进行了编码,并设计了有效的启发式解码方法进行解码.测试结果表明,该算法比已有算法得到了更优的结果.     

Development of robust interconnect model based on design ofexperiments and multiobjective optimization

When designing an integrated circuit, it is important to take into consideration random variations arising from process variability. Traditional optimization studies on VLSI interconnect attempt to find the deterministic optimum of a cost function but do not take into account the effect of these random variations on the objective. We have developed an effective methodology based on TCAD simulation and design of experiments to optimize interconnect including the effects of process variations. The aim of the study is to search for optimum designs that both meet the performance specification and are robust with respect to process variations. A multiobjective optimization technique known as Normal Boundary Intersection is used to find evenly-spaced tradeoff points on the Pareto curve. Designers can then select designs from the curve without using arbitrary weighting parameters. The proposed methodology was applied to a 0.12 μm CMOS technology; optimization results are discussed and verified using Monte Carlo simulation     

Optimal routing in circuit switched communication networks

Consideration is given to the optimal circuit routing problem in an existing circuit-switched network. The objective is to find circuit routing which accommodates a given circuit demand while maximizing the residual capacity of the network. In addition, the cost of accommodating the circuit demand should not exceed a given amount. Practical considerations require that a solution be robust to the variations in circuit demand and cost. The objective function for the optimal circuit routing problem is not a smooth one. In order to overcome the difficulties of nonsmooth optimization, the objective function is approximated by smooth concave functions. The optimization algorithm for the circuit routing problem is obtained as a limiting case of the sequence of optimal routing strategies for the corresponding smooth convex optimization problems, and the proof of its convergence to the optimal solution is given. An approach to calculating the optimal multicommodity flow is presented. The optimization algorithm efficiently handles networks with a large number of commodities, satisfies the robustness requirements, and can be used to solve circuit routing problems for large networks     

Automated hierarchical CMOS analog circuit stack generation withintramodule connectivity and matching considerations

An efficient automated layout for CMOS transistors in analog circuits is described. The matching requirements are used as the primary constraint on the analog layout; however, parasitic capacitances and area considerations are also included. A designer-chosen arbitrary circuit partition from the schematic can be used to generate the corresponding layout as an optimum stack of transistors with complete intramodule connectivity. The transistor stack generation is performed by representing the circuit with a diffusion graph and recursively fragmenting the graph until the base constructs are reached. For each of the modules, the port structures are also created. These port structures are considered as part of the module area and parasitic optimization procedure. With aspect-ratio-related constraints, the procedure allows optimal floorplanning. The results are demonstrated through several examples     

VLSI电路划分问题的分散搜索算法

电路划分是超大规模集成电路(VLSI)设计自动化中的一个关键阶段,是NP困难的组合优化问题.本文把基于顶点移动的Fiduccia-Mattheyses(FM)算法结合到分散搜索算法框架中,提出了电路划分的分散搜索算法.算法利用FM算法进行局部搜索,利用分散搜索的策略进行全局搜索.为满足该方法对初始解的质量和多样性的要求,采用贪心随机自适应搜索过程(GRASP)和聚类相结合的方法产生初始解.实验结果表明,算法可以求解较大规模的电路划分实例,且与基于多级框架的划分算法hMetis相比,划分的质量有明显的提高.     

Comparative analysis of the Lyapunov function for different strategies of analogue circuits design

Generalized methodology has been developed for analogue circuits design based on applying the optimal control theory. The problem of time optimal system design was defined as a classical functional optimization problem of the optimal design theory. In this case the process of analogue circuits design is mathematically defined as a dynamic control system. In this context the minimization problem of the processor time of designing can be formulated as a minimization problem of the response time of dynamic system. In order to analyze the properties of such a system, it is proposed to use the concept of the Lyapunov dynamic system function. Using this function and its time derivative a special function has been built that allows us to predict the total processor time of circuit design by using the characteristics of the initial period of designing. Numerical results indicate the possibility of predicting the processor time of different design strategies in terms of the special function behavior.     

Applying Improved Convolutional Neural Network in Image Classification

In order to solve the poor accuracy problem which caused by the gradient descent easily fail into local optimum during the training process and the noise interference in process of feature extracting. This paper presents an integrated optimization method of simulated annealing (SA) and Gaussian convolution based on Convolutional Neural Network (CNN). Firstly, the improved algorithm extract some features from the central feature of a model as priori information, and find the optimal solution as initial weights of full-connection layer by simulating annealing, so as to accelerate the weight updating and convergence rate. Secondly, using the Gaussian convolution method, this paper can smooth image to reduce noise disturbing. Finally, the improved integrated optimization method is applied to the MNIST and CIFAR-10 databases. Simulation results show that the accuracy rate of the integrated network is improved through the contrastive analysis of different algorithms.

     

P/G Pin Position-Aware Voltage Island Floorplanning For IR Drop Security and avoidance in Flip Chip Designs of FIR Filter

In flip-chip design, voltage drop reduction in the power ground network has become a challenging problem particularly in the modern Multiple Supply Voltage(MSV) designs. An effective P/G network design and floorplanning- based solutions helps to produce a quality power plan in the layout. Hence, this paper proposes an iterative MSV floorplanning methodology that performs modifications in the existing floorplan representation that satisfies the voltage island constraint and produce an IR drop-aware quality layout. Furthermore, the proposed methodology is integrated with commercial tool design flow to analyze the reduction of IR drop in the layout. Two simulation-based experiments are performed in this paper to showcase the significance of this work. Firstly, it presents the simulation results that benchmark the proposed idealogy in non-flip chip designs. Secondly, the presented framework is integrated in flip-chip layouts of FIR design operating with two voltage islands for low power consumption. To understand the ability of the proposed floorplanning approach, the simulation were performed for two different sized P/G mesh structure for various mesh width. Experimental results from both simulations demonstrate that the proposed MSV floorplanning technique is effective in reducing IR drop while optimizing the design for low power dissipation.

     

Minimization of delay and crosstalk in high-speed VLSIinterconnects

Design optimization of time responses of high-speed VLSI interconnects modeled by distributed coupled transmission line networks is presented. The problem of simultaneous minimization of crosstalk, delay and reflection is formulated into minimax optimization. Design variables include physical/geometrical parameters of the interconnects and parameters in terminating/matching networks. A recently published simulation and sensitivity analysis technique for multiconductor transmission lines is expanded to directly address the VLSI interconnect environment. The new approach permits efficient physical/geometrical oriented interconnect design using exact gradient based minimax optimization. Examples of interconnect optimization demonstrate significant reductions of crosstalk, delay, distortion and reflection at all vital connection ports. The technique developed is an important step towards optimal design of circuit interconnects for high-speed digital computers and communication systems     

Fast floorplanning for effective prediction and construction

Floorplanning is a crucial phase in VLSI physical design. The subsequent placement and routing of the cells/modules are coupled very closely with the quality of the floorplan. A widely used technique for floorplanning is simulated annealing. It gives very good floorplanning results but has major limitation in terms of run time. For circuit sizes exceeding tens of modules simulated annealing is not practical. Floorplanning forms the core of many synthesis applications. Designers need faster prediction of system metrics to quickly evaluate the effects of design changes. Early prediction of metrics is imperative for estimating timing and routability. In this work we propose a constructive technique for predicting floorplan metrics. We show how to modify the existing top-down partitioning-based floorplanning to obtain a fast and accurate floorplan prediction. The prediction gets better as the number of modules and flexibility in the shapes increase. We also explore applicability of the traditional sizing theorem when combining two modules based on their sizes and interconnecting wirelength. Experimental results show that our prediction algorithm can predict the area/length cost function normally within 5-10% of the results obtained by simulated annealing and is, on average, 1000 times faster     

Low-Complexity DOA Estimation Based on Constraint Solution Space

The Weighted Subspace Fitting (WSF) algorithm is one of the universal algorithms in Direction-Of-Arrival (DOA) estimation, which is of high accuracy. However, it involves the multi-dimensional nonlinear optimization problem, and the computational complexity is usually high. In this paper, we propose a low-complexity DOA estimation algorithm based on constraint solution space. Firstly, we use ESPRIT algorithm to limit the solution space around the best solution and reduce the computational range. Then, we find the best solution in a smaller solution space constraint by Cramr-Rao Bound (CRB), and seek repeatedly until reaching the global optimal solution of WSF algorithm by using the space of the best solution. By limiting the searching process in smaller solution space, this strategy controls the direction of convergence and reduces computational complexity. The experimental results show that this algorithm needs less iterations when the same DOA accuracy is required, and the computational complexity is apparently reduced.

     

Hybrid genetic-paired-permutation algorithm for improved VLSI placement

This paper addresses Very large-scale integration (VLSI) placement optimization, which is important because of the rapid development of VLSI design technologies. The goal of this study is to develop a hybrid algorithm for VLSI placement. The proposed algorithm includes a sequential combination of a genetic algorithm and an evolutionary algorithm. It is commonly known that local search algorithms, such as random forest, hill climbing, and variable neighborhoods, can be effectively applied to NP-hard problem-solving. They provide improved solutions, which are obtained after a global search. The scientific novelty of this research is based on the development of systems, principles, and methods for creating a hybrid (combined) placement algorithm. The principal difference in the proposed algorithm is that it obtains a set of alternative solutions in parallel and then selects the best one. Nonstandard genetic operators, based on problem knowledge, are used in the proposed algorithm. An investigational study shows an objective-function improvement of 13%. The time complexity of the hybrid placement algorithm is O(N²).     

A VLSI 8 × 8 MIMO Near-ML Detector with Preprocessing

Multiple-input multiple-output (MIMO) systems are of significant interest due to their ability to increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits. A particularly difficult part of these systems is the detector, where the optimal maximum-likelihood solution is desirable, but cannot be directly implemented due to its exponential complexity. This paper addresses this challenge and presents a digital circuit design for an 8×8 MIMO detection problem. A key feature is the integrated channel preprocessing unit, which performs the channel decomposition functions that are either omitted or performed “off-line” in other designs. The proposed device achieves near maximum likelihood bit error rate results at 57.6 Mbps. Other novelties include a high speed sorting mechanism and power saving features.     

Bridging the gap between design and test

There is general agreement today about pursuing the goal of integrating computer-aided systems for designing and testing VLSI circuits. This goal has been fairly successfully attained for the static functional test by automatic adaption of simulation bit patterns to the ATE. But better use of ATE resources has to be achieved. There is no satisfying solution to the problem of adapting simulation bit patterns for the analysis of dynamic circuit behavior to corresponding test patterns for the dynamic test.In this paper we intend to demonstrate that a knowledge based system may be used to realize integration of designing and testing functions in a meaningful and cost-effective way.