Full‐Duplex Operations in Wireless Powered Communication Networks

In this paper, a wireless powered communication network (WPCN) consisting of a hybrid access point (H‐AP) and multiple user equipment (UE), all of which operate in full‐duplex (FD), is described. We first propose a transceiver structure that enables FD operation of each UE to simultaneously receive energy in the downlink (DL) and transmit information in the uplink (UL). We then provide an energy usage model in the proposed UE transceiver that accounts for the energy leakage from the transmit chain to the receive chain. It is shown that the throughput of an FD WPCN using the proposed FD UE (FD‐WPCN‐FD) can be maximized by optimal allocation of the UL transmission time to the UE by solving a convex optimization problem. Simulation results reveal that the use of the proposed FD UE efficiently improves the throughput of a WPCN with a practical self‐interference cancellation capability at the H‐AP. Compared to the WPCN with FD H‐AP and half‐duplex (HD) UE, FD‐WPCN‐FD achieved an 18% throughput gain. In addition, the throughput of FD‐WPCN‐FD was shown to be 25% greater than that of WPCN in which an H‐AP and UE operated in HD.     

一种全数字化载波频偏估计器算法

本文提出一种适合ＱＡＭ调制信号的全数字经载波频偏观测器算法,它用于不再采用锁相环同步器的全数字接收机中直接测量频偏的大小,文中提出了频偏观测器算法,接着引入频偏的卡尔曼滤波算法,最终把频偏观测器与卡尔曼滤波器相结合构成了频偏估计器,为存在较大偏的移动通信信道中解决载波同步问题提供了一种实现方案。     

A Frequency Divider Implemented With a Subharmonic Mixer and a Divide-by-Two Divider

This letter proposes a divide-by-four injection-locked frequency divider (ILFD) with the use of a subharmonic mixer and a divide-by-two frequency divider (D2FD). The D2FD circuit consists of a two-stage differential CMOS ring oscillator with n-MOS switches directly coupled to its differential outputs, the measured phase noise of the D2FD is -97 dBc/Hz at 1-MHz offset from the free running frequency of 1.08GHz. The low-voltage CMOS divide-by-four FD (D4FD) has been implemented with the UMC 0.18-mum 1P6M CMOS technology and the power consumption is 9 mW at the supply voltage of 1.2 V. At the input power of 0 dBm, the D4FD can function properly with about 330-MHz locking range from 4.15 to 4.48GHz     

Link selection based on switching between full‐duplex and half‐duplex modes

Multiple‐input multiple‐output systems can achieve a full sum rate (SR) via full duplex (FD). However, its performance is degraded by self‐interference (SI) that occurs between the transmitter and receiver at the same node and thus is constrained by error floors. Conversely, half duplex (HD) can avoid the SI albeit at lower spectral efficiency, and the slope of its error curve is determined by the diversity order. In this study, a link selection scheme based on switching between FD and HD is examined as a simple method to improve the bit error rate (BER) performance of FD systems. In the proposed link selection algorithm, either FD or HD is selected based on the received minimum distance and signal‐to‐interference plus noise ratio. Simulation results indicate that the proposed hybrid FD/HD switching system offers significant BER performance improvement when compared with that of the conventional FD and FD based on only the received minimum distance under the same fixed SR. Under relatively sufficient SI cancellation, it is demonstrated to outperform the HD with a diversity advantage in low and medium signal‐to‐noise ratio region.     

FIR, Allpass, and IIR Variable Fractional Delay Digital Filter Design

This paper presents two-step design methodologies and performance analyses of finite-impulse response (FIR), allpass, and infinite-impulse response (IIR) variable fractional delay (VFD) digital filters. In the first step, a set of fractional delay (FD) filters are designed. In the second step, these FD filter coefficients are approximated by polynomial functions of FD. The FIR FD filter design problem is formulated in the peak-constrained weighted least-squares (PCWLS) sense and solved by the projected least-squares (PLS) algorithm. For the allpass and IIR FD filters, the design problem is nonconvex and a global solution is difficult to obtain. The allpass FD filters are directly designed as a linearly constrained quadratic programming problem and solved using the PLS algorithm. For IIR FD filters, the fixed denominator is obtained by model reduction of a time-domain average FIR filter. The remaining numerators of the IIR FD filters are designed by solving linear equations derived from the orthogonality principle. Analyses on the relative performances indicate that the IIR VFD filter with a low-order fixed denominator offers a combination of the following desirable properties including small number of denominator coefficients, lowest group delay, easily achievable stable design, avoidance of transients due to nonvariable denominator coefficients, and good overall magnitude and group delay performances especially for high passband cutoff frequency ( ges 0.9pi) . Filter examples covering three adjacent ranges of wideband cutoff frequencies [0.95, 0.925, 0.9], [0.875, 0.85, 0.825], and [0.8, 0.775, 0.75] are given to illustrate the design methodologies and the relative performances of the proposed methods.     

Device Design and Optimization Methodology for Leakage and Variability Reduction in Sub-45-nm FD/SOI SRAM

Ultrathin-body fully depleted silicon-on-insulator (UTB FD/SOI) devices have emerged as a possible candidate in sub-45-nm technologies and beyond. This paper analyzes leakage and stability of FD/SOI 6T SRAM cell and presents a device design and optimization strategy for low-power and stable SRAM applications. We show that large variability and asymmetry in threshold-voltage distribution due to random dopant fluctuation (RDF) significantly increase leakage spread and degrade stability of FD/SOI SRAM cell. We propose to optimize FD devices using thinner buried oxide (BOX) structure and lower body doping combined with negative back-bias or workfunction engineering in reducing the RDF effect. Our analysis shows that thinner BOX and cooptimization of body doping and back biasing are efficient in designing low-power and stable FD/SOI SRAM cell in sub-45-nm nodes.     

A Dual-Capture Wide Dynamic Range CMOS Image Sensor Using Floating-Diffusion Capacitor

A dual-capture wide dynamic range CMOS image sensor using an in-pixel floating-diffusion (FD) storage capacitor is proposed. The proposed structure uses the FD as a storage capacitor. The potential of the FD node is read out using a floating-gate capacitor without a contact metallization of the FD node to reduce the leakage. The proposed sensor was fabricated using a 0.35-mum CMOS process. The chip includes 320 times 240 pixels whose pitch is 5.6 mum and whose fill factor is 36%. The measurement results show 100-dB dynamic range, and the leakage at the non-metalized FD is reduced to about one-third of that of the conventional FD with the contact metallization.     

On the diversity gain region of the dynamic decode-and-forward relay-assisted Z-channel

In an interference-limited system, the interference forwarding by a relay enhances the interference level and thereby enables the cancellation of the interference. In this work, interference forwarding by a half-duplex dynamic decode-and-forward (HD DDF) relay in a two-user Z-channel is considered. In the two-user Z-channel, one user is interference-limited while the other user is interference-free. The diversity gain region (DGR), which characterizes the tradeoff between the achievable diversity orders between the two users, is an appropriate performance metric for the Z-channel. Closed-form expression for the achievable DGR with the interference forwarding by the HD DDF relay is presented. The multiplexing gain regions (MGRs) where the HD DDF protocol achieves better DGR over the direct transmission scheme, full-duplex decode-and-forward (FD DF) and FD partial DF relay assisted Z- channel are identified. The HD DDF protocol is shown to achieve better DGR than the FD DF and FD PDF relay for a large range of MGR. The achievable DGRs for the HD DDF, FD DF, and FD PDF relay-assisted Z-channel and direct transmission scheme are presented for various interference levels and multiplexing gain pairs.     

Subthreshold kinks in fully depleted SOI MOSFET's

Measured current-voltage characteristics of scaled, floating-body, fully depleted (FD) SOI MOSFET's that show subthreshold kinks controlled by the back-gate (substrate) bias are presented. The underlying physical mechanism is described, and is distinguished from the well known kink effect in partially depleted devices. The physical insight attained qualifies the meaning of FD/SOI and implies new design issues for low-voltage FD/SOI CMOS     

可重用全数字频率检测电路的设计与实现

频率检测模块(FD)作为重要的传感器以及信号处理功能电路,被广泛应用在片上系统(SoC)及数字信号处理(DSP)电路中。在安全芯片产品中,FD作为安全传感器之一,对于芯片安全防护体系有着重要意义。传统的FD检测模块部分或全部由模拟电路实现,这会带来面积、功耗、以及工艺移植性问题。为此,我们尝试使用全数字FD电路对内部主时钟以及外部通信时钟进行频率超限检测。本文将简略叙述FD的原理,并在此基础上阐述数字FD电路设计,解释数字FD在实现过程遇到的难点与性能权衡,给出相应的解决方案及依据。本文所述的FD电路设计与实现方法具有一定的借鉴和参考意义。     

AN-aided full-duplex secure transmissions under imperfect self-interference cancellation

This paper considers a full-duplex (FD) secure transmission scheme with aid of the artificial noise deployed at both transmitter and receiver under imperfect self-interference cancellation. The expressions of secrecy and connection outage probabilities are derived, and hence, the secrecy throughput of the proposed scheme is evaluated. The results show that the performance of the proposed FD scheme outperforms that of conventional half-duplex and FD receiver schemes in terms of the secrecy outage probability. In addition, the proposed FD scheme can achieve high secrecy throughput under various locations of the eavesdropper. Especially when the eavesdropper is located close to the transmitter, the secrecy throughput of the proposed FD scheme is nearly double that of the half-duplex scheme with artificial noise injection while that of the scheme with FD jamming receiver goes to zero.     

Variable Fractional Delay Filter Design Using a Symmetric Window

In this paper a numerically efficient method for designing a nearly optimal variable fractional delay (VFD) filter based on a simple and well-known window method is presented. In the proposed method a single window extracted from the optimal filter with fixed fractional delay (FD) is divided into even and odd part. Subsequently, the odd part is discarded and symmetric even part of the extracted window is used to design a family of nearly optimal filters with varying FD. In addition to window extraction, the proposed approach requires filter gain correction which is dependent on the desired FD. Optimum values of the gain correction factor as well as the extracted window can be computed beforehand, which allows us to design a nearly optimal FD filter with arbitrary FD at low numerical costs during runtime. On the basis of the proposed filter design method, the universal structure of VFD filter allowing for change of filter type and length has been proposed. In the paper, three FD filter optimality criteria are considered, which are maximal flatness, Chebyshev (minimax), and least squares.     

Maxflat Fractional Delay IIR Filter Design

Fractional delay (FD) filters are an important class of digital filters and are useful in various signal processing applications. This paper discusses a design problem of FD infinite-impulse-response (IIR) filters with the maxflat frequency response in frequency domain. First, a flatness condition of FD filters at an arbitrarily specified frequency point is described, and then a system of linear equations is derived from the flatness condition. Therefore, a set of filter coefficients can be easily obtained by solving this system of linear equations. For a special case in which the frequency response is required to be maxflat at omega = 0 or pi , a closed-form expression for its filter coefficients is derived by solving a linear system of Vandermonde equations. It is also shown that the existing maxflat FD finite-impulse-response (FIR) and IIR filters are special cases of the FD IIR filters proposed in this paper. Finally, some examples are presented to demonstrate the effectiveness of the proposed filters.     

Estimating fractal dimension with fractal interpolation functionmodels

Fractal dimension (FD) is a feature which is widely used to characterize medical images. Previously, researchers have shown that FD separates important classes of images and provides distinctive information about texture. The authors analyze limitations of two principal methods of estimating FD: box-counting (BC) and power spectrum (PS). BC is ineffective when applied to data-limited, low-resolution images; PS is based on a fractional Brownian motion (fBm) model-a model which is not universally applicable. The authors also present background information on the use of fractal interpolation function (FIF) models to estimate FD of data which can be represented in the form of a function. They present a new method of estimating FD in which multiple FIF models are constructed. The mean of the FD's of the FIF models is taken as the estimate of the FD of the original data. The standard deviation of the FD's of the FIF models is used as a confidence measure of the estimate. The authors demonstrate how the new method can be used to characterize fractal texture of medical images. In a pilot study, they generated plots of curvature values around the perimeters of images of red blood cells from normal and sickle cell subjects. The new method showed improved separation of the image classes when compared to BC and PS methods     

迭层式双折射膜系双频激光器

为了简化双折射双频激光器的结构,减小激光谐振腔的调节难度,增强频差的稳定性,构建了一种以迭层式双折射膜系为双折射元件产生频率分裂的新型双频激光器。迭层式双折射膜系由反射膜、双折射膜和增透膜等层叠组成,不同的膜层独立地完成不同的功能。实验中综合利用横向塞曼效应和He-Ne激光器的腔内双折射效应,获得了约7.5MHz的频差。     

Training sequence optimization: comparisons and an alternativecriterion

Two previously proposed training sequence optimization techniques for channel estimation are compared. One method is based on a frequency-domain (FD) based channel estimation method and the other is based on a time-domain (TD) channel estimation technique. The FD method produces a lower complexity search strategy, but does not always result in the optimal training sequences in terms of the mean-squared channel estimation error. A proof of the superiority of the TD method over the FD method is presented. Based on the proof, an alternative search criterion is proposed, which, in general, provides equivalent or better performance than the FD method while still enjoying the low search complexity     

Full-Duplex Cognitive Radio with RF Energy Harvesting

Wireless Personal Communications - With the development of self-interference suppression techniques, full-duplex (FD) communication is expected to double the spectrum efficiency (SE). In FD based...     

Frequency-Domain Turbo Equalization and Multiuser Detection for DS-UWB Systems

One of the major challenges in direct sequence-ultra wideband (DS-UWB) receiver design is intersymbol interference (ISI). Several equalization schemes to eliminate ISI in DS-UWB systems have been proposed in the literature. It was shown that frequency-domain (FD) equalization techniques can offer better trade off between performance and complexity compared to timedomain equalization schemes for DS-UWB systems on highly dispersive channels. In this paper, we derive low-complexity FD minimum mean square error turbo equalization schemes for single-user binary phase shift keying (BPSK) and quaternary bi-orthogonal keying (4BOK) DS-UWB systems. For multiuser DS-UWB systems, we combine FD turbo equalization schemes with soft interference cancelation to obtain multiuser FD turbo detectors. The bit error rate performance gain due to turbo detection is shown to be significant, particularly for multiuser DS-UWB systems.     

On the performance of two‐user full‐duplex network‐coded cooperation

In this paper, we propose two schemes based on a full‐duplex network‐coded cooperative communication (FD‐NCC) strategy, namely, full‐duplex dynamic network coding (FD‐DNC) and full‐duplex generalized dynamic network coding (FD‐GDNC). The use of full‐duplex communication aims at improving the spectrum efficiency of a two‐user network where the users cooperatively transmit their independent information to a common destination. In the proposed FD‐NCC schemes, the self‐interference imposed by full‐duplexing is modeled as a fading channel, whose harmful effect can be partially mitigated by interference cancellation techniques. Nevertheless, our results show that, even in the presence of self‐interference, the proposed FD‐NCC schemes can outperform (in terms of outage probability) the equivalent half‐duplex network‐coded cooperative (HD‐NCC) schemes, as well as traditional cooperation techniques. Moreover, the ?‐outage capacity, that is, the maximum information rate achieved by the users given a target outage probability, is evaluated. Finally, we examine the use of multiple antennas at the destination node, which increases the advantage of the FD‐NCC (in terms of the diversity‐multiplexing trade‐off and ?‐outage capacity).     

Increased junction breakdown voltages in silicon-on-insulatordiodes

A junction breakdown model and the results of PISCES II simulations are presented for silicon-on-insulator (SOI) devices. This model shows the dependence of breakdown voltage in fully depleted (FD) SOI diode on the backgate bias, the properties of the buried oxide layer, and the device parameters. Breakdown in a thin FD SOI diode is quite different from that observed in a thicker, partially depleted (PD) diode. The analysis is supported by breakdown voltage measurements of separation by implantation of oxygen (SIMOX)-based SOI diodes, the results of which suggest that body breakdown is dominant in FD SOI diodes, and the junction curvature effect is dominant in PD SOI diodes. Furthermore, the results also show that breakdown voltage in the FD SOI diode is higher than their bulk-silicon counterpart and can be further increased by applying the appropriate backgate bias