Advanced backside failure analysis in 65 nm CMOS technology

Due to reducing size of elementary devices, increasing number of metallization levels and decreasing of power supply voltage, the debug and failure analysis of advanced CMOS designs requires the implementation of specific backside sample preparation methodologies and backside measurement flow.This paper describes the diagnosis and backside failure analysis flow implemented to successfully debug a flip-flop cell designed in 65 nm CMOS technology.     

A 144 × 144 Current-Mode Image Sensor With Self-Adapting Mismatch Reduction

We present a novel CMOS continuous-current imager that uses nonvolatile floating-gate charge storage in each pixel for automatic cancellation of fixed-pattern noise (FPN) and vignetting artifacts. We demonstrate the ability to reduce image artifacts over a wide range of incident light intensities. Adaptation occurs for each pixel in parallel, using a unique pixel circuit that employs hot-electron injection in stable feedback to accurately match a reference value. The adaptation mechanism stores a reference image, which may be uniform for FPN cancellation or nonuniform for various imaging applications. The design has been fabricated in a commercially available 3-metal, 2-poly 0.5-mum standard CMOS technology. Experimental results confirm the ability to reduce the FPN variance by a factor of 178x at the intensity at which adaptation was performed, and by a factor of 34x over five orders of magnitude of intensity. Adaptation takes as little as 4 s and the 144 times 144 image can be acquired at 0.9 frames/s. During normal operation, the chip consumes 140 muW under standard office lighting conditions at room temperature.     

1.8 V–3 GHz CMOS limiting amplifier with efficient frequency compensation

A compact robust CMOS limiting amplifier (LA) for high data traffic optical links is presented in this work. The core considers two different blocks. First, four common-source inverter amplifiers are included, which optimize the gain-bandwidth product of the structure. And second, two additional compensation stages are placed strategically between the gain stages alleviating the pernicious load effect. These stages develop two different compensation techniques simultaneously thus increasing the bandwidth. The proposed design consumes 113 mW with a single 1.8 V supply. It achieves a cut-off frequency up to 3 GHz and provides a gain of 21 dB. The circuit is packaged in a QFN24 and mounted on a commercial FR4 PCB.     

A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner

A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner is presented. Compared with the traditional one, the proposed Wilkinson power combiner could lower down the insertion loss and reduce the die area by eliminating the quarter-wavelength transmission lines while preserving the characteristics of Wilkinson power combining and good port isolation. The presented power amplifier has been implemented in 65 nm CMOS process and achieves a measured saturated output power of 10.61 dBm and a peak power added efficiency of 8.13% at 73 GHz with only 1 V power supply. The die area including pads is 1.23×0.45 mm², while the power combiner only occupies 200×80 μm².     

Implementation of plug-and-play ESD protection in 5.5 GHz 90 nm RF CMOS LNAs—Concepts, constraints and solutions

Design and implementation of ESD protection for a 5.5 GHz low noise amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as “plug-and-play”, is used as ESD protection for the RF pins. The consequences of design and process, as well as, the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail. Enhancement in the ESD robustness using additional core-clamp diodes is proposed.     

A 125 GHz millimeter-wave phase lock loop with improved VCO and injection-locked frequency divider in 65 nm CMOS process

In this paper, a CMOS mm-wave phase locked loop (PLL) with improved voltage controlled oscillator (VCO) and injection-locked frequency divider (ILFD) at operational harmonic frequency 125 GHz is presented. The VCO structure uses the bulk effective and MOS varactor capacitor to adjust parasitic capacitor of the cross coupled pair. It obtains 2th harmonic frequency with 24% tuning range (110–140 GHz) by applying?±?1.2 V input voltage variation. The divide-by-4 ILFD circuit uses a cross coupled VCO with three injection transistors acting in linear and nonlinear regions. The frequency dividers such as divided-by-4 ILFD, subsequent current mode logic (CML) and true single phase clock (TSPC) as divider chain with ratio 1/256 are used to synthesize frequency 244 MHz which is compared to reference frequency, 244 MHz in the PLL. Simulation results of the proposed PLL circuit are obtained after extracting post layout (with total chip size of 0.29 mm²) in 65 nm CMOS standard technology and @ 1.2 V power supply voltage. The obtained results confirm theoretical relations and indicate that the proposed circuit has good figure of merit (FoM), and higher tuning range and lower die area than the recent designs.

     

SLM device for 193 nm lithographic applications

The imaging capability of a new spatial light modulator, (SLM), a custom MEMS device is presented. Low k₁ factor aerial image measurements show the suitability of the SLM device for a variety of uses including optical maskless lithography (OML) applications.Collaborating with ASML partner companies, a fully programmable 11-million micro-mirror SLM device was designed, fabricated, and tested. Innovative MEMS manufacturing techniques were developed to fabricate the very large number of micro-mirrors on the underlying mixed-signal CMOS control circuitry. The individual eight-micron square mirrors were designed to support conventional, attenuated, and alternating phase-shift lithography.     

6.8 GHz monolithic oscillator fabricated by 0.35 μm CMOStechnologies

A 6.8 GHz CMOS monolithic oscillator with a 5.9 dBm output power has been demonstrated by 0.35 μm 1P4M CMOS technologies. The oscillator was designed based on a home-made modified BSIM3v3 large-signal model, where the high-frequency parasitics were included. In addition, on chip spiral inductors and MIM capacitors for the resonant circuit were characterised and used in this monolithic oscillator circuit     

High linearity,low power RF mixer design in 65 nm CMOS technology

A design of RF down-conversion Gilbert-Cell, with 65 nm CMOS technology, at a supply voltage of 1.8 V, with a new degenerating structure to improve linearity. This architecture opens the way to more integrated CMOS RF circuits and to achieve a good characteristics in terms of evaluating parameters of RF mixers with a very low power consumption (2.17 mW). At 1.9 GHz RF frequency; obtained results show a third order input intercept point (IIP3) equal to 11.6 dBm, Noise Figure (NF) is 4.12 dB, when conversion gain is 8.75 dB.     

Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm

Classical scaling equations which estimate parameters such as circuit delay and energy per operation across technology generations have been extremely useful for predicting performance metrics as well as for comparing designs across fabrication technologies. Unfortunately in the CMOS deep-submicron era, the classical scaling equations are becoming increasingly less accurate and new practical scaling methods are needed. We curve fit second and third-order polynomials to circuit delay, energy, and power dissipation results based on HSpice simulations utilizing the Predictive Technology Model (PTM) and International Technology Roadmap for Semiconductors (ITRS) models. While the classical scaling equations give differences as much as 83×from the predictions of PTM and ITRS models, our predictive polynomial models with table-based coefficients yield a coefficient of determination, or R², value of greater than 0.95.     

NEMS switch with 30 nm-thick beam and 20 nm-thick air-gap for high density non-volatile memory applications

We developed two types of titanium nitride (TiN) based nanoelectromechanical systems (NEMS) switches with the smallest dimensions ever made by typical “top-down” complementary metal–oxide–semiconductor (CMOS) fabrication technology. NEMS cantilever switch (NCLS) and NEMS clamp switch (NCS) with 30 nm-thick TiN beam and 20 nm-thick air-gap were successfully fabricated and electrically characterized. The fabricated NCLS showed ideal on/off current characteristics with an essentially zero off current, a sub-threshold slope of less than 3 mV/decade, and an on/off current ratio over 10⁵ in air ambient. Also, the NCLS exhibited an endurance of over several hundred of switching cycles under dc and ac bias conditions in air ambient. Suspended beam memory (SBM) cell array structure was suggested for high density non-volatile memory applications.     

Universal MOSFET gate impedance model for 200 MHz–20 GHz frequency range

The scaling of CMOS technology to 100 nm and below and the endless pursuit of higher operating frequencies drives the need to accurately model effects such as gate leakage and the deterioration of transport characteristics that dominate at those feature sizes and frequencies. Current modeling techniques are frequency limited and require different models for different frequency ranges in order to achieve accuracy goals. In the foundry world, high frequency models are typically empirical in nature and significantly lag their low frequency counterparts in terms of availability. This tends to slow the adoption of new foundry technologies for high performance applications such as extremely high data rate serializer/deserializer (SERDES) transceiver cores. However, design cycle time and time to market while transitioning between technology nodes can be reduced by incorporating a re-usable, industry-standard model. This work proposes such a model for device gate impedance that is simulator-friendly, compact, frequency-independent, and relatively portable across technology nodes. This semi-empirical gate impedance model is based on depletion in the poly-silicon gate electrode. The model performs accurately over 200 MHz–20 GHz at different bias conditions and widths and has been verified by measured data in three technology nodes. The model and model parameter behavior are consistent across technology nodes thereby enabling re-usability and portability.     

Very low leakage InGaAs/InAlAs pHEMTs for broadband (300 MHz to 2 GHz) low-noise applications

This paper presents the design, fabrication and characterisation of InGaAs–InAlAs high electron mobility transistors (pHEMTs) suitable for low-frequency LNA designs. Very low levels of leakage, in the order of 0.05 A/cm², are demonstrated by the pHEMTs, which have enabled the implementation of large-geometry, low-noise devices. Transistors with gate widths ranging from 200 μm to 1.2 mm are demonstrated to operate up to frequencies of 30 GHz. These are extremely promising as LNA components for implementation in broadband low-frequency systems as the very low-noise resistance simplifies matching requirements. The levels of leakage observed in our transistors further support the potential of the InGaAs/InAlAs material system as an alternative to Si when the CMOS roadmap comes to an end.     

Evaluation of the ESD performance of local protections based on SCR or bi-SCR with dynamic or static trigger circuit in 32 nm

The reliability of electronic devices against electrostatic discharge stresses is still a severe challenge, particularly for deep sub-micron technologies such as the CMOS 32 nm in this work. The paper presents a comparison between four ESD protections in CMOS 32 nm node. Dynamic and static triggering circuits are investigated and SCR and bi-SCR are compared. Each structure is characterized through TLP and protects up to 2 kV HBM stresses.     

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology

As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to radiation induced soft errors. In this paper, a low cost and highly reliable radiation hardened latch is proposed using 65 nm CMOS commercial technology. The proposed latch can fully tolerate the single event upset (SEU) when particles strike on any one of its single node. Furthermore, it can efficiently mask the input single event transient (SET). A set of HSPICE post-layout simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures, and the comparison results among the latches of type 4 show that the proposed latch reduces at least 39% power consumption and 67.6% power delay product. Moreover, the proposed latch has a second lowest area overhead and a comparable ability of the single event multiple upsets (SEMUs) tolerance among the latches of type 4. Finally, the impacts of process, supply voltage and temperature variations on our proposed latch and previous latches are investigated.     

Roadmap for 22 nm and beyond (Invited Paper)

The down-scaling is still the most important and effective way for achieving the high-performance logic CMOS operation with low power, regardless of its concern for the technological difficulties, and thus, the past shrinking trend of the gate-length has been very aggressive. In this paper, logic CMOS technology roadmap for ‘22 nm and beyond’ is described with ITRS (International Technology Roadmap for Semiconductor) as a reference. In the ITRS 2008 Update published just recently, there has been some significant change in the trend of the gate length. The future gate-length shrinking trend predicted in the past several versions of the ITRS has been too aggressive even for the most advanced semiconductor companies to catch up, and thus, the predicted trend has been amended to be less aggressive from the ITRS 2008 Update, resulting in the delay in the gate-length shrinkage for 3 years in the short term and 5 years in the long term from those predicted in ITRS 2007. Corresponding to this, the pace of the introduction of new technologies becomes slower. For the long term, the limit of the downsizing is a big concern. The limit is expected to be at the gate length of around 5 nm because of the too huge off-leakage current in the entire chip. Until that we will have probably six more generations or ‘technology nodes’, considering that we are now in the so-called 45 nm generation. It would take probably 20–30 years until we reach the final limit, because the duration between the generations will become longer when approaching the limit. In order to suppress the off-leakage current, double gate (DG) or fin-FET type MOSFETs are the most promising. Then, it is a natural extension for DG FETs to evolve to Si-nanowire MOSFETs as the ultimate structure of transistors for CMOS circuit applications. Si-nanowire FETs are more attractive than the conventional DG FETs because of higher on-current conduction due to their quantum nature and also because of their adoptability for high-density integration including that of 3D. Then, what will come next after reaching the final limit of the downsizing? The answer is new algorithm. In the latter half of this century, the application of algorithm used for the natural bio system such as the brains of insects and even human will make the integrated circuits operation tremendously high efficiency. Much higher performance with ultimately low power consumption will be realized.     

Design and characterization of high-voltage NMOS and PMOS devices in standard 0.25 μm CMOS technology

This paper presents the design of high-voltage NMOS and PMOS devices with shallow trench isolation (STI) in standard 0.25 μm/5 V CMOS technology. Breakdown voltages of 20 V for n-channel device with a specific on resistance of 1.06 mΩ cm² and −20 V for p-channel device with a specific on resistance of 2.83 mΩ cm² have been achieved without any modification of existing standard CMOS process.     

Single Event Upset rate determination for 65 nm SRAM bit-cell in LEO radiation environments

The degradation of SRAM bit-cells designed in a 65 nm bulk CMOS technology in a Sun-Synchronous Low Earth Orbit (LEO) ionizing radiation environment is analyzed. We propose an inflight SEU rate estimation approach based on a modeled heavy ion cross section as opposed to the standard experimental characterization. Effects of irradiation with estimated LET spectrum in SRAM bit cell, i.e. the location of sensitive regions, its tendency to cause upset, magnitude and duration of transient current as well as voltage pulses were determined. It was found with SEU map that 65 nm SRAM bit-cell can flip even if high LET particle strikes in close proximity of bit-cell outside the SRAM bit-cell area. The SEU sensitive parameters required to predict SEU rate of on-board target device, i.e., 65 nm SRAM were calculated with typical aluminum spot shielding using fully physical mechanism simulation. In order to characterize the robustness of scaled CMOS devices, state of the art simulation tools such as Visual TCAD/Genius, GSEAT/Visual Particle, runSEU, were utilized whereas LEO radiation environment assessment, upset rate prediction was accomplished with the help of OMERE-TRAD software.     

3–5 GHz FSK-OOK ultra wideband transmitter based on memristive ring oscillator

The compatibility of a memristor with CMOS technology has attracted the attention of many researchers to explore its application further. In this work, an ultra low-power and low-complexity ultra wideband (UWB) chirp transmitter based on memristive ring oscillator (RO) is designed in 0.18 µm TSMC CMOS technology. The Chirp waveform was chosen because of its low side-lobes and large time-bandwidth product, which allows for more spectrum use. OOK and FSK modulation are supported by the proposed UWB chirp transmitter. The chirp frequency is controlled linearly with time across the pulse duration using memristors. The binary data "1" and "0" are encoded using distinct chirp frequencies in FSK TX. The simulation results show a maximum TX output pulse of 457 mV _Vpp with a pulse width of 21 ns. The overall DC power consumption for a pulse repetition frequency (PRF) of 20 MHz is 0.328 mW, equivalent to an energy consumption of 16.4 pJ/pulse. The simulated output amplitude for OOK TX is 453 mV Vpp with a pulse width of 48 ns and a PSD of ? 10 dB over a frequency range of 3.2 to 4.8 GHz. The overall power consumption at 10 MHz PRF is 0.136 mW, which corresponds to an energy consumption of 13.6 pJ/pulse.