Experimental power cycling on insulated TRIAC package: Reliability interpretation thanks to an innovative failure analysis flow

This paper presents the insulated TO-220AB TRIAC package aging when these devices are subjected to experimental power cycling test with various case temperature swings (ΔT_case). This study includes reliability tests set-up, results and failure analysis. An innovative failure analysis flow is proposed to identify the failure mechanism implied. This new failure analysis process flow is necessary due to the complex stack of these devices. Finally, thanks to the reliability tests and the complete failure analysis results, the thermal resistance (R_th) change is correlated to the physical defect modification. This whole study gives the first data collection that is required to propose a lifetime prediction model for insulated TO-220AB TRIAC package during power cycling accelerated aging tests.     

Impact of flip-chip packaging on copper/low-k structures

Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth.     

45 nm芯片铜互连结构低k介质层热应力分析

采用铜互连工艺的先进芯片在封装过程中,铜互连结构中比较脆弱的低介电常数(k)介质层,容易因受到较高的热机械应力而发生失效破坏,出现芯片封装交互作用(CPI)影响问题.采用有限元子模型的方法,整体模型中引入等效层简化微小结构,对45 nm工艺芯片进行三维热应力分析.用该方法研究了芯片在倒装回流焊过程中,聚酰亚胺(PI)开口、铜柱直径、焊料高度和Ni层厚度对芯片Cu/低κ互连结构低κ介质层应力的影响.分析结果显示,互连结构中间层中低κ介质受到的应力较大,易出现失效,与报道的实验结果一致;上述四个因素对芯片低κ介质中应力影响程度的排序为:焊料高度＞PI开口＞铜柱直径＞Ni层厚度.     

Mechanical integrity evaluation of low-k device with bump shear

The mechanical integrity of low-k dielectric films has brought many process challenges in both front-end integration and back-end assembly, mostly due to possible interfacial delamination and fractures within the low-k films. From a packaging point of view, it is important to have an assessment of the integrity of the low-k stack before the device is fully assembled and the time-consuming full package evaluation is started. Some of the methods that are presently used to evaluate devices with low-k films either do not reflect the real stress situation in a package (such as 4-point bend), or introduce a mixed die-solder failure mode (such as die pull), which makes the results hard to interpret. In this paper, an evaluation method using solder bump shear is introduced. The solder joints are electroplated with a Cu stud as part of the under bump metallization. When the testing parameters are carefully optimized, bump shear can induce a failure in the low-k stack. By analyzing the maximum load of the shear test and the characteristics of the load curves, die with different interlayer dielectric materials and locations on the die with different interconnect metal densities can be effectively differentiated. A finite-element model is established and fracture mechanics methodologies are utilized to interpret the results of the bump shear.     

Backside failure analysis case study: Implementation of innovative Local Backside Deprocessing technique

This paper describes a failure analysis case study where innovative Local Backside Physical characterization technique was performed on an automotive custom Mix-Mode device.The full analysis flow is presented, starting with backside sample preparation in order to perform a backside electrical localization of the defect. Then the multiple challenges of that approach were discussed. The continuous need of decreasing the analysis cycle time was addressed without affecting the success ratio of such analysis flow. The part mechanical degradation was avoided with a local removal of the Silicon. That highly localized technique granted a direct access to the fault site.The tools and process used for this case are fully described underlining the main advantages of this technique in comparison to the global backside deprocessing or to other characterization techniques.That successful development was achieved while determining the failure mechanism, in correlation with the failure mode of the qualification reject.     

Investigation of the delamination mechanism of the thin film dielectric structure in flip chip packages

As the electronics industry continues its efforts in miniaturizing the integrated circuit (IC), an IC chip with copper/low-k stacked Back End of Line (BEoL) structures has been developed for reducing R-C delay in order to obtain high-speed signal communication. However, its reliability might become a concern owing to the considerably lower adhesive strength, as well as the greater coefficient of thermal expansion (CTE) of the low-k materials. In this paper, the global-local finite element method, specified boundary condition (SBC) method, is employed as a bridge to estimate the impact from package level to the deep submicron BEoL structure of the flip chip package. The results show that the defect in the stacking structure at the center of the silicon has a lower tendency to crack than that at the corner region. In addition, the higher underfill CTE shows the disadvantage of the defect.     

Under bump metallurgy study on copper/low-k dielectrics for fine pitch flip chip packaging

Because the semiconductor speed increases continuously, more usage of low-k dielectric materials to enhance the performance in Cu chips has taken place over the past few years. The implementation of copper (Cu) as an interconnect, in conjunction with the ultra-low-k materials as interlevel dielectrics or intermetal dielectrics in the fabrication of ultra-large-scale integrated circuits, has been used in the semiconductor community worldwide, especially for high-speed devices. The objective of this study is to investigate the under bump metallurgy (UBM) characterization with low-k dielectric material used in damascene Cu-integrated circuits. This paper focuses on electroless Ni/Au, Cu/Ta/Cu, and Ti/ Ni(V)/Cu/Au UBM fabrication on 8-in. damascene Cu wafers and flip chip package reliability with Pb-bearing and Pb-free solders. The interfacial diffusion study and bump shear test were carried out to evaluate the bump bonding, and the failure was analyzed with optical microscopy, scanning electron microscopy (SEM), and transmission electron microscopy (TEM). In order to investigate the thermal stability of the UBM system with Pb-free solder, high-temperature aging (above the melting temperature) was performed and each interface between the solder and UBM was observed with optical microscopy, SEM, and TEM, respectively. The failures observed and the modes are reported in the paper.     

倒装焊器件尺寸参数对低k层及焊点的影响

当前。集成电路制造中低k介质与铜互连集成工艺的引入已经成为一种趋势,因此分析封装器件中低矗结构的可靠性是很有必要的。利用有限元软件分析了倒装焊器件的尺寸参数对低k层及焊点的影响。结果表明：减薄芯片,减小PI层厚度,增加焊点高度,增加焊盘高度,减小基板厚度能够缓解低k层上的最大等效应力;而减薄芯片,增加PI层厚度,增加焊点高度,减小焊盘高度,减小基板厚度能够降低焊点的等效塑性应变。     

Packaging of copper/low-k IC devices: a novel direct fine pitch gold wirebond ball interconnects onto copper/low-k terminal pads

The trend toward finer pitch and higher performance devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. Compared to the commonly used aluminum metallization scheme on the traditional silicon dioxide and/or silicon nitride passivation, a Cu/low-k combination offers higher on-chip communication speed and a lower overall device cost. However, the process of packaging Cu/low-k devices has been proven to be difficult, relying either on additional lithography and deposition steps or on costly new process tools. Thus, this paper presents a novel methodology to bond fine pitch Au wire directly onto the Cu/low-k pad structure using the industry standard tool set. A Cu/low-k test vehicle is designed with the required slotted low-k fillings for dual damascene chemical mechanical polishing (CMP) process need. In addition, a thin organic passivation film is developed for coating the exposed Cu/low-k pad temporarily from copper oxidation and to provide a wirebondable surface to form the proper interconnects. A design of experiment is performed to optimize wirebonding parameters [power, time, and ultrasonic gauge (USG) bleed], along with key physical contributors from wafer sawing and die attaching steps that impact the interconnect shear strength and quality. In addition, electrical and optical characterization and surface failure analysis are performed to confirm the feasibility of the technology. Finally, reliability results of the pad structure design and recommendations for further process optimization are presented.     

FIB参数对低介电常数介质TEM样品制备的影响

研究了使用聚焦离子束(FIB)方法制备低k介质的TEM样品时离子束参数对介质微观形貌的影响,发现低k介质的微观形貌与离子束参数具有较强的相关性。传统大离子束流、高加速电压的FIB参数将导致低k介质多孔性增加、致密度下降;且k值越低,离子束参数影响越大。对于亚65nm工艺中使用的k值为2.7的介质,当离子束流减小到50pA、加速电压降低到5kV时,FIB制样方法对介质致密度的影响基本可忽略,样品微观形貌得到了显著改善;而对于65nm工艺中使用的k值为3.0的介质,其微观形貌受离子束参数的影响则相对较小。     

PLL soft functional failure analysis in advanced logic product using fault based analogue simulation and soft defect localization

Soft defect localization (SDL) is an analysis technique where changes in the pass/fail condition of a test are monitored while a laser is scanned across the device under test (DUT). This technique has proven its usefulness for quickly locating defects that are temperature, frequency, and/or voltage dependant, for example, scan logic soft fault. However, due to high sensibility at analogue circuits SDL meets great challenges. This work gives a new flow to analyze soft functional failure in advanced logic products using fault based analogue simulation and SDL. The paper will present one case study illustrating the application of analogue simulation based soft defect localization flow as an effective means to achieve fault isolation.     

Fault isolation in semiconductor product,process, physical and package failure analysis: Importance and overview

Failure analysis plays a major role in all areas of the semiconductor company especially during product development cycle, 1st silicon stage, or in wafer processes and fabrication as well as assembly and package development. Different companies have different FA flows but all FA steps will need to start with fault isolation. Fault isolation is the step to narrow down the focus area of a failing component or product to a manageable area that will allow us to (a) improve success of finding the defect that is causing the failure and, (b) significant speed up turn-around time for analysis.This paper provides an overview of all the available failure analysis on fault isolation methodologies and tools, for device/product level and expanding to package/assembly and PFA level isolation. The aim of the paper is to provide sufficient depth to each topic including some case studies to emphasize the key points related to each methodology. The tutorial will also cover some future directions/roadmaps.     

TEM样品制备辅助研究介质层可靠性失效机理

研究了TEM样品制备条件对Cu/低k制程ILD TDDB失效样品及含更低介电常数(k=2.7)介质层样品的TEM成像质量的影响,发现在一定的样品制备条件下低介电常数介质的疏松特性可在TEM成像时得到增强显示,进而揭示了某Cu/低k制程ILD TDDB可靠性失效样品的失效机理为芯片制造过程中介质层沉积温度异常导致其疏松特性增强,介电常数降低,从而导致其电绝缘性能下降而引起TDDB可靠性测试项目失效.     

Reliability study of 3D IC packaging based on through-silicon interposer (TSI) and silicon-less interconnection technology (SLIT) using finite element analysis

Three-dimensional (3D) integration using the through-silicon via (TSV) approach becomes one promising technology in 3D packaging. 2.5D through-silicon interposer (TSI) is one of the applications of TSV technology, which provides a platform for realizing heterogeneous integration on the TSI interposer. However, TSV manufacturing faces several challenges including high cost. Si-less interconnection technology (SLIT) could overcome such challenges and provide the similar function and benefits as TSI interposer. In SLIT technology, TSVs and silicon substrate are eliminated and the back-end-of-line (BEOL) structures are the same as that in the TSI interposer. Thermo-mechanical reliability is still one important concern under process condition and thermal cycling (TC) test condition for both packaging technologies. In this study, solder joint reliability has been investigated and compared for both packaging technologies through finite element analysis (FEA). Reflow process induced low-k stress and package warpage have also been simulated and compared between packages with TSI and SLIT technologies. The simulation results show that SLIT-based package has comparable micro bump TC reliability as TSI-based package, but SLIT-based package has better C4 joint TC reliability than TSI-based package. SLIT-based package also has lower reflow-induced package warpage and low-k stress than TSI-based package. FEA simulation results verify that SLIT-based packaging is one of promising packaging technologies with good thermo-mechanical performance and cost efficiency.     

Failure modes and effects analysis for high-power GaN-based light-emitting diodes package technology

In this study, nondestructive test is developed to analyze the structure failure of LED package. The relationship between thermal resistance analysis and LED package failure structure is build with T3Ster thermal transient tester and scanning electron microscope (SEM). The failure LED device with defect in the attaching layer and gap between LED chip and copper are designed advisedly. The failure factors of LED package have been measured with thermal resistance analysis and SEM cross-section images. The thermal dissipation performance of LED with defect in the attaching layer is indicated by thermal resistance analysis combined with SEM cross-section images. The blister in attaching layer results in 4.4 K/W additional thermal resistance. The gap between LED chip and copper also makes high additional thermal resistance with 8.6 K/W. Different failures of LED packages are indicated obviously using thermal transfer analysis. The LED package failure structure such as interface defect between solder and cup-shaped copper is able to forecast without destructive measurement.     

Hygrothermal Failures From Small Defects in Lead-Free Solder Reflowed Electronic Packages

Steam-driven delamination failure is a main failure mode in electronics packages during solder reflow. Steam pressures built up within interfaces in packages are sensitive functions of the reflow temperature. The switch to lead-free soldering will raise re-flow temperature by more than 20degC and double the equilibrium saturated steam pressure within defects in the package. The effects of saturated steam driven interfacial failure was analyzed using finite element in this study. Analyses revealed that packages which are thin and made using high thermal conductivity materials are at higher risk of failure than conventional packages made using standard materials. This suggests that electronics made with thick and inexpensive encapsulants are less prone to failure when switched to lead-free solder. Portable and mobile electronics which have low profiles and are made of high thermal conductive encapsulants are at higher risk when switched to lead-free solder reflow. Moreover, the study found that the critical temperature for failure is dependent on the defect size in the package. Reduction of initial defect size can reduce failures in high risk packages in lead-free solder reflow.     

Effect of physical defect on shmoos in CMOS DSM technologies

Dynamic laser stimulation (DLS) techniques based on operating integrated circuits (ICs) become a standard failure analysis technique for soft defect localization. This type of defect is getting more and more common with advanced technology; therefore, DLS is becoming a key technique for defect localization. To perform this technique, the determination of a pass–fail border in shmoo plot is necessary. It is essential to know the impact of the defect on the shmoo plot shape with different defects. This paper presents shmoos plots simulation for common defects encountered in ICs failure analysis. Ability of DLS to detect defects according to their resistances and capacitances values are clearly established. In the second part of this paper, case studies which validate simulations results are presented.     

一种陶瓷方形扁平封装外观缺陷检测方法

提出一种基于机器视觉的陶瓷方形扁平封装外观缺陷检测方法。对于封装外形尺寸较大而缺陷较细微的情形,将待检片分为多个区域与标准样片进行比对检测。首先通过Foerstner特征点检测法提取标准片图像的特征点,然后使用随机抽样一致性(RANSAC)图像匹配算法,将所有标准片图像拼接并融合生成一张标准片全幅面模板,再将待检片分区与标准片模板进行序贯比对,以提取可疑区域,最后利用支持向量机(SVM)分类器对可疑区域进行筛选分类。实验结果表明,这种方法不仅克服了传统视觉检测过程中视野范围与图像分辨率相互制约的矛盾,且对陶瓷方形扁平封装表面缺陷具有较高的检出率。     

碱性抛光液在CMP过程中对低k介质的影响

以p型111硅片为衬底,经过旋涂固化制备低介电常数(低k)材料聚酰亚胺。经过化学机械抛光(CMP)过程,考察实验前后低k材料介电性能的变化。实验中分别使用阻挡层抛光液、Cu抛光液以及新型抛光液对低k材料进行抛光后,利用电参数仪对低k材料进行电性能测试。结果显示,低k材料介电常数经pH值为7.09新型抛光液抛光后,k值由2.8变为2.895,漏电流在3.35 pA以下,去除速率为59 nm/min。经新型抛光液抛光后的低k材料,在电学性能等方面均优于阻挡层抛光液和Cu抛光液,抛光后的低k材料的性能能够满足应用要求。     

Forouhi-Bloomer离散方程在低k材料光学表征上的应用

半导体工艺中对低k介质材料的精确表征是工艺监控的重要环节,传统方法如扫描电子显微镜和透射电子显微镜存在耗时长和破坏性等缺点。使用一种结合了Forouhi-Bloomer离散方程组和宽光谱分光光度法的新方法,对低k薄膜进行光学表征,得到薄膜的折射率n、消光系数k和膜厚d,并将结果与椭偏仪的测量进行比较,证明了使用F-B方程在半导体工艺中精确表征低k材料的能力和这种方法快速无损的优点。