A 3$,times,$5-Gb/s Multilane Low-Power 0.18-$mu{hbox {m}}$ CMOS Pseudorandom Bit Sequence Generator

A low-power, three-lane, pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-mum CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb/s PRBS sequences, measurement results included in this paper have been obtained at only 5 Gb/s due to test setup limitations. The prototype employs a CMOS latch optimized to operate at frequencies close to the of the process and a current-mode logic (CML) MUX with modified active inductor loads for better high-speed large-signal behavior. In order to reduce the power consumption, a quarter-clock rate linear feedback shift register (LFSR) core in a power-efficient parallel architecture has been implemented to minimize the use of power-hungry, high-speed circuitry. Further power reduction has been achieved through the clever partitioning of the system into static logic and CML. In addition, the prototype design produces three uncorrelated 12-Gb/s data streams from a single quarter-rate LFSR core, thereby amortizing the power across multiple channels which lowers the power per channel by 3 times. The total measured power consumption at 5 Gb/s is 131 mW per lane and the calculated figure of merit per lane is 0.84 pJ/bit, which is significantly better than previously published designs.     

Low-Loss and Broadband Asymmetric Broadside-Coupled Balun for Mixer Design in 0.18-$mu{hbox {m}}$ CMOS Technology

This study presents an asymmetric broadside coupled balun with low-loss broadband characteristics for mixer designs. The correlation between balun impedance and a 3D multilayer CMOS structure are discussed and analyzed. Two asymmetric multilayer meander coupled lines are adopted to implement the baluns. Three balanced mixers that comprise three miniature asymmetric broadside coupled Marchand baluns are implemented to demonstrate the applicability to MOS technology. Both a single and dual balun occupy an area of only 0.06 mm². The balun achieves a measured bandwidth of over 120%, an insertion loss of better than 4.1 dB (3 dB for an ideal balun) at the center frequency, an amplitude imbalance of less than 1 dB, and a phase imbalance of less than 5deg from 10 to 60 GHz. The first demonstrated circuit is a Ku-band mixer, which is implemented with a miniaturized balun to reduce the chip area by 80%. This 17-GHz mixer yields a conversion loss of better than 6.8 dB with a chip size of 0.24 mm². The second circuit is a 15-60-GHz broadband single-balanced mixer, which achieves a conversion loss of better than 15 dB and occupies a chip area of 0.24 mm². A three-conductor miniaturized dual balun is then developed for use in the third mixer. This star mixer incorporates two miniature dual baluns to achieve a conversion loss of better than 15 dB from 27 to 54 GHz, and occupies a chip area of 0.34 mm².     

A Single-Chip UHF RFID Reader in 0.18 $mu{hbox {m}}$ CMOS Process

A single-chip UHF RFID reader that integrates all building blocks—including an RF transceiver, IQ data converters, and a digital baseband—is implemented in a 0.18 $mu{hbox {m}}$ CMOS process. A high-linearity RX front-end and a low-phase-noise synthesizer are proposed to handle the large self-interferer, which is a key challenge in the reader RX design. Highly reconfigurable mixed-signal baseband architecture for channel-selection filtering is proposed to achieve power optimization for multi-protocol operation with different system dynamic ranges and data rates. The reader dissipates a maximum power of 276.4 mW when transmitting maximum output power of 10.4 dBm and receiving the tag's response of $-$70 dBm in the presence of $-$5 dBm self-interferer while occupying 18.3 ${hbox {mm}}^{2}$.      

300-mm Low-${hbox {k}}$ Wafer Dicing Saw Development

With the further shrinking of IC dimensions, low- material has been widely used to replace the traditional SiO interlayer dielectric (ILD) in order to reduce the interconnect delay. The introduction of low- material into silicon imposed challenges on dicing saw process. ILD and metal layers peeling and its penetration into the sealing ring of the die during dicing saw are the most common defects. In this paper, the low- material structure and its impact on wafer dicing were elaborated. A practical dicing quality inspection matrix was developed to assess the cutting process variation. A 300-mm CMOS90-nm dual damascene low- wafer was chosen as a test vehicle to develop a robust low- dicing saw process. The critical factors (dicing blade, index speed, spindle speed, cut in depth, test pattern in the saw street, etc.) affecting cutting quality were studied and optimized. The selected C90 Dual damascene low- device passed package reliability tests with the optimized low- dicing saw recipe and process. The further improvement and solutions in eliminating the low- dicing saw peeling were also explored.     

Arithmetic Unit for Finite Field ${rm GF}(2^{m})$

An arithmetic unit (AU) that performs all basic arithmetic operations in the finite field GF(2^m) is presented, where m is an arbitrary integer. The presented finite field AU consists of an arithmetic processor, an arithmetic logic unit, and a control unit. The proposed AU has low circuit complexity and is programmable, so that any error-correcting decoder that operates in GF(2^m) can be easily implemented with this AU.     

Complementary Antiparallel Schottky Barrier Diode Pair in a 0.13- $mu hbox{m}$ Logic CMOS Technology

A shunt-connected complementary antiparallel diode pair (C-APDP) using n- and p-type Schottky barrier diodes (SBDs) in a 0.13-mum CMOS logic process is demonstrated. The structure eliminates the deleterious effects of parasitic capacitance to substrate and reduces the substrate resistance effects. The extrapolated cutoff frequency of C-APDP is above 470 GHz, which demonstrates the potential as a millimeter-wave frequency component. The harmonic power measurements indicate that C-APDPs can generate more than 25 dB higher third harmonic powers than n-type SBDs. The C-APDPs can be integrated with the other devices in CMOS technologies to enable generation and processing of millimeter- and submillimeter-wave signals.     

High-Performance Focal Plane Array Based on InAs–GaSb Superlattices With a 10-$mu{hbox {m}}$ Cutoff Wavelength

We report on the demonstration of a focal plane array based on Type-II InAs-GaSb superlattices grown on n-type GaSb substrate with a 50% cutoff wavelength at 10 mum. The surface leakage occurring after flip-chip bonding and underfill in the Type-II devices was suppressed using a double heterostructure design. The R₀A of diodes passivated with SiO₂ was 23 Omegamiddotcm² after underfill. A focal plane array hybridized to an Indigo readout integrated circuit demonstrated a noise equivalent temperature difference of 33 mK at 81 K, with an integration time of 0.23 ms.     

Microwatt MOSLED Using ${hbox {SiO}}_{rm x}$ With Buried Si Nanocrystals on Si Nano-Pillar Array

Microwatt light emission from a metal-oxide-semiconductor light-emitting diode (MOSLED) made by using SiOx film with buried Si nanocrystals on Si nano-pillar array is demonstrated. The Si nano-pillar array obtained by drying the rapidly self-aggregated Ni nano-dot-masked Si substrate exhibit size, aspect ratio, and density of 30 nm, 10, and 2.8times10¹⁰ cm^-2, respectively. These high-aspect-ratio Si nano-pillar array helps to enhance the Fowler-Nordheim tunneling-based carrier injection and to facilitate the complete relaxation on total internal reflection, thus increasing the quantum efficiency by one order of magnitude and improving the light extraction from the nano-roughened device surface by three times at least. The light-emission intensity, turn-on current and power-current slope of the MOSLED are 0.2 mW/cm² , 20-30 muA, and 3plusmn0.5 mW/A, respectively. At a biased current of 400 muA, the highest external quantum efficiency is over 0.2% to obtain the maximum EL power of > 1 muW. Compared with the same device made on smooth Si substrate under a power conversion ratio of 1 times 10^-4 , such an output power performance is enhanced by at least one order of magnitude.     

A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

Characterization of $m$-Sequences of Lengths $2^{2k}-1$ and $2^{k}-1$ With Three-Valued Cross Correlation

Considered is the distribution of the cross correlation between in-sequences of length 2^2k -1, where m = 2k, and m-sequences of shorter length 2^k -1. New pairs of m -sequences with three-valued cross correlation are found and the complete correlation distribution is determined. Finally, we conjecture that there are no more cases with a three-valued cross correlation apart from the ones proven here.     

Blue-Enhanced PIN Finger Photodiodes in a 0.35-$mu{hbox {m}}$ SiGe BiCMOS Technology

Finger photodiodes in PIN technology are introduced to enhance the responsivity for blue and ultraviolet light. A thick low doped epitaxial layer results in high responsivity and high bandwidth also for red and near-infrared light. Results of PIN finger photodiodes are compared to that of PIN photodiodes for 10- and 15-mum epitaxial intrinsic layer thickness. The cathode finger structure results in a high responsivity of 0.20 A/W (quantum efficiency 61%) for 410-nm light and a bandwidth of 1.25 GHz for 10- mum epi thickness at a reverse bias voltage of 3 V. The rise and fall times with an epitaxial layer thickness of 15 mum are below 1 ns for the wavelength range from 410 to 785 nm.     

$Ka$-Band Low-Loss and High-Isolation Switch Design in 0.13-$mu{hbox {m}}$ CMOS

This paper presents designs and measurements of Ka-band single-pole single-throw (SPST) and single-pole double-throw (SPDT) 0.13-CMOS switches. Designs based on series and shunt switches on low and high substrate resistance networks are presented. It is found that the shunt switch and the series switch with a high substrate resistance network have a lower insertion loss than a standard designs. The shunt SPST switch shows an insertion loss of 1.0 dB and an isolation of 26 dB at >35 GHz. The series SPDT switch with a high substrate resistance network shows excellent performance with 2.2-dB insertion loss and isolation at 35 GHz, and this is achieved using two parallel resonant networks. The series-shunt SPDT switch using deep n-well nMOS transistors for a high substrate resistance network results in an insertion loss and isolation of 2.6 and 27 dB, respectively, at 35 GHz. For series switches, the input 1-dB compression point (1P₁) can be significantly increased to with the use of a high substrate resistance design. In contrast, of shunt switches is limited by the self-biasing effect to 12 dBm independent of the substrate resistance network. The paper shows that, with good design, several 0.13- CMOS designs can be used for state-of-the-art switches at 26-40 GHz.     

Analysis of the ${rm TE}$ -Pass or ${rm TM}$-Pass Metal-Clad Polarizer With a Resonant Buffer Layer

A metal-clad optical polarizer with a resonant buffer layer has been investigated by the finite-element method in this paper. Important waveguide design parameters, such as the refractive index, thickness, interaction length, fabrication tolerance, and band-stop characteristics, have been analyzed in detail. Mode coupling within the polarizer and the losses due to coupling between the polarizer and the input and output waveguides are considered using the normal mode analysis. The loss behaviors of and modes are explained and the roles of the resonant buffer layer are interpreted. By using ultralow index layers, resonance, as well as its phase-matching conditions and excellent performance, has also been presented and discussed for this structure for the first time. Simulations show that high performance can be achieved in a wide range of the cladding thicknesses (ges 2 mum) and interaction length for both TE-pass and TM-pass polarizers. With optimized parameters under 3-mm length, it is possible to obtain a broadband TE-pass polarizer with an extinction ratio of more than 40 dB and insertion loss below 0.2 dB over 200 nm, and a TM-pass polarizer with an extinction ratio of more than 30 dB and insertion loss below 0.4 dB over 28 nm.     

A Low-Noise and Low-Power Frequency Synthesizer Using Offset Phase-Locked Loop in 0.13-$mu{rm m}$ CMOS

In this letter, a fractional-N frequency synthesizer based on an offset phase-locked loop (OPLL) architecture is presented. The proposed synthesizer achieves low-noise as the two low-pass filters that are inherent in the OPLL highly suppresses the quantization noise from the delta-sigma modulator. In addition, it consumes low power by employing charge-recycling technique in the sub-PLL. A prototype synthesizer implemented in 0.13 $mu{rm m}$ CMOS process achieves 9 dB of noise reduction compared to a conventional PLL while consuming 3.2 mW of power.      

Stochastic Modeling of the Transform-Domain $varepsilon {rm LMS}$ Algorithm

This paper presents a statistical analysis of the transform-domain least-mean-square (TDLMS) algorithm, resulting in a more accurate model than those discussed in the current open literature. The motivation to analyze such an algorithm comes from the fact that the TDLMS presents a higher convergence speed for correlated input signals, as compared with other adaptive algorithms possessing a similar computational complexity. Such a fact makes it a highly competitive alternative to some applications. Approximate analytical models for the first and second moments of the filter weight vector are obtained. The TDLMS algorithm has an orthonormal transformation stage, accomplishing a decomposition of the input signal into distinct frequency bands, in which the interband samples are practically uncorrelated. On the other hand, the intraband samples are correlated; the larger the number of bands, the higher their correlation. The model is then derived taking into account such a correlation, requiring that a high-order hyperelliptic integral be computed. In addition to the proposed model, an approximate procedure for computing high-order hyperelliptic integrals is presented. A regularization parameter is also considered in the model expressions, permitting to assess its impact on the adaptive algorithm behavior. An upper bound for the step-size control parameter is also obtained. Through simulation results, the accuracy of the proposed model is assessed.     

Fabrication of Self-Aligned Enhancement-Mode $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs With $ hbox{TaN/HfO}_{2}hbox{/AlN}$ Gate Stack

In this letter, we report the fabrication and characterization of self-aligned inversion-type enhancement-mode In_0.53Ga_0.47As metal-oxide-semiconductor field-effect transistors (MOSFETs). The In_0.53Ga_0.47As surface was passivated by atomic layer deposition of a 2.5-nm-thick AIN interfacial layer. In_0.53Ga_0.47As MOS capacitors showed an excellent frequency dispersion behavior. A maximum drive current of 18.5 muA/mum was obtained at a gate overdrive of 2 V for a MOSFET device with a gate length of 20 mum. An I_on/_off ratio of 104, a positive threshold voltage of 0.15 V, and a subthreshold slope of ~165 mV/dec were extracted from the transfer characteristics. The interface-trap density is estimated to be ~7-8 times 10¹² cm^-2 ldr eV^-1 from the subthreshold characteristics of the MOSFET.     

Time-Resolved Linewidth Enhancement Factors in Quantum Dot and Higher-Dimensional Semiconductor Amplifiers Operating at 1.55 $mu{hbox{m}}$

We report time-resolved measurements of the linewidth enhancement factors (-factors) , and , associated with the adiabatic carrier recovery, carrier heating, and two-photon absorption dynamical processes, respectively, in semiconductor optical amplifiers (SOAs) with different degrees of dimensionality-one InAs/InGaAsP/InP quantum dot (0-D), one InAs/InAlGaAs/InP quantum dash (1-D), and a matching InGaAsP/InGaAsP/InP quantum well (2-D)-all operating near 1.55- wavelengths. We find the lowest values in the QD SOA, 2-10, compared to 8-16 in the QW, and values of and that are also lower than in the QW. In the QD SOA, the -factors exhibit little wavelength dependence over the gain bandwidth, promising for wide-bandwidth all-optical applications. We also find significant differences in the -factors of lasers with the same structure, due to the differences between gain changes that are induced optically or through the electrical bias. For the lasers we find the QW structure instead has the lower -factor, having implications for directly modulated laser applications.     

High-Work-Function Ir/HfLaO ${rm p}$-MOSFETs Using Low-Temperature-Processed Shallow Junction

We report a high effective work function (Phi_m-eff) and a very low Vt Ir gate on HfLaO p-MOSFETs using novel self-aligned low-temperature shallow junctions. This gate-first process has shallow junctions of 9.6 or 20 nm that are formed by solid phase diffusion using SiO₂-covered Ga or Ni/Ga. At 1.2-nm effective oxide thickness, good Phi_m-eff of 5.3 eV, low V_t of +0.05 V, high mobility of 90 cm²/V-s at -0.3 MV/cm, and small 85degC negative bias-temperature instability (NBTI) of 20 mV (10 MV/cm for 1 h) are measured for Ir/HfLaO p-MOSFETs.     

High Density and Low Leakage Current in $ hbox{TiO}_{2}$ MIM Capacitors Processed at 300 $^{circ} hbox{C}$

We report Ir/TiO₂/TaN metal-insulator-metal capacitors processed at only 300degC, which show a capacitance density of 28 fF/mum² and a leakage current of 3 times 10^-8 (25degC) or 6 times 10^-7 (125degC) A/cm² at -1 V. This performance is due to the combined effects of 300degC nanocrystallized high-kappa TiO₂, a high conduction band offset, and high work-function upper electrode. These devices show potential for integration in future very-large-scale-integration technologies.