40Gbit／s高速并行12信道光接收模块的研制

研究并制作了12信道并行光接收模块,单信道传输速率大于等于3．318Gbit／s,12信道并行总传输速率为40Gbit／s。模块采用工作波长在850nm的高速PIN型光电探测器（PD）列阵作为光接收器件,PD列阵与接收电路芯片直接用Au丝压焊连接,输入光信号直接由12信道的光纤阵列耦合进入PD列阵中。对光接收模块进行眼...     

160-Gbit/s clock recovery using an electro-absorption modulator and 40-Gbit/s ETDM demultiplexer

A 10-GHz clock recovery from a 16×10-Gbit/s optical time-division-multiplexed (OTDM) data stream is experimentally demonstrated using an electro-absorption modulator and 40-Gbit/s electric time-division-multiplexed (ETDM) demultiplexer. The recovered clock signal exhibits excellent stability, with root square (RMS) jitter of 328 and 345 fs corresponding to back-to-back and transmission over 100 km, respectively.     

4-bit multiplexer/demultiplexer chip set for 40-Gbit/s optical communication systems

We have designed and fabricated a low-power 4:1 multiplexer (MUX), 1:4 demultiplexer (DEMUX) and full-clock-rate 1:4 DEMUX with a clock and data recovery (CDR) circuit using undoped-emitter InP-InGaAs HBTs. Our HBTs exhibit an f/sub T/ of approximately 150 GHz and an f/sub max/ of approximately 200 GHz at a collector current density of 50 kA/spl mu/m/sup 2/. In the circuit design, we utilize emitter-coupled logic and current-mode logic series gate flip-flops and optimized the collector current density of each transistor to achieve low-power operation at required high bit rates. Error-free operation at bit rates of up to 50 Gbit/s were confirmed for the 4:1 MUX and 1:4 DEMUX, which dissipates 2.3 and 2.5 W, respectively. In addition, the full-clock-rate 1:4 DEMUX with the CDR achieved 40-Gbit/s error-free operation.     

Toward High-Speed 40-Gbit/s Transponders

Today a 40-Gbit/s data rate is agreed by major optical telecommunication players as the next step in the network evolution, with an actual deployment foreseen in the 2007-2008 timeframe. R&D activities on technologies for 40-Gbit/s products are currently active but the path to 40-Gbit/s transponders is not yet fully settled. In this paper, we review the different component technologies currently considered for the actual development and the implementation of future 40-Gbit/s transponders. Dedicated paragraphs are devoted to electronic ICs and electrooptical devices, along with considerations on the technical solutions ensuring suitable interconnections or integration of the different components. Such advanced transponders should be compliant with the requirements of the different segments of the optical transport market. Solutions derived from choices made at lower data rates are projected for the shortest transmission paths, based on conventional nonreturn to zero modulation. In the peculiar case of long-haul transmission, signal distortion resulting from fiber propagation impairments calls for the generation of alternative modulation formats at the transmitter side and the potential need for electronic processing at the receiver side. This obviously has a clear impact on both the transponder design and the individual components features. Finally, recent advances in the field of innovative "all-optical" transponders implementing optical regeneration are also reported.     

40-Gbit/s 3-input all-optical priority encoder based on cross-gain modulation in two parallel semiconductor optical amplifiers

A 3-input all-optical priority encoder is designed.Proof-of-concept experiment is performed at 40-Gbit/s based on a cross-gain modulation (XGM) in two parallel semiconductor optical amplifiers (SOAs).O...     

40-Gbit/s SDH光纤通信系统前置放大器设计

基于0.35μm SiGe BiCMOS工艺,设计了共基极和共发共基两种输入结构的前置放大器.为获得更宽的电路带宽,共基极电路采用了电容峰化技术.电路仿真表明,采用这些技术使两种前置放大器的跨阻带宽都达到了28GHz以上,满足了40Gbit/s SDH光纤通信系统带宽要求.通过比较两种不同输入结构前置放大器的增益、带宽、电路稳定性以及噪声特性,提出了双极型晶体管实现高速前置放大器的设计方案.     

40-Gbit/s ETDM Channel Technologies for Optical Transport Network

We review recent progress and the future of 40-Gbit/s electrical time division multiplexed (ETDM) channel technologies for the optical transport network (OTN), where optical technologies, including high-speed ETDM channel transmission and wavelength division multiplexing (WDM), dramatically enhance network flexibility while reducing transport node cost as well as transmission cost. The 40 Gbit/s channel has recently been specified to be one of the optical channels in OTN. A new digital frame for the optical channels [optical channel transport unit (OTU)] was introduced for the network node interface of OTN in International Telecommunication Union-Telecommunication (ITU-T) standard. The specified data bit rates are 2.7 Gbit/s (OTU1), 10.7 Gbit/s (OTU2), and 43.0 Gbit/s (OTU3). These OTU frames have additional overhead bytes that support the network management overhead for OTN and out-of-band forward error correcting (FEC) codes. We discuss the feasibility and impact of the OTU3 frame in terrestrial networks. A newly developed 43-Gbit/s OTN line terminal prototype that confirms the feasibility of 43-Gbit/s ETDM channels and the OTU3 management capability is discussed. As a guide to the evolution of OTN, modulation formats for 43Gbit/s-based DWDM transmission are described for long distance application with the total capacity over one terabit per second.     

Optimum design of a 4-Gbit/s GaAs MESFET optical preamplifier

An analysis for determining the optimum MESFET gate width to optimize the sensitivity of a high-speed optical preamplifier is presented. A full MESFET model is employed including correlated gate and drain noise sources. The design of an optimum sensitivity monolithic shunt feedback amplifier, including stability requirements, is investigated. The results show that the optimum gate width for minimizing input equivalent noise is significantly larger than earlier simplfied predictions. A sensitivity improvement of 1.2 dB is demonstrated for a 4-Gbit/s MESFET optical amplifier, and results showing the dependence of optimum FET width on photodetector capacitance are described.     

40-Gbit/s TDM transmission technologies based on ultra-high-speedICs

This paper presents 40-Gbit/s time division multiplexing (TDM) transmission technologies based on 0.1-μm-gate-length InP high electron mobility transistor IC's and a scheme for upgrading toward a terabit-per-second capacity system. A 40-Gbit/s, 300-km, in-line transmission experiment and a dispersion-tolerant 40-Gbit/s duobinary transmission experiment are described as 40-Gbit/s single carrier system applications on dispersion-shifted fiber. An ultra-high-speed receiver configuration using a high-output-power photodiode is introduced to realize fully electrical receiver operation beyond 40 Gbit/s. The high-sensitivity operation of the optical receiver (-27.6 dBm@BER=10^-9) is demonstrated at a data bit rate of 50 Gbit/s for the first time using a unitraveling carrier photodiode. A dense wavelength division multiplexing (DWDM) system operating up to terabits per second can be easily realized on a zero-dispersion flattened transmission line using ultra-high speed TDM channels of 40 Gbit/s and beyond. An experiment demonstrates 1.04-Tbit/s DWDM transmission based on 40-Gbit/s TDM channels with high optical spectrum density (0.4 bit/s/Hz) without dispersion compensation     

An analog front-end chip set employing an electro-optical mixeddesign on SPICE for 5-Gb/s/ch parallel optical interconnection

A chip set composed of a laser-diode driver (LDD) and an optical receiver (RCV), which incorporates a full 2D (reshape, regenerate) function, has been developed by using silicon bipolar technology for a four-channel 5-Gb/s parallel optical transceiver. An electro-optical mixed design on SPICE of the LDD and the LD is accomplished by describing the rate equations of the LD as an electrical circuit. This design accommodates easy connectivity of the LDD chip to the LD in the optical transmitter module without the need for adjustment of the optical waveform. A pseudobalanced transimpedance amplifier (TIA) and feedforward automatic decision threshold control (ATC) in the RCV minimize the number of off-chip bypass capacitors, eliminate the need for any off-chip coupling capacitors, and keep crosstalk less than -50 dB and low cutoff frequency less than 80 kHz. A prototype parallel optical transmitter module and a prototype receiver module, based on the chip set, demonstrated asynchronous four-channel 5-Gb/s operation. The chip set has a throughput of 20 Gb/s with a power dissipation of 1.3 W at a 3.3-V supply     

Packaging technology for 40-Gb/s optical receiver module with anMU-connector interface

A compact 40-Gb/s optical receiver module with an MU-connector interface has been developed. Its packaging has three main technical features. (1) Coplanar waveguide (CPW) patterns of the waveguide photodiode (WG-PD) and of the preamplifier IC in the facing area of the flip-chip structure are optimized for impedance matching. (2) A film carrier is used to connect the preamplifier IC to an electrical coaxial connector for electrical signal output. (3) An MU-connector is used as the optical interface to reduce the module size. Optimum design enabled a module size of 14.0 mm wide, 40.4 mm long, and 9.65 mm high. Measurements showed a 3-dB down bandwidth of the optical/electrical response of at least 50 GHz and a clear open eye pattern for a 40-Gb/s nonreturn-to-zero (NRZ) signal input. This optical receiver module is suitable for large-capacity communication network systems     

Near hexagonal close-packed optical fiber array for parallel optical interconnection

In conventional optical fiber based two-dimensional (2-D) parallel optical interconnection (POI), optical fiber arrays are aligned to 2-D light sources and detectors using precisely fabricated hole-plate or stacked V-groove plates. All these structures have problems in making positioning components and assembly with high accuracy. For polymer optical fibers with large diameter, the whole dimension of the array will be too large if they are positioned using V-grooves or hole-plate. This paper proposes a 2-D near hexagonal close-packed (NHCP) optical fiber array for 2-D POI. NHCP array has a cross-sectional profile of near-hexagonal lattice and with fibers precisely positioned at each node of lattice. Compared with perfect HCP lattice, NHCP lattice is slightly stretched in one dimension and still have all fibers with nonuniform diameter packed tightly with high packing fraction. The position of fibers in NHCP array is very important when aligned to 2-D light sources and detectors. This paper deduce the analytically expression for the probability distribution of fiber position which is related to variance of fiber diameter and structure parameters of NHCP array, and verified it by computer simulation. Experiment samples of NHCP array have been made showing that NHCP array is easy to be fabricated.     

Upgrading WDM Submarine Systems to 40-Gbit/s Channel Bitrate

The introduction of wavelength division multiplexing (WDM) has triggered a tremendous capacity growth in submarine systems, both by the increase of the number of WDM channels and by the increase of the channel bitrate. Starting from 2.5 Gbit/s in the mid-1990s, the bitrate was upgraded to 10 Gbit/s by the end of the century in commercial products. The next generation of submarine systems will likely be based on a 40-Gbit/s bitrate. However, transmissions at a 40-Gbit/s rate are more challenging than transmissions at 10 Gbit/s. The goal of this paper is to provide an overview of the technologies which could be required or used in next-generation submarine systems. In the first part of this paper, an overview of the history of submarine links is provided. Then the technologies used in current N /spl times/ 10 Gbit/s systems are described. Eventually, the challenges to overcome are discussed, whether they concern the type of fiber, the type of optical amplifier, or the nature of the modulation format.     

16-channel parallel optical interconnect demonstration with an InGaAs/InP MQW modulator array

A 4*4 planar array of MQW surface modulators driven by standard high-speed CMOS has been demonstrated in an experimental parallel-interconnect system. Transition times were fast enough for 100 Mbit/s operation and the potential exists to increase array dimensions to include hundreds of devices and transmission rates to many Gbit/s.<>     

Technology development of a high-density 32-channel 16-Gb/s opticaldata link for optical interconnection applications for theoptoelectronic technology consortium (OETC)

A parallel, 32-channel, high density (140 μm pitch), 500 Mb/s NRZ, point-to-point, optical data link has been fabricated using existing GaAs IC, silicon optical bench (SiOB), and multichip module (MCM-D) technologies. The main components of the transmitter and the receiver modules are a GaAs-based vertical cavity surface emitting laser (VCSEL) array at 850 mn with its IC driver array chip and an integrated metal-semiconductor-metal (MSM) receiver (photodetector and signal processing circuits) array at 850 nm. The package module uses a modified 164 I/O JEDEC premolded plastic quad flat pack (PQFP) in combination with a polymer film integrated circuit (POLYFIC) chip carrier. The electrical input and output are 500 Mb/s NRZ binary signals. The optical I/O in both modules consists of a directly-connectorized (nonpigtail) fiber array block that plugs into the 32×1 optical fiber ribbon directly on one side and accepts 32 optical signals from the SEL array or delivers them to the MSM receiver array via a gold-coated 45° polished fiber array mirror. The MACII-32 ribbon cable is an enhanced version of the standard MACII connector ribbon cable. This paper characterizes key components of the optical data link, describes its package design, and discusses preliminary component and optical data link test results     

Compact 10-Gbit/s optical transmitter and receiver circuit packs

Compact wideband 10-Gbit/s optical transmitter and receiver circuit packs are realized using high speed analog and digital GaAs IC's as well as a highly thermally conductive board and appropriately designed small function block modules that employ multichip packaging and resonant cavity mode damping. To achieve a compact receiver, the receiver circuit employs a clamp and peak-detector IC in the high speed analog equalizer amplifier to obtain a constant output direct current level for any mark density imbalance in the number of ones and zeros in the signal and a variable phase-shifter IC in the timing circuit. Realized circuit pack size is 200×280×15.24 mm and the power consumption of each pack is about 25 W     

Differential precoder IC modules for 20-and 40-Gbit/s opticalduobinary transmission systems

This paper reports on 20- and 40-Gbit/s differential precoder modules for optical duobinary transmission systems. These precoder modules overcome the speed limit of a conventional precoder by parallel processing. The proposed precoders handle two or four parallel signals before multiplexing with data rates of one-half or one-quarter the transmission bit rate, and the final preceded signal is obtained by multiplexing the precoder output bit by bit, production-level 0.2-μm gate-length GaAs MESFET's were used to fabricate the precoders. The precoders are mounted in an RF package. They successfully performed 20- and 40-Gbit/s precoding for the first time, and the 20-Gbit/s precoder achieved a maximum precoding rate of 22 Gbit/s, which is 76% faster than that of the conventional circuit using the same MESFETs. The 40-Gbit/s precoder performs 40-Gbit/s precoding when combined with a 40-Gbit/s multiplexer unit. Twenty-Gbit/s optical duobinary transmitter and receiver circuits using the 20-Gbit/s precoder module successfully generate fully encoded optical duobinary signal at this rate for the first time. These circuits show a receiver sensitivity of -28.6 dBm for a bit error rate of 1×10^-9     

New nodal design for high throughput data vortex optical interconnection network

This paper proposes a new three input nodal structure within the data vortex packet switched interconnection network. With additional optical switches, the modified architecture allows for two input packets in addition to a buffered packet to be processed simultaneously within a routing node. A much higher degree of parallel processing is allowed in comparison to previously proposed enhanced buffer node with two input processing or the original network node with single input processing. Unlike the previous contention prevention mechanism, the new network operates by introducing the packet blocking within the node if no exit path is available. This eliminates the traffic control signaling and the strict timing alignment associated with the routing paths which simplifies the overall network implementation. This study shows that both data throughput and the latency performance are improved significantly within the new network. The study compares the three input node with the two input node as well as the original single input data vortex node. Due to additional switch count and nodal cost, networks that support the same I/O ports and of the same cost are compared for a fair comparison. The limitation introduced by the blocking rate is also addressed. The study has shown that under reasonable traffic and network condition, the blocking rate can be kept very low without introducing complex controls and management for dropped packets. As previous architectures require operation under saturation point, the proposed architecture should also operate at reasonable level of network redundancy to avoid excessive packet drop. This study provides guidance and criteria on the proposed three input network design and operation for feasible applications. The proposed network provides an attractive alternative to the previous architectures for higher throughput and lower latency performance.     

40-Gbit/s OEIC on GaAs substrate through metamorphic buffer technology

An optoelectronic integrated circuit operating in the 1.55-/spl mu/m wavelength range was realized on GaAs substrate through metamorphic technology. High indium content layers, metamorphically grown on a GaAs substrate, were used to fabricate the optoelectronic integrated circuits (OEICs) with -3 dB bandwidth of 40 GHz and 210 V/W of calculated responsivity. The analog OEIC photoreceiver consists of a 12-/spl mu/m, top-illuminated p-i-n photodiode, and a traveling wave amplifier (TWA). This receiver shows 6 GHz wider bandwidth than a hybrid photoreceiver, which was built using comparable, but stand-alone metamorphic p-i-n diode and TWA. With the addition of a buffer amplifier, the OEIC shows 7 dB more gain than the hybrid counterpart. To our knowledge, this is the first 40 Gbit/s OEIC achieved on a GaAs substrate operating at 1.55 /spl mu/m.