A novel low-power,low-offset,and high-speed CMOS dynamic latched comparator

A novel dynamic latched comparator with offset voltage compensation is presented. The proposed comparator uses one phase clock signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch stage. As it provides a larger voltage gain up to 22 V/V to the regenerative latch, the input-referred offset voltage of the latch is reduced and metastability is improved. The proposed comparator is designed using 90 nm PTM technology and 1 V power supply voltage. It demonstrates up to 24.6% less offset voltage and 30.0% less sensitivity of delay to decreasing input voltage difference (17 ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption. In addition, with a digitally controlled capacitive offset calibration technique, the offset voltage of the proposed comparator is further reduced from 6.03 to 1.10 mV at 1-sigma at the operating clock frequency of 3 GHz, and it consumes 54 μW/GHz after calibration.     

A 60 mW per Lane, 4$,times,$23-Gb/s 2$ ^7 -$1 PRBS Generator

An ultra-low-power, 2$ ^7-$1 PRBS generator with four, appropriately delayed, parallel output streams was designed. It was fabricated in a 150-GHz$f_T$SiGe BiCMOS technology and measured to work up to 23 Gb/s. The four-channel PRBS generator consumes 235 mW from 2.5 V, which results in only 60 mW per output lane. The circuit is based on a 2.5-mW BiCMOS CML latch topology, which, to the best of our knowledge, represents the lowest power for a latch operating above 10 Gb/s. A power consumption and speed comparison of series and parallel PRBS generation techniques is presented. Low-power BiCMOS CML latch topologies are analyzed using the OCTC method.     

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

This paper presents a new 0.5 V high-speed dynamic latch comparator with built-in foreground offset cancellation capability and rail-to-rail input range. Traditional latch comparators lose their speed performance in low voltage condition, especially in sub-1V applications. The proposed latch comparator utilizes a speed-up technique based on a novel boosting method to mitigate the low voltage imperfections on circuit operation. Employing a new offset cancellation technique based on the same boosting capacitors is another key idea. This enhances the accuracy of the ultra low-voltage latch comparators and relaxes the need for preamplifier stage, which is conventionally used in the low offset latch comparator. The performed Monte Carlo simulations over corners in 0.18 μm standard CMOS process show the improvement of input referred offset voltage with a standard deviation of 29.9 mV/299 μV before and after offset cancellation, respectively. The designed comparator dissipates 34 μW power from 0.5 V voltage supply while operating in 200 MHz clock frequency and detects 1 mV input difference.     

栅极触发PDSOI CMOS闩锁效应研究

测试了不同静态栅极触发电压(输入电压)下诱发CMOS闩锁效应需要的电源电压和输出电压(即将闩锁时的输出电压),发现静态栅极触发CMOS闩锁效应存在触发电流限制和维持电压限制两种闩锁触发限制模式,并且此栅极触发电压.输出电压曲线是动态栅极触发CMOS闩锁效应敏感区域与非敏感区域的分界线.通过改变输出端负载电容,测试出了不同电源电压下CMOS闩锁效应需要的栅极触发电压临界下降沿,并拟合出了0 pF负载电容时的临界下降沿,最终得出了PDSOI CMOS电路存在的CMOS闩锁效应很难通过电学方法测试出来的结论.     

Design of ultrahigh-speed low-voltage CMOS CML buffers and latches

A comprehensive study of ultrahigh-speed current-mode logic (CML) buffers along with the design of novel regenerative CML latches will be illustrated. First, a new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, two new high-speed regenerative latch circuits capable of operating at ultrahigh-speed data rates will be introduced. Experimental results show a higher performance for the new latch architectures compared to the conventional CML latch circuit at ultrahigh-frequencies. It is also shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.     

Highly Robust AHHVSCR‐Based ESD Protection Circuit

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR‐based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch‐up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit — (i) an AHHVSCR‐based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR‐based ESD protection circuit, and (iii) a standard HHVSCR‐based ESD protection circuit. A circuit having the proposed new structure is fabricated using 0.18 μm Bipolar‐CMOS–DMOS technology. The fabricated circuit is also evaluated using Transmission‐Line Pulse measurements to confirm its electrical characteristics, and human‐body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.     

An 8 bit 1 MS/s SAR ADC with 7.72-ENOB

This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18 μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5 μ W with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.     

A new true-single-phase-clocking BiCMOS dynamic pipelined logicfamily for high-speed, low-voltage pipelined system applications

New true-single-phase-clocking (TSPC) BiCMOS/BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1 μm BiCMOS technology. Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clock-high-evaluate-BiCMOS dynamic latch logic circuit and clock-low-evaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked MOS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively. Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1 μm BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, low-voltage dynamic pipelined system applications     

A 1?mW power-efficient high frequency CML 2:1 divider

In this study, a low power high operating frequency current mode logic (CML) 2:1 divider is presented. Because the latching transistor pair is biased in low current mode, the proposed divider is power-saving. In this divider, each latch has only one clock transistor, which means that the capacitive load to the former stages is reduced. This makes the buffer of the voltage controlled oscillator (VCO) or VCO be easily designed in phase locked loops. Besides, an active inductor is used in this circuit to resonate with parasitic capacitances and thus endows this topology a high-speed capability. The measurement results indicate that the proposed divider achieves an operation band from 10 to 15?GHz with only 1mW power dissipation.     

Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design

In this paper, we proposed a reliable ultra-low-voltage low-power latch design based on the probabilistic-based Markov random field (MRF) theory ,  and  to greatly improve the ability of noise-tolerance. Through MRF mapping decomposition, we map the previous state and the current state compatible logic function of the latch into the MRF network separately. In this way, we can overcome the challenge of applying Markov random field theory to sequential noise-tolerant circuits. In order to further lower the hardware cost and circuit complexity of the chip, we apply the absorption law and H-tree logic combination techniques [4] to simplify the circuit complexity of the MRF noise-tolerant latch circuit. To preserve the noise tolerant capability of MRF latch, we utilize the cross-coupled latching mechanism in the output of MRF latch. Finally, we apply the proposed MRF latch design in a 16-bit carry-lookahead adder circuit. In TSMC 90 nm CMOS process, our proposed circuit can operate reliably under a lower supply voltage of 0.55 V with superior noise tolerance and consumes only 31 μW power, which is 59.2% lower as compared with the conventional CMOS latch design.     

Current-Mode Logic in Organic Semiconductor Based on Source-Gated Transistors

Due to the low mobility and the abundance of trap states in organic field-effect transistors (OFETs), the operation of conventional logic circuits-based OFETs needs a large voltage swing, and suffers large switching noise and low speed. In this letter, current-mode logic (CML) circuits composed of organic source-gated transistors (OSGTs) are proposed for high-speed signaling based on existing material and process technologies. Mixed-mode simulations show that CML circuits using simple resistive loads can still be operated much faster than an ideal conventional inverter with perfect active loads and OFETs free of traps. With the same supply voltage and device parameters, CML circuits can work with a wide range of signal swings. The superior analog performance of OSGTs is also shown to fit well with the design requirements for CML circuits in terms of low power supply, high output impedance, and stability.      

High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design

In a modern high density VLSI design, with higher operating frequency and technology scaling, small critical charge in circuit nodes significantly increases susceptibility to radiation induced transient faults. In this paper, we propose a high efficiency hardened latch using the undesired delay of Schmitt trigger circuit and a special feedback loop to a comparator to build a low overhead time redundancy scheme. The proposed structure masks internal node transient faults also improves the recovery of the output node by transferring the faulty output in two different paths to the comparison circuit’s inputs. Experimental results, simulated in 45 nm CMOS technology, show an acceptable increase in the critical charge compared with the previous hardened latches, with a fair increase in power, delay and area. Monte Carlo simulations have also confirmed the proposed latch resistance to the process, voltage and temperature variations.     

Low‐Power,All Digital Phase‐Locked Loop with a Wide‐Range,High Resolution TDC

In this paper, we propose a low‐power all‐digital phase‐ locked loop (ADPLL) with a wide input range and a high resolution time‐to‐digital converter (TDC). The resolution of the proposed TDC is improved by using a phase‐interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 mm² using 0.13 µm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is ‐120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.     

High performance energy efficient radiation hardened latch for low voltage applications

Energy efficiency is considered to be the most critical design parameter for IoT and other ultra low power applications. However, energy efficient circuits show a lesser immunity against soft error, because of the smaller device node capacitances in nanoscale technologies and near-threshold voltage operation. Due to these reasons, the tolerance of the sequential circuits to SEUs is an important consideration in nanoscale near threshold CMOS design. This paper presents an energy efficient SEU tolerant latch. The proposed latch improves the SEU tolerance by using a clocked Muller- C and memory elements based restorer circuit. The parasitic extracted simulations using STMicroelectronics 65 nm CMOS technology show that by employing the proposed latch, an average improvement of ∼40% in energy delay product (EDP), is obtained over the recently reported latch. Moreover, the proposed latch is also validated in a TCAD calibrated PTM 32 nm framework and PTM 22 nm CMOS technology nodes. In 32 nm and 22 nm technologies, the proposed latch improves the EDP ∼12% and 59% over existing latches respectively.     

Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator

The demanding need of ultra-high speed, area efficient and power optimized analog-to-digital converter is forcing towards the exploration and usage of the dynamic regenerative comparator to minimize the power, area and maximize the speed. In this paper, detailed analysis of the delay for the various dynamic latch based comparators is presented and analytical expressions are derived. With the help of analytical expressions, the designer can obtain insight view of the different parameters, which are the contributors of the delay in the dynamic comparator. Based on the findings, various tradeoffs can be explored. Based on the literature and presented analysis, a new dynamic latch based comparator is proposed. The basic double tail dynamic latch based comparator and shared charge logic are modified for low-power and high-speed with the reduced power supply in the proposed comparator. With the modified structure of double tail latch comparator and adding the shared charge logic, the regeneration delay is reduced, at the same time, power consumption is also reduced. Simulation results in 90 nm CMOS technology confirm the claimed reductions. The simulation is carried out using 90 nm technology with a supply voltage of 1 V, at 1 GHz of frequency resulting into the delay of 50.9 ps while consuming 31.80 μW of power.     

低电压Charge-Recovery逻辑电路的设计

提出了一种新的适用于低电压工作的 sem i- adiabatic逻辑电路—— Dual- Swing Charge- Recovery L ogic(DSCRL) .该电路由 CMOS- latch- type电路及负载驱动电路构成 ,对负载的驱动为 full- adiabatic过程 .DSCRL 的电源为六相双峰值脉冲电源 ,低摆幅脉冲用于驱动负载 ,高摆幅脉冲用于驱动 CMOS- latch- type电路 .降低负载上摆幅时驱动负载的 NMOS管的栅压可以保持不变 ,有效地解决了传统的 adiabatic电路在低电压工作时 charge- re-covery效率降低的问题 .文中比较了 DSCRL 电路与部分文献中的 semi- adiabatic电路的功耗 ,DSCRL 在低电压工作方面     

基于0.18μm SiGe BiCMOS工艺的高速比较器分析与设计

基于预放大正反馈锁存比较理论,给出了一种8bit 8Gs/s高速比较器的设计.该比较器采用预放大器结构以提高分辨率、加快比较过程,采用主从锁存器降低亚稳态发生概率,采用输出缓冲器改善输出波形、提供测试接口;在HHNEC 0.18μm SiGe BiCMOS工艺下,采用Cadence Spectre进行仿真,结果显示,该比较器精度为4mV,输出摆幅±300mV,锁存时间37ps,过驱动恢复时间22ps,功耗约57mW,表现出良好的性能.     

A 455 nW 220 fJ/conversion-step 12 bits 2 kS/s SAR ADC for portable biopotential acquisition systems

An ultra-low power 12 bits 2 kS/s successive approximation register analog-to-digital converter(ADC) is presented.For power optimization,the voltage supply of the digital part is lowered,and the offset voltage of the latch is self-calibrated.Targeted for better linearity and lower noise,an improved digital-to-analog converter capacitor array layout strategy is presented,and a low kick-back noise latch is proposed.The chip was fabricated by using 0.18μm 1P6M CMOS technology.The ADC achieves 61.8 dB SNDR and dissipates 455 nW only,resulting in a figure of merit of 220 fJ/conversion-step.The ADC core occupies an active area of only 674×639μm~2.     

Low-voltage, high-speed CMOS analog latched voltage comparator using the “flipped voltage follower” as input stage

The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode signal detector, followed by a regenerative latch and a Set-Reset (S-R) latch. It is suitable for successive-approximation type’s analog-to-digital converters (ADC), but can also be adapted for use in flash-type ADCs. The circuit was fabricated using 0.18 μm CMOS technology, and its measured performance shows 12-bit resolution at 20 MHz comparison rate and 1 V single supply voltage, with a total power consumption of 63.5 μW.     

应用于60GHz的CMOS频率生成器

本文提出一种用于60GHz的频率生成器,其由电流模二分频器和倍频器组成. 得益于电流模结构和差分对的非线性,该频率生成器具有很宽的工作频率范围以补偿工艺,电压和温度的偏差。频率生成器用90nm 工艺投片验证。芯片的面积为0.64X0.65mm^2,。测试结果表明在输入0dBm功率的时候,该频率生成器可以工作在15GHz-25GHz。整个芯片工作电压是1.2V,消耗12.1mW功耗。