Analysis of Dataflow Programs with Interval-limited Data-rates

In this paper, we consider the problem of analyzing dataflow programs with the property that actor production and consumption rates are not constant and fixed, but limited by intervals. Such interval ranges may result from uncertainty in the specification of an actor or as a design freedom of the model. Major questions such as consistencyand buffer memory requirementsfor single-processor scheduleswill be analyzed here for such specifications for the first time. Also, metamodeling formulations of interval limited dataflow are discussed, with special emphasis on the application to cyclo-static dataflow modeling. Jürgen Teich received his masters degree (Dipl.-Ing.) in 1989 from the University of Kaiserslautern (with honours). From 1989 to 1993, he was PhD student at the University of Saarland, Saarbrücken, Germany from where he received his PhD degree (summa cum laude). His PhD thesis entitled ‘A Compiler for Application-Specific Processor Arrays‘summarizes his work on techniques for mapping computation intensive algorithms onto dedicated VLSI processor arrays. In 1994, Dr. Teich joined the DSP design group of Prof. E. A. Lee and D.G. Messerschmitt in the Department of Electrical Engineering and Computer Sciences (EECS) at UC Berkeley where he was working in the Ptolemy project (PostDoc). From 1995 to 1998, he held a position at Institute of Computer Engineering and Communications Networks Laboratory (TIK) at ETH Zürich, Switzerland, finishing his Habilitation entitled ‘Synthesis and Optimization of Digital Hardware Software Systems’ in 1996. From 1998 to 2002, he was full professor in the Electrical Engineering and Information Technology department of the University of Paderborn, holding a chair in Computer Engineering. Since 2003, he is appointed full professor in the Computer Science Institute of the Friedrich-Alexander University Erlangen-Nuremberg holding a chair in Hardware-Software-Co-Design. Dr. Teich has been a member of multiple program committees of well-known conferences and workshops. He is member of the IEEE and author of a textbook on Co-Design edited by Springer in 1997.His research interests are massive parallelism, embedded systems, Co-Design, and computer architecture. Since 2004, Prof. Teich is also an elected reviewer for the German Science Foundation (DFG) for the area of Computer Architecture and Embedded Systems. Prof. Teich is involved in many interdisciplinary national basic research projects as well as industrial projects. He is supervising 19 PhD students currently. Shuvra S. Bhattacharyyais an associate professor in the Department of Electrical and Computer Engineering and the Institute for Advanced Computer Studies (UMIACS) at the University of Maryland, College Park. He is also an affiliate associate professor in the Department of Computer Science. Dr. Bhattacharyya is coauthor or coeditor of four books and the author or coauthor of more than 100 refereed technical articles. His research interests include VLSI signal processing, embedded software, and hardware/software co-design. He received the B.S. degree from the University of Wisconsin at Madison, and the Ph.D. degree from the University of California at Berkeley. Dr. Bhattacharyya has held industrial positions as a Researcher at the Hitachi America Semiconductor Research Laboratory (San Jose, California), and as a Compiler Developer at Kuck & Associates (Champaign, Illinois).     

Characteristic Investigation of New Pathological Elements

A characteristic investigation of the new pathological elements (i.e voltage mirror and current mirror) has been presented. Many nullor-mirror equivalences are explored. The circuit cascadability is discussed with nullor and mirror concepts. Also, the conventional inverse network transformation has been extended for applying to the circuits with current mirror output. To demonstrate the use of presented properties, practical examples have been given. The derived circuits have been verified with HSPICE simulation and the simulation results confirm with our theoretical prediction.Hung-Yu Wang was born in Kaohsiung, Taiwan, Republic of China, on January 4, 1969. He received the Ph.D. degree in optical sciences from National Central University, Chung-Li, Taiwan in 2002.Since 1993 he has worked on promoting the prototyping IC implementation of academic researches, and propelling the collaboration of the academia and industries in Chip Implementation Center (CIC), National Science Council of the Republic of China. In 2003 he became a researcher and the deputy director in Division of Chip Implementation Service of CIC. He is currently working on South Region Office of National Chip Implementation Center, National Applied Research Laboratories as a researcher and the department manager. His research interests are in current-mode circuits design, analog IC design and analog IP design.Ching-Ting Lee was born in Taoyuan, Taiwan, R.O.C., on November 1, 1949. He received his B.S. and M.S. in Electrical Engineering Department of the National Cheng-Kung University, Taiwan, in 1972 and 1974, respectively. He received Ph.D. degree in Electrical Engineering Department from the Carnegie-Mellon University, Pittsburgh, PA, in 1982.He worked on Chung Shan Institute of Science and Technology, before he joined the Institute of Optical Sciences, National Central University, Chung-Li, Taiwan, as a Professor in 1990. He works on National Cheng-Kung University as the dean of Electrical Engineering and Computer Science and the professor or the Institute of Microelectronics, Department of Electrical Engineering in 2003. His current research interests include theory, design, and application of guided-wave structures and devices for integrated optics and waveguide lasers. His research activities have also involved in the research concerning semiconductor lasers, photodetectors and high-speed electronic devices, and their associated integration for electrooptical integrated circuits. He received the outstanding Research Professor Fellowship from the National Science Council (NSC), R.O.C. in 2000 and 2002. He also received the Optical Engineering Medal from Optical Engineering Society and Distinguish Electrical Engineering professor award from Chinese Institute of Electrical Engineering Society in 2003.Chun-Yueh Huang was born in Taichung, Taiwan, Republic of China, on March 24, 1967. He received the B.S. degree in industrial education from National Chang Hwa Normal University, Chang Hwa, Taiwan in 1991, M.S. and Ph.D. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan in 1993 and 1997, respectively. Since 1999 he has been with the Kan Shan University of Technology, where he is currently Associate Professor and Chairman of Department of Electronic Engineering. His biography is included in the 7th Edition (2003–2004) of Who’s Who in Science and Engineering.His current researches include current-mode circuits design, VLSI design, analog IC design and analog IP design.     

CMOS image sensors for sensor networks

We report on two generations of CMOS image sensors with digital output fabricated in a 0.6 μm CMOS process. The imagers embed an ALOHA MAC interface for unfettered self-timed pixel read-out targeted to energy-aware sensor network applications. Collision on the output is monitored using contention detector circuits. The image sensors present very high dynamic range and ultra-low power operation. This characteristics allow the sensor to operate in different lighting conditions and for years on the sensor network node power budget. Eugenio Culurciello (S’97–M’99) received the Ph.D. degree in Electrical and Computer Engineering in 2004 from Johns Hopkins University, Baltimore, MD. In July 2004 he joined the department of Electrical Engineering at Yale University, where he is currently an assistant professor. He founded and instrumented the E-Lab laboratory in 2004. His research interest is in analog and mixed-mode integrated circuits for biomedical applications, sensors and networks, biological sensors, Silicon on Insulator design and bio-inspired systems. Andreas G. Andreou received his Ph.D. in electrical engineering and computer science in 1986 from Johns Hopkins University. Between 1986 and 1989 he held post-doctoral fellow and associate research scientist positions in the Electrical and Computer engineering department while also a member of the professional staff at the Johns Hopkins Applied Physics Laboratory. Andreou became an assistant professor of Electrical and Computer engineering in 1989, associate professor in 1993 and professor in 1996. He is also a professor of Computer Science and of the Whitaker Biomedical Engineering Institute and director of the Institute’s Fabrication and Lithography Facility in Clark Hall. He is the co-founder of the Johns Hopkins University Center for Language and Speech Processing. Between 2001 and 2003 he was the founding director of the ABET accredited undergraduate Computer Engineering program. In 1996 and 1997 he was a visiting professor of the computation and neural systems program at the California Institute of Technology. In 1989 and 1991 he was awarded the R.W. Hart Prize for his work on mixed analog/digital integrated circuits for space applications. He is the recipient of the 1995 and 1997 Myril B. Reed Best Paper Award and the 2000 IEEE Circuits and Systems Society, Darlington Best Paper Award. During the summer of 2001 he was a visiting professor in the department of systems engineering and machine intelligence at Tohoku University. In 2006, Prof. Andreou was elected as an IEEE Fellow and a distinguished lecturer of the IEEE EDS society. Andreou’s research interests include sensors, micropower electronics, heterogeneous microsystems, and information processing in biological systems. He is a co-editor of the IEEE Press book: Low-Voltage/Low-Power Integrated Circuits and Systems, 1998 (translated in Japanese) and the Kluwer Academic Publishers book: Adaptive Resonance Theory Microchips, 1998. He is an associate editor of IEEE Transactions on Circuits and Systems I.     

A New Differential CMOS Current-Mode Preamplifier for GBps Data Communications

This paper presents a new low-voltage fully differential CMOS current-mode preamplifier for GBps data communications. The number of transistors between the power and ground rails is only two so that the minimum supply voltage is one threshold voltage plus one pinch-off voltage. The preamplifier is a balanced two-stage configuration such that the effect of bias-dependent mismatches is minimized. A new inductive series-peaking technique is introduced to increase the bandwidth by utilizing the resonance characteristics of LC networks. In addition, a new negative differential current feedback technique is proposed to boost the bandwidth and to reduce the value of peaking inductors. The preamplifier has been implemented in TSMC 0.18 μm, 1.8 V, 6-metal mixed-mode CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. For an optical front-end with a 0.3 pF photodiode capacitance, simulation results demonstrate that the preamplifier has bandwidth of 3.5 GHz and provides a transimpedance gain of 66 dBΩ. The total chip area is approximately 1 mm² and the DC power consumption is about 85 mW. Bendong Sun received the B.Eng. degree in electrical engineering from Shanghai Jiaotong University, Shanghai, China, in1992, and the MASc degree in electrical and computer engineering from Ryerson University, Toronto, Ontario, Canada, in 2003. He is currently working towards the Ph.D. degree in electrical and computer engineering at University of Waterloo, Waterloo, Ontario, Canada. During 1992 through 1998 he was a Design Engineer at China Electronics Engineering Design Institute, Beijing, China. From 1998 to 2000 he worked for Bently Nevada Corporation, a GE Power Systems business, as a System Engineer. Since 2001, he has been a Research Assistant with the System-on-Chip Laboratory at Ryerson University. His research interests include design of analog and mixed-signal integrated circuits for high-speed data communications. Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the MASc degree in chemical engineering and PhD degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively. During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Canada. During 1989–1994, he worked for Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer. Since July 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book “Computer Methods for Analysis of Mixed-Mode Switching Circuits” (Kluwer Academic Publishers, 2004, with Ajoy Opal). Dr. Yuan received an “Excellence of Teaching" award from Changzhou Institute of Technology in 1988, a post-graduate scholarship from Natural Science and Engineering Research Council (NSERC) of Canada during 1997–1998. He is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada. Ajoy Opal (S'86-M'88) received the B. Tech degree from Indian Institute of Technology, New Delhi, India in 1981, and the MASc and PhD degrees from University of Waterloo, Waterloo, Ontario, Canada in 1984 and 1987, respectively. During 1989–92 he worked for Bell-Northern Research in the area of analog circuit simulation. He joined the Department of Electrical and Computer Engineering, University of Waterloo in 1992 and currently a Full Professor. Dr. Opal works in the area of simulation of analog and mixed digital-analog circuits, such as, switched capacitor, switched current, oversampled sigma-delta modulators. Other interests include circuit theory and filter design.     

Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages

A CMOS OTA-C low-pass notch filter for EEG application is described. The pass-band covers four bands of brain wave and provides more than 65 dB attenuation for the 50 Hz power line interference. The OTA works in the weak inversion region and a low transconductance of 3 nA/V is achieved. The low transconductance enables using small capacitors in the OTA-C filter so that the filter is suitable for the multi-channel EEG integrated circuits. The measured results show the good performance of the filter for filtering the noise in acquired EEG signals. Xinbo Qian received the B.Sc. degree from Beijing Institute of Technology, P.R. China, in 1991 and M.Sc. degree from Institute of Physics, Chinese Academy of Sciences, in 1996. From 1996 to 1999, she was a research engineer in the Institute of Acoustics, Chinese Academy of Sciences, worked on the sonar signal receiving and processing systems. Since 1999, she has been pursuing the Ph.D. degree in Electrical and Computer Engineering department, National University of Singapore, with research direction on on-chip readout circuits for microbolometer focal plane arrays. Now she is employed by Department of Mechanical Engineering and Division of Bioengineering, National University of Singapore as a research fellow. Her research interest is low-noise integrated circuits design and bio-medical sensor electronics, including electroencephalography IC, magnetocardiography IC, low-noise amplifier, filter and data converters etc. Yong Ping Xu graduated from Nanjing University, P.R. China in 1977. He received his Ph.D. from University of New South Wales (UNSW) Australia, in 1994. From 1978 to 1987, he was with Qingdao Semiconductor Research Institute, P.R. China, initially as an IC design engineer, and later the deputy R&D manager and the Director. From 1989 to 1992, he was working on silicon diode based infrared detectors towards his Ph.D. at School of Electrical Engineering, UNSW Australia. From 1993 to 1995, he worked on an industry collaboration project with GEC Marconi, Sydney, Australia, at the same university, involved in design of sigma-delta ADCs. He was a lecturer at University of South Australia, Adelaide, Australia from 1996 to 1998. He has been with the Department of Electrical and Computer Engineering, National University of Singapore since June 1998 and is now an Associate Professor. His general research interests are in the areas of mixed-signal and RF integrated circuits, and integrated MEMS and sensing systems. His current focuses are high-speed wideband ADC, UWB front-end circuits and low-power low-voltage integrated circuits for biomedical applications. He is a Senior Member of IEEE. Xiaoping Li received his Ph.D. degree from Department of Mechanical and Manufacturing Engineering, University of New South Wales, Australia in 1991, and joined the National University of Singapore in 1992, where he is currently an Associate Professor with the Department of Mechanical Engineering and Division of Bioengineering. He was a visiting professor of Tokyo Institute of Technology, Japan in 2000, and visiting professor of Georgia Institute of Technology, USA in 2001. He is a member of American Society of Mechanical Engineers (ASME), a senior member of Society of Manufacturing Engineering (SME) and a senior member of North American Manufacturing Research Institute/SME, and is currently the Chairman of SME Singapore Chapter. His current research interests include neurosensors and nanomachining. He is a guest editor of International Journal of Computer Applications in Technology, USA. He is a regular reviewer of the ASME Journal of Manufacturing Engineering, USA, Transactions of NAMRI/SME, USA, Journal of materials processing technology, UK, International Journal of Machine Tools and Manufacture, UK, and IMechE Journal of Engineering Manufacture, UK.     

New Single-Resistance-Controlled Oscillator Configurations Using Unity-Gain Cells

Unity-gain voltage followers and unity-gain current followers have attracted attention in the recent literature in the context of analog signal processing as well as signal generation because of the advantages of wider bandwidth and low power consumption of these active elements as compared to other more complex building blocks. Motivated by these advantages, followers have been used as alternatives to other more complex building blocks in the realisation of filters, oscillators and more recently, in impedance converters. Although some configurations for realizing sinusoidal oscillators using unity-gain voltage/current followers have been described in the earlier literature, only one of them is a second-order single-resistance-controlled oscillator but requires as many as eight followers. This paper derives, through a state-variable synthesis approach, a number of new follower-based single-resistance-controlled oscillators requiring a much smaller number (only two to four) of followers. The new circuits are shown to possess a number of other interesting features. The workability of the new structures has been confirmed by SPICE simulation results using CMOS-based followers. S.S. Gupta was born on July 2, 1962 at Kalinjer (Banda), UP, India. He obtained B.E. in 1982 (from Government Engineering College, Rewa, India) and M.E. (Honors) in 1988 (from Motilal Nehru National Institute of Technology, Allahabad, India)- both in Electrical Engineering. He worked as a Lecturer in Electrical Engineering Department of Motilal Nehru National Institute of Technology, Allahabad during 1984–85. He worked as Design Engineer at Bharat Heavy Electricals Limited, Jhansi during 1985–87 before joining Ministry of Industry, Govt. of India in 1988 where he worked as Assistant Development Officer till June 2000. Since June 2000, he is working as Assistant Professor in the Division of Electronics and Communication Engineering, Netaji Subhas Institute of Technology, New Delhi. His teaching and research interest are in the areas of Network Synthesis and Filter Design, Analog Integrated Circuits and Signal Processing, Bipolar and MOS current mode circuit design and chaotic nonlinear circuits and he has published thirteen papers in various international journals of repute. Raj Senani was born on March 14, 1950 at Budaun, UP, India. He received B.Sc. from Lucknow University, B.Sc. Engg. from Harcourt Butler Technological Institute, Kanpur, M.E. (Honors) from Motilal Nehru National Institute of Technology, Allahabad and Ph.D. in Electrical Engg. from the University of Allahabad. Dr. Senani held the positions of Lecturer (1975–1986) and Reader (1987–1988) at the Electrical Engineering Department of M.N.R. Engineering College, Allahabad. He joined the Electronics and Communication Engineering (ECE) Department of the Delhi Institute of Technology (DIT), Delhi in 1988 as an Assistant Professor. He became a Professor in 1990. Since then, he has served as Head, ECE Department (1990–1993, 1997–1998), Head Applied Sciences (1993–1996), Head, Manufacturing Processes and Automation Engineering (1996–1998), Dean Research (1993–1996), Dean Academic (1996–1997), Dean Administration (1997–1999), Dean Post Graduate Studies (1997–2001), Director, Netaji Subhas Institute of Technology (NSIT) during June 1996–September 1996, February 1997–June 1997 and May 2003–January 2004. He is currently functioning as Head, Division of ECE at NSIT (2000-till date). Professor Senani's teaching and research interests are in the areas of Circuits, Systems and Signal Processing, Bipolar and CMOS analog integrated circuits, Current-mode Signal processing, Electronic Instrumentation, Chaotic nonlinear circuits and Log-domain/Translinear circuits. He has authored or co-authored 100 research papers in the above areas which have been published in IEEE (USA), IEE (UK) and other international journals of repute. He served as an Honorary Editor of the Research Journal of the Institution of Electronics and Telecommunication Engineers (IETE, India) during 1990–1995, in the area of Circuits and Systems and has been a Member of the Editorial Board of the IETE Journal on Education since 1995. He has been functioning as Editorial reviewer for a number of IEEE (USA), IEE (UK) and other international journals of repute. He is currently serving as an Associate Editor for the Journal on Circuits, Systems and Signal Processing, Birkhauser Boston (USA). He is listed in several editions of Marquis' Who's Who in the World, Marquis' Who's Who in Science and Engineering, Marquis' Who' Who in Finance and Industry (all published from N.J., USA during 1998–2004); 2000 Outstanding Scholars of the 21st Century and Outstanding people of the 20th Century (both published by International Biographical Centre, Cambridge); Indo-American Who's Who (2001), Indo-Asian Who's Who (2003), Asia's Who's Who of Men & Women of Achievement (2003), Asia/Pacific Who's Who (2004) and a number of other international biographical directories.     

A biomimetic VLSI sensor for visual tracking of small moving targets

Taking inspiration from the visual system of the fly, we describe and characterize a monolithic analog very large-scale integration sensor, which produces control signals appropriate for the guidance of an autonomous robot to visually track a small moving target. This sensor is specifically designed to allow such tracking even from a moving imaging platform which experiences complex background optical flow patterns. Based on relative visual motion of the target and background, the computational model implemented by this sensor emphasizes any small-field motion which is inconsistent with the wide-field background motion.     

Fault-Tolerant and 3-Dimensional Distributed Topology Control Algorithms in Wireless Multi-hop Networks

The topology of a multi-hop wireless network can be controlled by varying the transmission power at each node. The life-time of such networks depends on battery power at each node. This paper presents a distributed fault-tolerant topology control algorithm for minimum energy consumption in multi-hop wireless networks. This algorithm is an extension of cone-based topology control algorithm [19, 12]. The main advantage of this algorithm is that each node decides on its power based on local information about the relative angle of its neighbors and as a result of these local decisions, a fault-tolerant connected network is formed on the nodes. It is done by preserving the connectivity of a network upon failing of, at most, k nodes (k is a constant) and simultaneously minimize the transmission power at each node to some extent. In addition, simulations are studied to support the effectiveness of this algorithm. Finally, it is shown how to extend this algorithm to 3-dimensions. An extended abstract version of this paper appeared in the 11th IEEE International Conference on Computer Communications and Networks(ICCCN02). Mohsen Bahramgiri born in 1979, recieved the Bachelor's degree in Mathematical Sciences from Sharif University of Technology, Tehran, Iran in 2000. He is now a PhD candidate in Mathematics Department at Massachusetts Institute of Technology. His research interests include Symplectic Hodge Theory on Higher dimentional Geometry, Kahler Geometry, Mathematical Physics and Geometric Analysis on one hand, and algorithmic Graph Theory and Combinatorics on the other hand. MohammadTaghi Hajiaghayi received the Bachelor's degree in computer engineering from Sharif University of Technology in 2000. He received the Master's degree in Computer Science from the University of Waterloo in 2001. Since 2001, he is a Ph.D. candidate in Computer Science and Artificial Intelligence Laboratory at the Massachusetts Institute of Technology. During his Ph.D. studies, he also worked at the IBM T.J. Watson Research Center (Department of Mathematical Sciences) and at the Microsoft Research (Theory group). His research interests are algorithmic graph theory, combinatorial optimizations, distributed and mobile computing, computational geometry and embeddings, game theory and combinatorial auctions, and random structures and algorithms. Vahab S. Mirrokni received the Bachelor's degree in computer engineering from Sharif University of Technology, Tehran, Iran in 2001. Since 2001, he is a Ph.D. candidate in Computer Science and Artificial Intelligence Laboratory at the Massachusetts Institute of Technology. During his Ph.D. studies, he also worked at the Bell-Laboratories (Networking Center and Department of Fundamental Mathematics). His research interests include approximation algorithms, combinatorial optimization, computational game theory, mobile computing, network mannagement, and algorithmic graph theory.     

Graphical properties of easily localizable sensor networks

The sensor network localization problem is one of determining the Euclidean positions of all sensors in a network given knowledge of the Euclidean positions of some, and knowledge of a number of inter-sensor distances. This paper identifies graphical properties which can ensure unique localizability, and further sets of properties which can ensure not only unique localizability but also provide guarantees on the associated computational complexity, which can even be linear in the number of sensors on occasions. Sensor networks with minimal connectedness properties in which sensor transmit powers can be increased to increase the sensing radius lend themselves to the acquiring of the needed graphical properties. Results are presented for networks in both two and three dimensions. B. D. O. Anderson supported by National ICT Australia, which is funded by the Australian Government’s Department of Communications, Information Technology and the Arts and the Australian Research Council through the Backing Australia’s Ability initiative and the ICT Centre of Excellence Program. A. S. Morse supported by US Army Research Office and US National Science Foundation. W. Whiteley supported in part by grants from NSERC (Canada) and NIH (USA). Y. R. Yang supported in part by US National Science Foundation. Brian Anderson is a Distinguished Professor at the Research School of Information Sciences and Engineering, The Australian National University, Australia. Professor Anderson took his undergraduate degrees in Mathematics and Electrical Engineering at Sydney University, and his doctoral degree in Electrical Engineering at Stanford University. He worked in industry in the United States and at Stanford University before serving as Professor of Electrical Engineering at the University of Newcastle, Australia from 1967 through 1981. At that time, he took up a post as Professor and Head of the Department of Systems Engineering at the Australian National University in Canberra, where he was Director of the Research School of Information Sciences and Engineering from 1994 to 2002. For approximately one year to May 2003, he was the inaugural CEO of the newly formed National ICT Australia, established by the Australian Government through the Department of Communications, Information Technology and the Arts and the Australian Research Council under the Information and Communication Technologies Centre of Excellence program. Professor Anderson has served as a member of a number of government bodies, including the Australian Science and Technology Council and the Prime Minister’s Science, Engineering and Innovation Council. He was a member of the Board of Cochlear Limited, the world’s major supplier of cochlear implants from its listing until 2005. He is a Fellow of the Australian Academy of Science and Academy of Technological Sciences and Engineering, the Institute of Electrical and Electronic Engineers, and an Honorary Fellow of the Institution of Engineers, Australia. In 1989, he became a Fellow of the Royal Society, London, and in 2002 a Foreign Associate of the US National Academy of Engineering. He holds honorary doctorates of the Catholic University of Louvain in Belgium, the Swiss Federal Institute of Technology, and the Universities of Sydney, Melbourne and New South Wales. He was appointed an Officer of the Order of Australia in 1993. He was President of the International Federation of Automatic Control for the triennium 1990 to 1993, and served as President of the Australian Academy of Science for four years from 1998 to 2002. Professor Anderson became the Chief Scientist of National ICT Australia in May 2003 and served in that role till September 2006. Tolga Eren received the B.S. degree in electrical engineering from Bilkent University, Ankara, Turkey, the M.S.E.E. degree in electrical engineering from the University of Massachusetts, the M.S. and the Ph.D. degrees in engineering and applied science from Yale University, New Haven, Connecticut, in 1994, 1998, 1999, and 2003, respectively. From October 2003 to July 2005, he was a postdoctoral research scientist at the Computer Science Department at Columbia University in the City of New York. Since September 2005, he has been at the department of Electrical Engineering at Kirikkale University, Turkey. His research interests are multi-agent (multi-robot, multi-vehicle) systems, sensor networks, computer vision, graph theory, and computational geometry. A. Stephen Morse was born in Mt. Vernon, New York. He received a BSEE degree from Cornell University, MS degree from the University of Arizona, and a Ph.D. degree from Purdue University. From 1967 to 1970 he was associated with the Office of Control Theory and Application OCTA at the NASA Electronics Research Center in Cambridge, Mass. Since 1970 he has been with Yale University where he is presently the Dudley Professor of Engineering and a Professor of Computer Science. His main interest is in system theory and he has done research in network synthesis, optimal control, multivariable control, adaptive control, urban transportation, vision-based control, hybrid and nonlinear systems, sensor networks, and coordination and control of large grouping of mobile autonomous agents. He is a Fellow of the IEEE, a Distinguished Lecturer of the IEEE Control System Society, and a co-recipient of the Society’s 1993 and 2005 George S. Axelby Outstanding Paper Awards. He has twice received the American Automatic Control Council’s Best Paper Award and is a co-recipient of the Automatica Theory/Methodology Prize . He is the 1999 recipient of the IEEE Technical Field Award for Control Systems. He is a member of the National Academy of Engineering and the Connecticut Academy of Science and Engineering. Walter Whiteley (B.Sc. 66, Queen’s University at Kingston, Canada) received his Ph.D. in Mathematics from MIT, Cambridge Mass in 1971. He is currently the Director of Applied Mathematics at York University, and a member of the graduate programs in Mathematics, in Computer Science, and in Education. His research focuses on the rigidity and flexibility of systems of geometric constraints (distances, angles, directions, projections, …). Recent work has included applications of this theory to location in networks, control of formations of autonomous agents, built structures in structural engineering, linkages in mechanical engineering, geometric constraints in computational geometry and CAD, and algorithms for protein flexibility in biochemistry. He is also active in geometry education and development of visual reasoning at all levels of mathematics education and in applications of mathematics. Yang Richard Yang received the B.E. degree in Computer Science and Technology from Tsinghua University, Beijing, China, in 1993, and the M.S. and Ph.D. degrees in Computer Science from the University of Texas at Austin in 1998 and 2001, respectively. Since 2001, he has been with the Department of Computer Science, Yale University, New Haven, CT, where currently he is an Associate Professor of Computer Science and Electrical Engineering. His current research interests are in computer networks, mobile computing, and sensor networks. He leads the Laboratory of Networked Systems (LANS) at Yale University.     

Analog VLSI focal-plane array with dynamic connections for the estimation of piecewise-smooth optical flow

An analog very large-scale integrated (aVLSI) sensor is presented that is capable of estimating optical flow while detecting and preserving motion discontinuities. The sensor's architecture is composed of two recurrently connected networks. The units in the first network (the optical-flow network) collectively estimate two-dimensional optical flow, where the strength of their nearest-neighbor coupling determines the degree of motion integration. While the coupling strengths in our previous implementations were globally set and adjusted by the operator, they are now dynamically and locally controlled by a second on-chip network (the motion-discontinuity network). The coupling strengths are set such that visual motion integration is inhibited across image locations that are likely to represent motion boundaries. Results of a prototype sensor illustrate the potential of the approach and its functionality under real-world conditions.     

A New CMOS Current-Mode Multiplexer for l0 Gbps Serial Links

This paper presents an in-depth study of the pros and cons of voltage-mode multiplexers for Gbps serial links and exploits the advantages of multiplexing in current domain. In addition, it proposes a new fully differential CMOS current-mode multiplexer where a high multiplexing speed is achieved by multiplexing at a low-impedance node. Multiplexing speed is further improved by inductive shunt peaking with active inductors. The differential configuration of the multiplexer minimizes the effect of common-mode disturbances, particularly those coupled from the power and ground rails. The flow of the output currents in the opposite directions minimizes the effect of electro-magnetic interference from channels, making the multiplexer particularly attractive for high-speed data transmission over long interconnects and printed-circuit-board (PCB) traces. The proposed multiplexer draws a constant current from the supply voltage, thereby minimizing both switching noise and noise injected to the substrate. A fully differential CMOS current-mode 8-to-l multiplexer has been implemented in TSMC’s 1.8 V 0.18 μm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3v device models. Simulation results demonstrate that the multiplexer offers sufficiently large eye-opening when multiplexed at 10 Gbps.Jean Jiang received the B.Eng. degree in Electrical Engineering from Wuhan University of Technology, Wuhan, China in 1995. From 1999 to 2001, she worked for Ericsson Global IT Services where she was a technical staff to maintain computer networks. Since 2002, she has been a research assistant with the System-on-Chip research lab of Ryerson University. She is currently a M.A.Sc candidate under the supervision of Dr. Fei Yuan in the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada. Her research interests are in analog CMOS circuit design for high-speed data communications. She was awarded the Ontario Graduate Scholarship (OGS) in 2003–2005 for academic excellence.Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the MASc. degree in chemical engineering and PhD. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively.During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Canada. During 1989–1994, he worked for Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer. Since July 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book “Computer Methods for Analysis of Mixed-Mode Switching Circuits” (Kluwer Academic Publishers, 2004, with Ajoy Opal). Dr. Yuan received an “Excellence of Teaching” award from Changzhou Institute of Technology in 1988, a post-graduate scholarship from Natural Science and Engineering Research Council (NSERC) of Canada during 1997–1998. He is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada.     

Optimization of lithographic masks using genetic algorithms

Due to its cost effectiveness and reliability, wet-chemical etching of silicon is still one of the key technologies for producing bulk-silicon microstructures. In this paper we present an approach for the design of advanced mask sets for anisotropic, wet-chemical etching of silicon. The optimization method of genetic algorithms is used to derive suitable masks for cases where geometrically calculated compensation structures fail. The underlying etch simulation is described as well as the optimization algorithm itself. Design tasks of current research projects are used as examples to illustrate the advantage of using the presented tool. Udo Triltsch was born in Bergisch Gladbach, Germany, in 1976. He received the Dipl.-Ing. degree for Mechanical Engineering from the Technical University of Braunschweig, Germany, in 2002. He is currently working towards his Ph.D. at the Institute for Microtechnology, Braunschweig, Germany. His research interests include: design methodology for MEMS, process simulation and knowledge management. Anurak Phataralaoha was born in Bangkok, Thailand, in 1973. He received the B. Eng. degree for Production Engineering from KMUTT, Thailand in 1995 and Dipl.-Ing. degree for Mechanical Engineering from Technical University of Clausthal, Germany in 2002. He is currently working towards his Ph.D. at the Institute for Microtechnology, Braunschweig, Germany. His research interests include: 3D-tactile sensors, micro machining for silicon, Tribological micro guide. Stephanus Büttgenbach obtained the Diploma and Ph.D. degrees in physics from the University of Bonn, Germany, in 1970 and 1973, respectively. From 1974 to 1985, he was with the Institute of Applied Physics of the University of Bonn, working on atomic and laser spectroscopy. In 1983, he was promoted to Professor of Physics. From 1977 to 1985, he was also a Scientific Associate at CERN in Geneva, Switzerland. In 1985, Dr. Büttgenbach joined the Hahn-Schickard-Society of Applied Research at Stuttgart as Head of the Department of Microtechnology, where he worked on micromechanics, laser microfabrication, and resonant sensors. From 1988 to 1991, he was the Founding Director of the Institute of Micro and Information Technology of the Hahn-Schickard-Society. In 1991, Dr. Büttgenbach became Professor of Microtechnology at the Technical University of Braunschweig. His current research centers on the development and application of micro sensors, micro actuators, and micro systems. Currently, he is Vice President of the Technical University of Braunschweig, where his areas of responsibility are research and technology transfer. Dima Straube was born in Berlin, Germany, in 1977. He received the Dipl.-Ing. degree for Civil Engineering from Technical University of Berlin, Germany, in 2002. He is currently working towards his Ph.D. at the Institute for Engineering Design, Braunschweig. His research interests include: design methodology for MEMS, computer aided design and tolerance management. Hans-Joachim Franke was born in Helmstedt, Germany, on February 14, 1944. He received his diploma in mechanical engineering (Dipl.-Ing.) from the Technical University of Braunschweig, Germany, in 1969. From 1969 to 1976 he was research assistant of Prof. Roth at the Institute for Engineering Design. In 1976 he received his Ph.D. degree in mechanical engineering. From 1976 to 1988 he had diverse executive positions at the KSB-AG in Frankenthal, Germany, a company, which produces pumps and valves. Since 1988 he has been the director of the Institute for Engineering Design of the Technical University of Braunschweig. His research interests are in the areas of design methodology, computer aided design and machine elements.     

FAMOUS: A Network Architecture for Delivering Multimedia Services to FAst MOving USers

When today’s commuters in the train or in a car want to access the Internet, they see themselves restricted to simple web surfing or e-mail. Interactive multimedia services, like online gaming or video conferencing are still unavailable to them, even with promising new technologies like UMTS or WiMAX. The impact of high bit rate multimedia traffic on the access network and aggregation network is an important topic, that has not been addressed in enough detail before. We designed a network architecture for offering these multimedia services to fast moving users. We refer to the overall network architecture as the FAMOUS network architecture, which consists of two parts: (i) an access network part which has to deal with large number of users, asking for a high bandwidth, while experiencing a high handoff frequency and (ii) an aggregation network part which has to deal with dynamic tunnels of very high bandwidth, while experiencing a low handoff frequency. In this paper, we detail the FAMOUS architecture, together with optimized handoff strategies, an optical switching architecture, a design methodology for dimensioning aggregations networks and automatic tunnel pre-configuration and activation. Moreover, performance results of these mentioned aspects will be presented.Filip De Greve was born in Gent, Belgium, in 1978. He received his Master of Science degree in Electrotechnical Engineering from Ghent University, Gent, Belgium in 2001. In 2002, he joined the Department of Information Technology of the Faculty of Applied Sciences, University of Ghent as a doctoral researcher. Besides specific Ethernet-related research topics, his current research interests are related to broadband communication networks and include design, routing and reliability of access and aggregation networks.Bart Lannoo was born in Torhout, Belgium, in 1979. He received his Master of Science degree in Electrotechnical Engineering from Ghent University, Ghent, Belgium in 2002. Since August 2002, he has been working with Department of Information Technology (INTEC) of the Faculty of Applied Sciences, Ghent University as a doctoral researcher. His current research interests are in optical access networks, including both fixed access networks (FTTx) and optical access for wireless communication.Liesbeth Peters received the degree in Electrotechnical Engineering from Ghent University, Belgium in 2001. Since August 2001, she has been working as a doctoral researcher with the Department of Information Technology of Ghent University, where she joined the Broadband Communications Networks Group. Since October 2002, she works there as a research assistant of the Fund for Scientific Research – Flanders (F.W.O.-V., Belgium). Her current research interests are in broadband wireless communication and the support of IP mobility in wired cum wireless networks.Tom Van Leeuwen was born in Gent, Belgium, in 1979. He received his masters degree in Computer Engineering from the Ghent University, Gent, Belgium in 2002. Since 2002, he has been working with Department of Information Technology of Ghent University (INTEC) as a doctoral researcher. In 2004 he received a PhD grant from the Institute for the Promotion of Innovation through Science and Technology in Flanders (IWT-Vlaanderen). His current research interests are in broadband wireless communication.Frederic Van Quickenborne (M. Sc. Degree in Electrotechnical Engineering, University of Ghent, Belgium, 2002) published different papers on the growing importance of ethernet in aggregation and core networks. Besides his interest in ethernet related topics (QoS, VLANs, xSTP), he is also involved in projects concerning video-streaming and is working on a Click-based ethernet testbed. This research is funded by a PhD grant from the Institute for the Promotion of Innovation through Science and Technology in Flanders (IWT-Vlaanderen), that he obtained in 2004.Didier Colle received a M.Sc. degree in electrotechnical engineering (option: communications) from the Ghent University in 1997. Since then, he has been working at the same university as researcher in the department of Information Technology (INTEC). He is part of the research group INTEC Broadband Communication Networks (IBCN) headed by Prof.: Piet Demeester. His research lead to a Ph.D. degree in February 2002. From January 2003 on, he was granted a postdoctoral scholarship from the “Instituut voor de aanmoediging van Innovatie door Wetenschap en Technologie in Vlaanderen (IWT-Vlaanderen)”. His research deals with design and planning of communication networks. His work is focussing on optical transport networks, to support the next-generation Internet. Up till now, he has actively been involved in three IST projects (LION, OPTIMIST and DAVID) and in the COST266 action. His work has been published in more than 40 scientific publications in international conferences and journals.Filip de Turck received his M.Sc. degree in Electronic Engineering from the Ghent University, Belgium, in June 1997. In May 2002, he obtained the Ph.D. degree in Electronic Engineering from the same university. From October 1997 to September 2001, Filip De Turck was research assistant with the Fund for Scientific Research-Flanders, Belgium (F.W.O.-V.). At the moment, he is a part-time professor and a post-doctoral fellow of the F.W.O.-V., affiliated with the Department of Information Technology of the Ghent University. Filip De Turck is author or co-author of approximately 80 papers published in international journals or in the proceedings of international conferences. His main research interests include scalable software architectures for telecommunication network and service management, performance evaluation and optimization of routing, admission control and traffic management in telecommunication systems.Ingrid Moerman was born in Gent, Belgium, in 1965. She received the degree in Electro-technical Engineering and the Ph.D degree from the Ghent University, Gent, Belgium in 1987 and 1992, respectively. Since 1987, she has been with the Interuniversity Micro-Electronics Centre (IMEC) at the Department of Information Technology (INTEC) of the Ghent University, where she conducted research in the field of optoelectronics. In 1997, she became a permanent member of the Research Staff at IMEC. Since 2000 she is part-time professor at the Ghent University. Since 2001 she has switched her research domain to broadband communication networks. She is currently involved in the research and education on broadband mobile & wireless communication networks and on multimedia over IP. She is author or co-author of more than 300 publications in the field of optoelectronics and communication networks.Mario Pickavet received an M.Sc. and Ph.D. degree in electrical engineering, specialized in telecommunications, from Ghent University in 1996 and 1999, respectively. Since 2000, he is professor at Ghent University where he is teaching telecommunication networks and algorithm design. His current research interests are related to broadband communication networks (WDM, IP, (G-)MPLS, OPS, OBS) and include design, long-term planning and routing of core and access networks. In this context, he is currently involved a.o. in the European IST projects “All-Optical Label Swapping Employing Optical Logic Gates in Network Nodes” (LASAGNE) and “Optical Networks: Towards Bandwidth Manageability and Cost Efficiency” (e-Photon/ONe) and in several national research projects. He has published about a hundred international publications, both in journals (e.g. IEEE JSAC, IEEE Comm. Mag., JLT) and in proceedings of conferences. He is one of the authors of the book ‘Network Recovery: Protection and Restoration of Optical, SONET-SDH, IP, and MPLS’.Bart Dhoedt received a degree in Engineering from the Ghent University in 1990. In September 1990, he joined the Department of Information Technology of the Faculty of Applied Sciences, University of Ghent. His research, addressing the use of micro-optics to realize parallel free space optical interconnects, resulted in a PhD degree in 1995. After a 2 year post-doc in opto-electronics, he became professor at the Faculty of Applied Sciences, Department of Information Technology. Since then, he is responsible for several courses on algorithms, programming and software development. His research interests are software engineering and mobile & wireless communications. Bart Dhoedt is author or co-author of approximately 70 papers published in international journals or in the proceedings of international conferences. His current research addresses software technologies for communication networks, peer-to-peer networks, mobile networks and active networks.Piet Demeester finished his PhD thesis at the Department of Information Technology (INTEC) at the Ghent University in 1988. At the same department he became group leader of the activities on Metal Organic Vapour Phase Epitaxial growth for optoelectronic components. In 1992 he started a new research group on Broadband Communication Networks. The research in this field resulted in already more than 300 publications. In this research domain he was and is a member of several programme committees of international conferences, such as: ICCCN, the International Conference on Telecommunication Systems, OFC, ICC, and ECOC. He was Chairman of DRCN’98. In 2001 he was chairman of the Technical Programme Committee ECOC’01. He was Guest Editor of three special issues of the IEEE Communications Magazine. He is also a member of the Editorial Board of the Journals “Optical Networks Magazine” and ldquo;Photonic Network Communications”. He was a member of several national and international PhD thesis commissions. Piet Demeester is a member of IEEE (Senior Member), ACM and KVIV. His current research interests include: multilayer networks, Quality of Service (QoS) in IP-networks, mobile networks, access networks, grid computing, distributed software, network and service management and applications (supported by FWO-Vlaanderen, the BOF of the Ghent University, the IWT and the European Commission). Piet Demeester is currently full-time professor at the Ghent University, where he is teaching courses in Communication Networks. He has also been teaching in different international courses.     

Output SNR Improvement in Array Processing Architectures of WCDMA Systems by Low Side Lobe Beamforming

In Wideband direct sequence code division multiple access (WCDMA) same frequency spectrum is shared through all cells simultaneously, as opposed to TDMA which is used for most 2nd generation systems. In a WCDMA system all transmitted signals turn out to be disturbing factors to all other users in the system in the form of interference limiting the system capacity. To suppress the amount of interference, fast and reliable interference controlling algorithms must be employed in next generation systems. In this paper it is shown that antenna arrays with steer able low side lobes can reduce interference in WCDMA can increase the system capacity and output signal to noise ratio of the array processing architecture. The performance metric O/P SNR of an array processing architectures is simulated in an interfering environment to demonstrate the advantage of low side lobe beamforming over adaptive antennas. Rajesh Khanna was born in Ambala, India. He received B.Sc (Engg.) degree in Electronics & Comm. in 1988 from Regional Engineering College, Kurkshetra and M.E degree in 1998 from Indian Institute of Sciences, Bangalore He was with Hartron R&D centre till 1993. Until 1999 he was in All India Radio as Assistant Station Engineer. Presently he is working as Assistant Professor in the department of Electronics & Communication at Thapar Institute of Engineering & Technology, Patiala. He is also pursuing his PhD in the area of adaptive antennas for mobile communication. He has published 12 papers in national and International conferences. Rajiv Saxena was born in Gwalior, India. He received his B.E degree in Electronics and Telecommunication Engineering from Jabalpur University, M.E degree in Elect Engg from Jiwaji University, Gwalior and PhD from University of Roorkee in 1982, 1990 and 1996 respectively. He worked as an engineer in GRASIM and Reliance Textile Industries till 1983. In 1984 he joined Electronics Engineering Department of Madhav Institute of Technology and Sciences, Gwalior as Lecturer. He became Reader in 1990 and Professor in 2002. Presently he is Principal Rustam Ji Institute of Technology, BSF Academy, Tekanpur Distt. – Gwalior (M.P.). He has published more than 53 papers in various national and International Journals and conferences. His research interests include wireless and mobile communication and Digital Signal Processing.     

Analysis of bandwidth allocation algorithms for wireless personal area networks

A major issue in the design and operation of ad hoc networks is sharing the common spectrum among links in the same geographic area. Bandwidth allocation, to optimize the performance of networks in which each station can converse with at most a single neighbor at a time, has been recently studied in the context of Bluetooth Personal Area Networks. There, centralized and distributed, capacity assignment heuristics were developed, with applicability to a variety of ad hoc networks. Yet, no guarantees on the performance of these heuristics have been provided. In this paper, we extend these heuristics such that they can operate with general convex objective functions. Then, we present our analytic results regarding these heuristics. Specifically, we show that they are β-approximation (β<2) algorithms. Moreover, we show that even though the distributed and centralized algorithms allocate capacity in a different manner, both algorithms converge to the same results. Finally, we present numerical results that demonstrate the performance of the algorithms. Randeep Bhatia received the Ph.D. degree in Computer Science from University of Maryland, the M.S. degree in Mathematics and Computer Science from University of Illinois at Chicago and the B.Tech. degree in Computer Science and Engineering from Indian Institute of Technology, Delhi. He is currently with the High Speed Networks Research Department at Bell Labs, Lucent technologies, working on network design, traffic engineering and scheduling algorithms. His current research interests are in the area of QoS for multimedia services in wireless data networks. Adrian Segall received the B.Sc. and M.Sc. degrees in electrical engineering from the Technion, Israel Institute of Technology in 1965 and 1971, respectively, and the Ph.D. degree in electrical engineering with a minor in statistics from Stanford University in 1973. After serving active duty in the Israel Defense Forces, he joined in 1968 the Scientific Department of Israel’s Ministry of Defense. From 1973 to 1974 he was a Research Engineer at System Control Inc., Palo Alto, CA and a Lecturer at Stanford University. From 1974 to 1976 he was an Assistant Professor of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology. From 1987 to 1998 he was on the faculty of the Department of Computer Science at the Technion. He is presently Benjamin Professor of Computer-Communication Networks in the Department of Electrical Engineering, Technion, Israel Institute of Technology. From 1982 to 1984 he was on leave with the IBM T.J.Watson Research Center, Yorktown Heights, NY. He held visiting positions with IBM, AT&T and Lucent Bell Labs. His current research interests are in the area of optical networks, wireless, sensor and ad-hoc networks. Dr. Segall is an IEEE Fellow and has served in the past as Editor for Computer Communication Theory of the IEEE Transactions on Communications, Editor for the IEEE Information Theory Society Newsletter and Senior Editor for the IEEE Journal on Selected Areas in Communications. He was selected as an IEEE delegate to the 1975 IEEE-USSR Information Theory Workshop, and is the recipient of the 1981 Miriam and Ray Klein Award for Outstanding Research and of the 1990 Taub Award in Computer Science. Gil Zussman received the B.Sc. degree in Industrial Engineering and Management and the B.A. degree in Economics (both summa cum laude) from the Technion—Israel Institute of Technology in 1995. He received the M.Sc. degree (summa cum laude) in Operations Research from Tel-Aviv University in 1999 and the Ph.D. degree in Electrical Engineering from the Technion—Israel Institute of Technology in 2004. Between 1995 and 1998, he served as an engineer in the Israel Defense Forces. He is currently a Postdoctoral Associate in the Laboratory for Information and Decision Systems in MIT. His current research interests are in the area of ad hoc and sensor networks. In particular, he is interested in energy efficient protocols, medium access control protocols, and personal area networks. Gil received the Knesset (Israeli Parliament) Award for distinguished students, the Best Student Paper Award at the IFIP-TC6 Networking 2002 Conference, and the IEEE Communications Magazine Best Paper Award at the OPNETWORK 2002 Conference. In 2004 he received the Marie Curie Outgoing International Fellowship and the Fulbright Fellowship.     

Low Power Downlink MAC Protocols for Infrastructure Wireless Sensor Networks

This paper addresses low power medium access control (MAC) protocols for the downlink channel of infrastructure wireless sensor networks. Access points are assumed to be energy unconstrained. The trade-off between the power consumption of the sensor nodes and the transmission delay is analyzed, focusing on low traffic. We describe WiseMAC (Wireless Sensor MAC), a new protocol for the downlink of infrastructure wireless sensor networks. Another original contribution is the presentation and analysis of PTIP (Periodic Terminal Initiated Polling). Here, polling is used in the reversed direction as compared to common polling protocols. WiseMAC and PTIP are compared with PSM (Power Save Mode), the power save protocol used in both the IEEE 802.11 and IEEE 802.15.4 ZigBee standards. Analytical expressions are derived for the power consumption and the transmission delay for each protocol, as a function of the wake-up period. It is shown that WiseMAC provides, with low bit rate radio transceivers, a significantly lower power consumption than PSM. Although less energy efficient than WiseMAC and PSM, it is shown that PTIP can, thanks to its implementation simplicity, become attractive for applications tolerating large transmission delays.Amre El-Hoiydi received the electrical engineer degree from the Swiss Federal Institute of Technology in Zurich (ETHZ), Switzerland, in 1994. In 1995, he was a teaching assistant at the Swiss Federal Institute of Technology in Lausanne (EPFL), working on mobility management for low earth orbit mobile satellite communication systems. In 1996, he joined CSEM (Neuchâtel, Switzerland). Since then, he has been working on several research and development projects dealing with various aspects of wireless communications. In the ACTS RAINBOW and FRAMES projects, he was involved with the network and air interface aspects of 3rd generation cellular systems. In the ESPRIT INFOGATE and IST OPENROUTER projects, he worked on electronic design and embedded programming of Linux based wireless LAN gateways. His current research focus is low power communication protocols for wireless sensor networks.Jean-Dominique Decotignie is head of the real-time and networking group at the Swiss Center for Electronics and Microsystems (CSEM) in Neuchâtel. He is professor at the School of Computer and Communication Sciences of EPFL (Swiss Federal Institute of Technology in Lausanne) and teaches real-time systems as well as hardware and software design. From 1977 to 1982, he has worked at EPFL and the University of Tokyo in the area of optical communications. In 1983, he joined the Industrial Computer Engineering Lab. at EPFL where he became Assistant Professor in 1992. From 1989 to 1992, he has been the head of an interdisciplinary project on Computer Integrated Manufacturing at EPFL. Since January 1997, he is with CSEM. His current research interests include industrial and real-time local area networks, distributed control systems and software engineering for real-time systems as well as real-time wireless networks.     

Future Directions for Biomedical Engineering Research: Recommendations of an Evaluation Workshop for the NIGMS Physiology and Biomedical Engineering Program

This report presents the recommendations of participants in a workshop held to evaluate the content of the Physiology and Biomedical Engineering Program of the National Institute of General Medical Sciences (NIGMS). On the basis of a systematic review of the field, a number of promising areas were identified in which further work is needed.     

Network-Adaptive Video Communication Using Packet Path Diversity and Rate-Distortion Optimized Reference Picture Selection

In this paper, we present error-resilient Internet video transmission using path diversity and rate-distortion optimized reference picture selection. Under this scheme, the optimal packet dependency is determined adapting to network characteristics and video content, to achieve a better trade-off between coding efficiency and forming independent streams to increase error-resilience. The optimization is achieved within a rate-distortion framework, so that the expected end-to-end distortion is minimized under the given rate constraint. The expected distortion is calculated based on an accurate binary tree modeling with the effects of channel loss and error concealment taken into account. With the aid of active probing, packets are sent across multiple available paths according to a transmission policy which takes advantage of path diversity and seeks to minimize the loss rate. Experiments demonstrate that the proposed scheme provides significant diversity gain, as well as gains over video redundancy coding and the NACK mode of conventional reference picture selection. Yi Liang received the Ph.D. degree in Electrical Engineering from Stanford University in 2003. His expertise is in the areas of networked multimedia systems, real-time voice and video communication, and low-latency media streaming over the wire-line and wireless networks. Currently holding positions at Qualcomm CDMA Technologies, San Diego, CA, he is responsible for video and multimedia system design and development for Qualcomm's mobile station modem (MSM) chipsets. From 2000 to 2001, he conducted research with Netergy Networks, Inc., Santa Clara, CA, on voice over IP systems that provide improved quality over best-effort networks. From 2001 to 2003, he had been the lead of the Stanford - Hewlett-Packard Labs low-latency video streaming project, in which he and his colleagues developed error-resilience techniques for rich media communication over IP networks at low latency. In the summer of 2002 at Hewlett-Packard Labs, Palo Alto, CA, he developed an accurate loss-distortion model for compressed video and contributed in the development of the mobile streaming media content delivery network (MSM - CDN) that delivers rich media over 3G wireless. Yi Liang received the B. Eng. degree from Tsinghua University, Beijing, China. Eric Setton received the B.S. degree from Ecole Polytechnique, Palaiseau, France in 2001 and the M.S. degree, in Electrical Engineering from Stanford University in 2003. He is currently a Ph.D. candidate in the department of Electrical Engineering of Stanford University and is part of the Image, Video and Multimedia Systems group. Multimedia communication over wired and wireless networks, video compession and image processing are his main research interests. In 2001, he received the Carnot fellowship and the SAP Stanford Graduate fellowship. In 2003, he received the Sony SNRC fellowship. He has spent time in industry in France at SAGEM and in the United States at HP labs and at Sony Electronics. He has 4 patents pending. Bernd Girod is Professor of Electrical Engineering in the Information Systems Laboratory of Stanford University, California. He also holds a courtesy appointment with the StanfordDepartment of Computer Science and he serves as Director of the Image Systems Engineering Program at Stanford. His research interests include networked media systems, video signal compression and coding, and 3-d image analysis and synthesis. He received his M.S. degree in Electrical Engineering from Georgia Institute of Technology, in 1980 and his Doctoral degree “with highest honours” from University of Hannover, Germany, in 1987. Until 1987 he was a member of the research staff at the Institut fur Theoretische Nachrichtentechnik und Informationsverarbeitung, University of Hannover, working on moving image coding, human visual perception, and information theory. In 1988, he joined Massachusetts Institute of Technology, Cambridge, MA, USA, first as a Visiting Scientist with the Research Laboratory of Electronics, then as an Assistant Professor of Media Technology at the Media Laboratory. From 1990 to 1993, he was Professor of Computer Graphics and Technical Director of the Academy of Media Arts in Cologne, Germany, jointly appointed with the Computer Science Section of Cologne University. He was a Visiting Adjunct Professor with the Digital Signal Processing Group at Georgia Institute of Technology, Atlanta, GA, USA, in 1993. From 1993 until 1999, he was Chaired Professor of Electrical Engineering/Telecommunications at University of Erlangen-Nuremberg, Germany, and the Head of the Telecommunications Institute I, co-directing the Telecommunications Laboratory. He has served as the Chairman of the Electrical Engineering Department from 1995 to 1997, and as Director of the Center of Excellence “3-D Image Analysis and Synthesis” from 1995-1999. He has been a Visiting Professor with the Information Systems Laboratory of Stanford University, Stanford, CA, during the 1997/98 academic year. As an entrepreneur, Prof. Girod has worked successfully with several start-up ventures as founder, investor, director, or advisor. Most notably, he has been a co-founder and Chief Scientist of Vivo Software, Inc., Waltham, MA (1993–98); after Vivo's aquisition, 1998-2002, Chief Scientist of RealNetworks, Inc. (Nasdaq: RNWK); and, from 1996–2004, an outside Director of 8 × 8, Inc. (Nasdaq: EGHT). Prof. Girod has authored or co-authored one major text-book, two monographs, and over 250 book chapters, journal articles and conference papers in his field, and he holds about 20 international patents. He has served as on the Editorial Boards or as Associate Editor for several journals in his field, and is currently Area Editor for Speech, Image, Video and Signal Processing of the “IEEE Transactions on Communications.” He has served on numerous conference committees, e.g., as Tutorial Chair of ICASSP-97 in Munich and ICIP-2000 in Vancouver, as General Chair of the 1998 IEEE Image and Multidimensional Signal Processing Workshop in Alpbach, Austria, and as General Chair of the Visual Communication and Image Processing Conference (VCIP) in San Jose, CA, in 2001. Prof. Girod has been a member of the IEEE Image and Multidimensional Signal Processing Committee from 1989 to 1997 and was elected Fellow of the IEEE in 1998 ‘for his contributions to the theory and practice of video communications.’ He has been named ‘Distinguished Lecturer’ for the year 2002 by the IEEE Signal Processing Society. Together with J. Eggers, he is recipient of the 2002 EURASIP Best Paper Award.     

M<Emphasis Type="SmallCaps">AP</Emphasis>: Medial axis based geometric routing in sensor networks

One of the challenging tasks in the deployment of dense wireless networks (like sensor networks) is in devising a routing scheme for node to node communication. Important consideration includes scalability, routing complexity, quality of communication paths and the load sharing of the routes. In this paper, we show that a compact and expressive abstraction of network connectivity by the medial axis enables efficient and localized routing. We propose MAP, a Medial Axis based naming and routing Protocol that does not require geographical locations, makes routing decisions locally, and achieves good load balancing. In its preprocessing phase, MAP constructs the medial axis of the sensor field, defined as the set of nodes with at least two closest boundary nodes. The medial axis of the network captures both the complex geometry and non-trivial topology of the sensor field. It can be represented succinctly by a graph whose size is in the order of the complexity of the geometric features (e.g., the number of holes). Each node is then given a name related to its position with respect to the medial axis. The routing scheme is derived through local decisions based on the names of the source and destination nodes and guarantees delivery with reasonable and natural routes. We show by both theoretical analysis and simulations that our medial axis based geometric routing scheme is scalable, produces short routes, achieves excellent load balancing, and is very robust to variations in the network model. A preliminary version appeared in ACM International Conference on Mobile Computing and Networking (MobiCom’05), August, 2005. This work was supported in part by the Lee Center for Advanced Networking at the California Institute of Technology, and by NSF grant CCR-TC-0209042. Jie Gao’s work was done at Center for the Mathematics of Information, California Institute of Technology, Pasadena, CA 91125. Anxiao (Andrew) Jiang’s work was done at Department of Electrical Engineering, California Institute of Technology, Pasadena, CA 91125. Jehoshua Bruck is the Gordon and Betty Moore Professor of Computation and Neural Systems and Electrical Engineering at the California Institute of Technology. During 2003–2005 he served as the founding Director of Caltech's Information Science and Technology (IST) program. He received the B.Sc. and M.Sc. degrees in electrical engineering from the Technion, Israel Institute of Technology, in 1982 and 1985, respectively and the Ph.D. degree in Electrical Engineering from Stanford University in 1989. His research combines work on the design of distributed information systems and the theoretical study of biological circuits and systems. Dr. Bruck has an extensive industrial experience, including working with IBM Research for ten years where he participated in the design and implementation of the first IBM parallel computer. He was a co-founder and chairman of Rainfinity (acquired in 2005 by EMC), a spin-off company from Caltech that focused on software products for management of network information systems. He is an IEEE fellow, and his awards include the National Science Foundation Young Investigator award and the Sloan fellowship. He published more than 200 journal and conference papers and he holds 25 US patents. His papers were recognized in journals and conferences, including, winning the 2005 S. A. Schelkunoff Transactions prize paper award from the IEEE Antennas and Propagation society and the 2003 Best Paper Award in the 2003 Design Automation Conference. Jie Gao received her Ph.D in computer science from Stanford University in 2004, and her BS degree from University of Science and Technology of China in 1999. She is currently an assistant professor at Computer Science department, State University of New York, Stony Brook. Her research interests include algorithms, ad hoc communication and sensor networks, and computational geometry. Anxiao (Andrew) Jiang received the B.S. degree with honors in 1999 from the Department of Electronic Engineering, Tsinghua University, Beijing, China, and the M.S. and Ph.D. degrees in 2000 and 2004, respectively, from the Department of Electrical Engineering, California Institute of Technology. He is currently an assistant professor in the Department of Computer Science, Texas A&M University. He was a recipient of the four-year Engineering Division Fellowship from the California Institute of Technology in 1999. His research interests include algorithm design, ad hoc communication and sensor networks, and file storage and retrieval.     

Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

Todays digital signal processing (DSP) applications use computationally complex and/or adaptive algorithms and have stringent requirements in terms of speed, size, cost, power consumption, and throughput. Efficient hardware implementation techniques should be employed to meet the requirements of these applications. Run-Time Reconfiguration (RTR) is a promising technique for reducing the hardware required for implementing DSP systems as well as improving the performance, speed and power consumption of these systems. In this survey, we explain different issues in run-time reconfigurable systems and list the implemented systems which support run-time reconfiguration. We also describe different applications of run-time reconfiguration and discuss the improvements achieved by applying run-time reconfiguration.Alireza Shoa received his B.Sc degree in Electrical Engineering from Sharif University of Technology, Tehran, Iran in 2001 and M.A.Sc degree in Electrical Engineering from McMaster University, Hamilton, Canada in 2003. Currently, he is a PhD candidate in Electrical Engineering at McMaster University. His research interests include VLSI circuits for signal processing and communication applications and image and video processing.Shahram Shirani received his B.S. in Electrical Engineering from Isfahan University of Technology, Isfahan, Iran, and M.Sc. in Biomedical Engineering from Amirkabir University of Technology, Tehran, Iran, and Ph.D. in Electrical Engineering from University of British Columbia, Vancouver, Canada, in 1989, 1994 and 2000 respectively. Since 2000 he has been with the department of Electrical and Computer Engineering, McMaster University, where he is an assistant professor. His research interests include image and video compression, multimedia communications, and ultrasonic imaging. He is a member of technical committee of IEEE International Conference on Image Processing (ICIP). He is a licensed professional engineer and a member of Institute of Electrical and Electronics Engineers (IEEE).