A glitch-corrector circuit for low-spur ADPLLs

This paper identifies the unavoidable time skew between counter and TDC inputs, if not properly compensated or corrected, as the major source of spurs in the output spectrum of an All-Digital-Phase-Locked Loops (ADPLLs). The frequency and the level of the main spur induced by the time skew are first analytically estimated. Then, an ADPLL, operating in the 3?C4-GHz band, is designed in 90-nm CMOS technology and the reported simulations confirm the theoretical results. A simple glitch-removal circuit, capable of operating even in the presence of fast and large frequency drifts is proposed. The glitch corrector is demonstrated to cancel out the ?24-dBc spur and its harmonics, without altering the lock transient behavior of the ADPLL.     

基于非均匀采样模型的DDS相位截断杂散谱分析

该文提出直接数字频率合成器(DDS)的非均匀采样模型,在此模型的基础上对DDS的相位截断频谱杂散进行了分析和计算,给出了一些重要的结论并指出了影响杂散特性一种较为准确的解释。同时给出了一种抑制相位截断噪音的方法。Matlab仿真结果表明在一定条件下该方法能够有效抑制相位截断误差。     

一种低抖动低杂散的亚采样锁相环

设计了一个5.156 25 GHz低抖动、低杂散的亚采样锁相环,使用正交压控振荡器产生4路等相位间隔时钟。分析了电荷泵的杂散理论,使用差分缓冲器和互补开关对实现了低杂散。使用Dummy采样器和隔断缓冲器,进一步减小了压控振荡器对杂散的恶化。该亚采样锁相环在40 nm CMOS工艺下实现,在1.1 V的供电电压下,功耗为7.55 mW;在156.25 MHz频偏处,杂散为-81.66 dBc;亚采样锁相环输出时钟的相位噪声在10 kHz~100 MHz区间内积分,得到均方根抖动为0.26 ps。     

A low phase noise PLL using Vackar VCO and a wide-locking range tunable divider for V-band signal generation in 65-nm CMOS

This paper presents a low phase noise integer-N phase-locked loop (PLL) for V-band signal generation. To enhance the frequency stability, we use a new class of Vackar voltage-controlled oscillator (VCO) in the PLL. The Vackar VCO achieves a low phase noise performance by effectively suppressing the AM-PM conversion. To properly align the locking range with the output of the VCO, a divider with wide locking range is realized by the current-mode logic (CML) D-flip-flops with tunable load. For spur reduction, an enhanced charge-pump structure is used to reject transient current glitches. With good static and dynamic current matching achieved in the charge pump, the reference spur is suppressed down to ?50 dBc. The designed PLL is implemented in a 65 nm RFCMOS process, and the measurement demonstrates a low phase noise signal up to 17 GHz. The in-band phase noise (at 1 MHz offset) and out-band phase noise (at 50 MHz offset) are ?103.6 and ?126.8 dBc/Hz, respectively. The PLL consumes 50.7 mW and occupies a chip area of 0.9 mm².     

DDS谱质分析及其杂散抑制研究综述

简介了ＤＤＳ工作原理,总结了关于ＤＤＳ杂散噪声来源的分析及其相关的研究结论,概述了近年来ＤＤＳ杂散抑制研究的有关方法,介绍了ＤＤＳ一些新的结构改进设计和应用。     

厂站直流系统接地故障检测方法分析

由于绝缘监测装置的电流互感器只接在母线馈线回路上,因此不能找出具体的接地支路。基于比较电流幅值的变频信号检测原理在一定程度上实现了自动查找故障支路的功能,但可靠性受故障支路分布电容及接地电阻的影响较大。本文通过改进变频信号检测原理的算法,消除了故障支路分布电容及接地电阻对检测可靠性的影响,并计算出故障支路的接地电阻值,提高了查找的可靠性。     

Dynamical simulation of quantum-well structures

For the design and development of optical semiconductor devices based on quantum-well structures, the investigation of saturation phenomena is necessary for high optical power operation. By applying stationary physical models, nonlinear effects cannot be described adequately; hence, transient models are important for an accurate analysis. By utilizing transient models, saturation phenomena, signal delays, and distortions can be investigated. For the analysis of integrated optoelectronic devices, such as lasers and modulators, transient transport or density matrix equations for carriers and photons and the Poisson equation have to be solved self-consistently. A transient model which is useful for the investigation of a wide range of optoelectronic applications is presented. Quantum optical phenomena are included by applying the interband density matrix formalism in real-space representation, where the Coulomb singularity is treated exactly in the limits of the discretization. As we focus on electroabsorption modulators, a drift-diffusion model adequately approximates the transport properties. Here, quantum effects are considered by a quantum correction, the Bohm potential. The model is applied to investigate transport effects in InP-based waveguide electroabsorption modulators including strained lattices     

基于分布式光纤传感的丁坝形变监测研究

介绍了丁坝的结构特点,针对丁坝在汛期容易产生坝基坍塌和崩岸等险情,采用分布式光纤传感技术,构建了基于瑞士Omnisens公司生产的DiTeSt光纤传感分析仪的丁坝形变监测系统;搭建了丁坝试验模型,并对丁坝试验模型进行了加载试验,对试验结果进行了分析,试验结果有利于指导进一步的工程实践研究。     

Phase-domain fractional-N frequency synthesizers

The concept of phase-domain fractional-N frequency synthesis is presented. Synthesizers using this architecture can achieve fast frequency switching without limiting the minimum channel spacing. In this architecture, a numerical phase comparator is used in conjunction with weighting coefficients, as a linear weighted phase-frequency detector. The synthesizer output spur level is determined by two factors. Namely, the delay of the numerical phase comparator, and the accuracy of the digital-to-analog convertor (DAC) used to convert the phase error to the analog domain. A novel second-order timing-error cancelation scheme is proposed to eliminate the effect of the phase comparator delays. Using this technique together with a 10-bit accuracy DAC, a maximum spur level of less than -65 dBc is simulated for a 900-MHz synthesizer. The settling time of the simulated synthesizer is less than 7 /spl mu/s, and is independent of the channel spacing. The details of the synthesizer architecture, design considerations, and system-level simulations are presented. Implementation issues including the DAC accuracy and timing-error effects are discussed extensively throughout the text.     

相控阵天线适当随机馈相对DDS 杂散的抑制*

将用于相控阵天线的随机馈相法,应用于DDS 的设计。这种方法的优点是,采用这种随机馈相,在DDS 中,频率偏差的均值为零,而且其杂散可得到抑制。当采用随机馈相的改进型,即适当随机馈相法时,DDS 杂散的峰值进一步降低。文中,给出了计算结果,并对不同随机馈相方法的计算结果进行了比较。     

Spur-reduced digital sinusoid synthesis

This paper presents and analyzes a technique for reducing the spurious signal content in digital sinusoid synthesis. Spur reduction is accomplished through dithering amplitude and phase values prior to wordlength reduction. The analytical approach developed for analog quantization is used to produce new bounds on spur performance in these dithered systems. Amplitude dithering allows output wordlength reduction without introducing additional spurs. Effects of periodic dither similar to that produced by a pseudo-noise (PN) generator are analyzed. This phase dithering method provides a spur reduction of 6(M+1) dB per phase bit when the dither consists of M uniform variates. While the spur reduction is at the expense of an increase in system noise, the noise can be made white, making the noise power spectral density small. This technique permits the use of a smaller number of phase bits addressing sinusoid look-up tables, resulting in an exponential decrease in system complexity. Amplitude dithering allows the use of less complicated multipliers and narrower data paths in purely digital applications, as well as the use of coarse-resolution, highly-linear digital-to-analog converters (DAC's) to obtain spur performance limited by the DAC linearity rather than its resolution     

Trapping Effects in the Transient Response of AlGaN/GaN HEMT Devices

In this paper, the transient analysis of an AlGaN/GaN high-electron mobility transistor (HEMT) device is presented. Drain-current dispersion effects are investigated when gate or drain voltages are pulsed. Gate-lag and drain-lag turn-on measurements are analyzed, revealing clear mechanisms of current collapse and related dispersion effects. Numerical 2-D transient simulations considering surface traps effects in a physical HEMT model have also been carried out. A comparison between experimental and theoretical results is shown. The presence of donor-type traps acting as hole traps, due to their low energy level of 0.25 eV relative to the valence band, with densities >1e20 cm^-3 (>5e12 cm^-2), uniformly distributed at the HEMT surface, and interacting with the free holes that accumulated at the top surface due to piezoelectric fields, accounts for the experimentally observed effects. Time constants next to 10 ms are deduced. Some additional features in the measured transient currents, with faster time constants, could not be associated with surface states     

Functional modeling of integrated injection logic—Transient analysis

A transient analysis of integrated-injection logic I²L structures is presented. This analysis is based on calculating the different depletion and neutral region charges. Doping profile, high-level effects, and geometrical layout are taken into account. To formulate a transient functional model of the structure, regional transient delays are defined as ratios of the corresponding charges to the electron current density Jnof the n-p-n vertical transistor. An analytical expression is given for the dominant storage time; τepi. The ratio of the stored charges in a metal-covered and oxide-covered base region is related to the surface recombination velocity and the ratio of the corresponding current densities. In a partitioned CAD model (as in Berger's injection model), the regional transient delays are expressed in terms of the corresponding current densities rather than Jn. The computed results for a five-state ring oscillator are compared to measurements.     

一种能有效减小DDS杂散的设计方法

在分析了直接数字频率合成(DDS)工作原理及现有的设计方法中引起DDS杂散的原因后，提出了一种通过改进ROM查表结构消除相位截断效应的设计方法，然后介绍了设计在FPGA芯片上的实现，最后给出了利用MATLAB软件对设计方法进行仿真的结果。     

相位量化数字射频存储器的寄生信号性能分析

本文导出了相位量化数字射频存储器的寄生信号性能。其寄生信号幅度随谐波次数的增加单调减小,峰值寄生信号为2~m-1次谐波(其中m为量化位数),其幅度为(2~m-1)~(-1),而近区(峰值寄生信号之前各次谐波)的寄生信号幅度为零。     

Ku波段宽带低噪声雷达频率源的研制

介绍一种低相噪、低杂散、宽带的雷达频率合成器方案的设计和实现,该方案采用超低相噪模拟锁相环芯片,并采用双环环内下混频结构,通过对环路滤波器的精心设计,大幅度改善相位噪声和杂散性能。给出设计过程及测试结果。实验证明该方案是成功的,达到的主要技术指标为:输出频率12.8~14.8 GHz,相位噪声-90 dBc/Hz@1 kHz,杂散-55 dBc,步进间隔50 MHz。     

Enhancing reliability with thermal transient testing

Thermal transient measurement, the method for the characterisation of IC packages is gaining increasing importance. The measurement of these transients requires dedicated equipment. The paper discusses the methodology of thermal transient measurements in details, including the compensation of second order effects as non-linearity, non-constant powering etc. In the following part the evaluation methods and algorithmic solutions are discussed. A typical example is presented. Reliability issues are discussed in the last section of the paper, including the problem of die attach testing. The contribution of the thermal transient measurements to the analysis of thermo-mechanical strain is demonstrated.     

A low jitter, low spur multiphase phase-locked loop for an IR-UWB receiver

A low jitter,low spur multiphase phase-locked loop(PLL) for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator(VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the l...     

直接数字射频调制器的实现

介绍了将I／Q两路8Bit信号转换成射频信号的一种直接数字射频调制实现方式．它通过采用温度计码编码减小数字信号跳变导致的噪声毛刺，而采用8-fold线性内插信号作为一阶保持信号的近似处理．大大抑制了数字信号镜像成分。对电路进行模拟后，双边带调制后信号镜像成分抑制53．52dB以上。噪声毛刺抑制53．01dB以上，单边带调制后信号镜像成分抑制59．15dB以上，噪声毛刺抑制53．92dB以上。     

Charge-control analysis of the COMFET turn-off transient

A quasi-static charge-control analysis of the unique transient turn-off characteristic of the COMFET is developed. The analysis describes the transient behavior in terms of steady ON-state current components that flow in the constituent MOSFET and BJT in the basic COMFET structure. The effects of the expanding depletion region at the cathode and of minority-carrier injection into the anode are properly accounted for. Consequently, the physics underlying the turnoff time is clarified, and device design criteria for shortening it, without considerably degrading the ON-state current conduction capability, are suggested.