4H-SiC埋沟MOSFET的研制

研制了4H-SiC热氧化生长氧化层埋沟nMOSFET.用室温下N离子注入的方法形成埋沟区和源漏区,然后在1600℃进行激活退火.离子注入所得到的埋沟区深度大约为0.2μm.从转移特性提取出来的峰值场效应迁移率约为18.1cm2/(V·s).造成低场效应迁移率的主要因素可能是粗糙的器件表面(器件表面布满密密麻麻的小坑).3μm和5μm器件的阈值电压分别为1.73V和1.72V.3μm器件饱和跨导约为102μS( V G=20V, V D=10V).     

Normally-off 4H-SiC trench-gate MOSFETs with high mobility

A new 4H-SiC trench-gate MOSFET structure with epitaxial buried channel for accumulation-mode operation, has been designed and fabricated, aiming at improving channel electron mobility. Coupled with improved fabrication processes, the MOSFET structure eliminates the need of high dose N⁺ source implantation. High dose N⁺ implantation requires high-temperature (1550 °C) activation annealing and tends to cause substantial surface roughness, which degrades MOSFET threshold voltage stability and gate oxide reliability. The buried channel is implemented without epitaxial regrowth or accumulation channel implantation. Fabricated MOSFETs subject to ohmic contact rapid thermal annealing at 850 °C for 5 min exhibit a high peak field-effect mobility (μ_FE) of 95 cm²/V s at room temperature (25 °C) and 255 cm²/V s at 200 °C with stable normally-off operation from 25 °C to 200 °C. The dependence of channel mobility and threshold voltage on the buried channel depth is investigated and the optimum range of channel depth is reported.     

Nitrogen Implantation to Improve Electron Channel Mobility in 4H-SiC MOSFET

Normally off 4H-SiC MOSFET devices have been fabricated on a p-type semiconductor and electrically characterized at different temperatures. A gate oxide obtained by nitrogen ion implantation performed before the thermal oxidation of SiC has been implemented in n-channel MOSFET technology. Two samples with a nitrogen concentration at the SiO₂/SiC interface of 5 X 10¹⁸ and 1.5 X 10¹⁹ cm^-3 and one unimplanted sample have been manufactured. The sample with the highest N concentration at the interface presents the highest channel mobility and the lowest threshold voltage. For increasing temperature, in all the samples, the threshold voltage decreases, and the electron channel mobility increases. The latter case attains a maximum value of about 40 cm²/V ldr s at 200degC for the sample with the highest N concentration. These trends are explained by the reduction of interface electron traps in the upper half of the band gap toward the conduction band edge. These results demonstrate that N implantation can be effectively used to improve the electrical performances of an n-type surface channel 4H-SiC MOSFET.     

Digital CMOS IC's in 6H-SiC operating on a 5-V power supply

A CMOS technology in 6H-SiC utilizing an implanted p-well process is developed. The p-wells are fabricated by implanting boron ions into an n-type epilayer. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells using a thermally grown gate oxide. The resulting NMOS devices have a threshold voltage of 3.3 V while the PMOS devices have a threshold voltage of -4.2 V at room temperature. The effective channel mobility is around 20 cm ²/Vs for the NMOS devices and around 7.5 cm²/Vs for the PMOS devices. Several digital circuits, such as inverters, NAND's, NOR's, and 11-stage ring oscillators are fabricated using these devices and exhibited stable operation at temperatures ranging from room temperature to 300°C. These digital circuits are the first CMOS circuits in 6H-SiC to operate with a 5-V power supply for temperatures ranging from room temperature up to 300°C     

Counter-doped MOSFETs of 4H-SiC

In this paper, we investigate the effect of counter-doping of nitrogen at the channel region of epitaxial n-channel 4H-SiC MOSFETs on the channel mobility and the threshold voltage. From this study, we have found that the channel mobility steeply improves as the nitrogen dose increases. At a dose of 2× or 2.5×10¹² cm^-2 the enhancement MOSFET has achieved an effective channel mobility of 20 cm²/Vs or a field effect mobility of 38 cm²/Vs at a peak     

Excellent effects of hydrogen postoxidation annealing on inversionchannel mobility of 4H-SiC MOSFET fabricated on (112¯0) face

Effects of hydrogen postoxidation annealing (H₂ POA) on 4H-silicon carbide (SiC) MOSFETs with wet gate oxide on the (112¯0) face have been investigated. As a result, an inversion channel mobility of 110 cm²/Vs was successfully achieved using H₂ POA at 800°C for 30 min. H₂ POA reduces the interface trap density by about one order of magnitude compared with that without H₂ POA, resulting in considerable improvement of the inversion channel mobility to 3.5 times higher than that without H₂ POA. In addition, 4H-SiC MOSFET with H₂ POA has a lower threshold voltage of 3.1 V and a wide gate voltage operation range in which the inversion channel mobility is more than 100 cm²/Vs     

Improved inversion channel mobility for 4H-SiC MOSFETs followinghigh temperature anneals in nitric oxide

Results presented in this letter demonstrate that the effective channel mobility of lateral, inversion-mode 4H-SiC MOSFETs is increased significantly after passivation of SiC/SiO₂ interface states near the conduction band edge by high temperature anneals in nitric oxide. Hi-lo capacitance-voltage (C-V) and ac conductance measurements indicate that, at 0.1 eV below the conduction band edge, the interface trap density decreases from approximately 2×10¹³ to 2×10¹² eV^-1 cm^-2 following anneals in nitric oxide at 1175°C for 2 h. The effective channel mobility for MOSFETs fabricated with either wet or dry oxides increases by an order of magnitude to approximately 30-35 cm²/V-s following the passivation anneals     

The planar 6H-SiC ACCUFET: a new high-voltage power MOSFETstructure

A novel planar accumulation channel SiC MOSFET structure is reported in this paper. The problems of gate oxide rupture and poor channel conductance previously reported in SiC UMOSFETs are solved by using a buried P⁺ layer to shield the channel region. The fabricated 6H-SiC unterminated devices had a blocking voltage of 350 V with a specific on-resistance of 18 mΩ.cm² at room temperature for a gate bias of only 5 V. This measured specific on-resistance is within 2.5× of the value calculated for the epitaxial drift region (10¹⁶ cm^-3, 10 μm), which is capable of supporting 1500 V     

1.1 kV 4H-SiC power UMOSFETs

Silicon Carbide (4H-SiC), power UMOSFETs were fabricated and characterized from room temperature to 200°C. The devices had a 12-μm thick lightly doped n-type drift layer, and a nominal channel length of 4 μm. When tested under Fluorinert^TM at room temperature, blocking voltages ranged from 1.0 kV to 1.2 kV. Effective channel mobility ranged from 1.5 cm²/V.s at room temperature with a gate bias of 32 V (3.5 MV/cm) up to 7 cm²/V.s at 100°C with an applied gate bias of 26 V (2.9 MV/cm). Specific on-resistance (R_on,sp) was calculated to be as low as 74 mΩ.cm² at 100°C under the same gate bias     

4H-SiC MOSFETs utilizing the H2 surface cleaningtechnique

The H₂ cleaning technique was examined as the precleaning of the gate oxidation for 4H-SiC MOSFETs. The device had a channel width and length of 150 and 100 μm, fabricated on the p-type epitaxial layer of 3×10¹⁶ cm^-3. The gate oxidation was performed after the conventional RCA cleaning, and H₂ annealing at 1000°C. The obtained channel mobility depends on the pre-cleaning process strongly, and was achieved 20 cm²/N s in the H₂ annealed sample. The effective interface-state density was also measured by the MOS capacitors fabricated on the same chips, resulting 1.8×10¹² cm^-2 from the photo-induced C-V method     

Dependence of electron channel mobility on Si-SiO2interface microroughness

The effect of the Si-SiO₂ interface microroughness on the electron channel mobility of n-MOSFETs was investigated. The surface microroughness was controlled by changing the mixing ratio of NH₄ OH in the NH₄OH-H₂O₂-H₂O solution in the RCA cleaning procedure. The gate oxide was etched, following the evaluation of the electrical characteristics of MOS transistors, to measure the microroughness of the Si-SiO₂ interface with scanning tunneling microscopy (STM). As the interface microroughness increases, the electron channel mobility, which can be obtained from the current-voltage characteristics of the MOSFET, gets lower. The channel mobility is around 360 cm²/V-s when the average interface microroughness is 0.2 nm, where the substrate impurity concentration is 4.5×10¹⁷ cm^-3, i.e. the electron bulk mobility is 400 cm²/V-s. It goes down to 100 cm²/V-s when the interface microroughness exceeds 1 nm     

High channel mobility in inversion layers of 4H-SiC MOSFETs byutilizing (112¯0) face

A dramatic improvement of inversion channel mobility in 4H-SiC MOSFETs was successfully achieved by utilizing the (112¯0) face: 17 times higher (95.9 cm²/Vs) than that on the conventional (0001) Si-face (5.59 cm²/Vs). A low threshold voltage of MOSFETs on the (112¯0) face indicates that the (112¯0) MOS interface has fewer negative charges than the (0001) MOS interface. Small anisotropy of channel mobility in 4H-SiC MOSFETs (μ_(11¯00)/μ₍₀₀₀₁₎=0.85) reflects the small anisotropy in bulk electron mobility     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

High-voltage accumulation-layer UMOSFET's in 4H-SiC

A novel silicon carbide UMOSFET structure is reported. This device incorporates two new features: a self-aligned p-type implantation in the bottom of the trench that reduces the electric field in the trench oxide, and an n-type epilayer under the p-base to promote lateral current spreading into the drift region. This UMOS structure is capable of supporting the full blocking voltage of the pn junction while keeping the electric field in the gate oxide below 4 MV/cm. An accumulation channel is formed on the sidewalls of the trench by epigrowth, and the gate oxide is produced by a polysilicon oxidation process, resulting in a uniform oxide thickness over both the sidewalls and bottom of the trench. The fabricated 4H-SiC devices have a blocking voltage of 1400 V (10 μm drift region), a specific on-resistance of 15.7 mΩ-cm ² at room temperature, and a gate oxide field of 3 MV/cm     

Insulator investigation on SiC for improved reliability

Significant improved high-temperature reliability of SiC metal-insulator-semiconductor (MIS) devices has been achieved with both thermally grown oxides and by using a stacked dielectric consisting of silicon oxide-nitride-oxide (ONO). Capacitors of p-type 6H-SiC, n-type 6H-SiC and n-type 4H-SiC were fabricated with a variety of insulators. The best performance was accomplished only with insulators incorporating silicon dioxide. A new thermal oxidation process of growing a dry oxide then following with a wet re-oxidation anneal produces an oxide with the dielectric strength of a dry oxide and the high-quality interface of a wet oxide. MIS field effect transistors (MISFETs) with an ONO gate insulator had surface channel mobilities similar to MISFETs with thermal gate oxides, and demonstrated a lifetime of 10 days at 335°C and 15 V bias. The lifetime of the ONO MISFET was a factor of 100 higher than for devices fabricated with deposited oxides, which had been the prior state of the art for high-temperature MISFETs on SiC     

Device quality MOS Gate insulators: Sputter deposition and low temperature processing

A series of n-channel, Al-gate MOS transistors were fabricated using reactively sputtered SiO2as the gate insulator. The SiO2was deposited at low temperatures and low RF powers, and during subsequent processing was not subjected to temperatures in excess of 465°C. Test results showed that for gate oxides deposited at 20 W, the measured breakdown strength was 3-4 MV/cm with interface trapped charge density of 4-8 × 10¹⁰cm^-2and that the resulting electron mobility of the transistor was 470 cm²/V.s. After annealing in nitrogen at 1000°C, the deposited oxides exhibited electrical properties which are very similar to those of thermally grown SiO2.     

Electron gate currents and threshold stability in the n-channel stacked gate MOS tetrode

A new structure is given for the n-channel stacked gate MOS tetrode which consists of a polycrystalline silicon buried control gate and thermally grown oxide for the offset gate insulator. As a result of the large band-bending in the offset gate depletion region of an operating tetrode, some drain current electrons surmount the Si-SiO2energy barrier and are injected into the oxide. Since the electron trapping is relatively small in the thermal-oxide offset gate insulator, it was possible to measure gate currents of up to2 times 10^{-4}A/cm². The gate current was measured as a function of the drain current, the drain voltage and the offset gate voltage. The resulting behavior confirms previous models of the tetrode device. Since electron trapping is much less in thermally grown oxide than in deposited pyrolytic oxide which was used formerly, the offset gate threshold voltage shifts less. As a result of this effect the new structure is used to advantage in fabricating the n-channel stacked gate tetrode in that the drain current is comparatively insensitive to changes in the offset gate voltage.     

High-performance polycrystalline SiGe thin-film transistors usingAl2O3 gate insulators

The use of aluminum oxide as the gate insulator for low temperature (600°C) polycrystalline SiGe thin-film transistors (TFTs) has been studied. The aluminum oxide was sputtered from a pure aluminum target using a reactive N₂O plasma. The composition of the deposited aluminum oxide was found to be almost stoichiometric (i.e., Al₂O₃), with a very small fraction of nitrogen incorporation. Even without any hydrogen passivation, good TFT performance was measured an devices with 50-nm-thick Al₂O₃ gate dielectric layers. Typically, a field effect mobility of 47 cm²/Vs, a threshold voltage of 3 V, a subthreshold slope of 0.44 V/decade, and an on/off ratio above 3×10⁵ at a drain voltage of 0.1 V can be obtained. These results indicate that the direct interface between the Al₂ O₃ and the SiGe channel layer is sufficiently passivated to make Al₂O₃ a better alternative to grown or deposited SiO₂ for SiGe field effect devices     

SiC devices: physics and numerical simulation

The important material parameters for 6H silicon carbide (6H-SiC) are extracted from the literature and implemented into the 2-D device simulation programs PISCES and BREAKDOWN and into the 1-D program OSSI Simulations of 6H-SiC p-n junctions show the possibility to operate corresponding devices at temperatures up to 1000 K thanks to their low reverse current densities. Comparison of a 6H-SiC 1200 V p-n^--n⁺ diode with a corresponding silicon (Si) diode shows the higher switching performance of the 6H-SiC diode, while the forward power loss is somewhat higher than in Si due to the higher built-in voltage of the 6H-SiC p-n junction. This disadvantage can be avoided by a 6H-SiC Schottky diode. The on-resistances of Si, 3C-SiC, and 6H-SiC vertical power MOSFET's are compared by analytical calculations. At room temperature, such SiC MOSFET's can operate up to blocking capabilities of 5000 V with an on-resistance below 0.1 Ωcm², while Si MOSFET's are limited to below 500 V. This is checked by calculating the characteristics of a 6H-SiC 1200 V MOSFET with PISCES. In the voltage region below 200 V, Si is superior due to its higher mobility and lower threshold voltage. Electric fields in the order of 4×10⁶ V/cm occur in the gate oxide of the mentioned 6H-SiC MOSFET as well as in a field plate oxide used to passivate its planar junction. To investigate the high frequency performance of SiC devices, a heterobipolartransistor with a 6H-SiC emitter is considered. Base and collector are assumed to be out of 3C-SiC. Frequencies up to 10 GHz with a very high output power are obtained on the basis of analytical considerations     

High field-effect mobility in n-channel Si face 4H-SiC MOSFETs with gate oxide grown on aluminum ion-implanted material

We report investigations of Si face 4H-SiC MOSFETs with aluminum (Al) ion-implanted gate channels. High-quality SiO/sub 2/-SiC interfaces are obtained both when the gate oxide is grown on p-type epitaxial material and when grown on ion-implanted regions. A peak field-effect mobility of 170 cm/sup 2//V/spl middot/s is extracted from transistors with epitaxially grown channel region of doping 5/spl times/10/sup 15/ cm/sup -3/. Transistors with implanted gate channels with an Al concentration of 1/spl times/10/sup 17/ cm/sup -3/ exhibit peak field-effect mobility of 100 cm/sup 2//V/spl middot/s, while the mobility is 51 cm/sup 2//V/spl middot/s for an Al concentration of 5/spl times/10/sup 17/ cm/sup -3/. The mobility reduction with increasing acceptor density follows the same functional relationship as in n-channel Si MOSFETs.