Status and application of HgCdTe device modeling

In this article, device modeling refers to numerical simulation of semiconductor device physics to predict electrical behavior. The silicon integrated circuit industry provides the example for the use of technology computer-aided design to simulate wafer fabrication processes, and the electrical performance of devices and circuits. This paper first reviews semiconductor device modeling in general, then as applied in work supporting the development and analysis of HgCdTe infrared detectors. Example applications of one- and two-dimensional device modeling are simulation of a bias-selectable, integrated two-color detector, and two-dimensional effects on the spectral response of a HgCdTe detector with composition grading.     

Multivariate rational regression and its application in semiconductor device modeling

Physics equation-based semiconductor device modeling is accurate but time and money consuming. The need for studying new material and devices is increasing so that there has to be an efficient and accurate device modeling method. In this paper, two methods based on multivariate rational regression (MRR) for device modeling are proposed. They are single-pole MRR and double-pole MRR. The two MRR methods are proved to be powerful in nonlinear curve fitting and have good numerical stability. Two methods are compared with OLS and LASSO by fitting the SMIC 40 nm MOS-FET I–V characteristic curve and the normalized mean square error of Single-pole MRR is \begin{document}$3.02 \times {10^{{\rm{ - }}8}}$\end{document} which is 4 magnitudes less than an ordinary least square. The I–V characteristics of CNT-FET and performance indicators (noise factor, gain, power) of a low noise amplifier are also modeled by using MRR methods. The results show MRR methods are very powerful methods for semiconductor device modeling and have a strong nonlinear curve fitting ability.     

多胞MOSFET器件的射频建模和参数提取

对纳米级金属氧化物半导体场效应管器件提出了改进的小信号模型.该改进模型中综合考虑了馈线的趋肤效应和器件多胞结构的影响.提取过程中, 根据可缩放规律, 由传统模型的参数推导出元胞参数.将模型应用于8×0.6×12 μm (栅指数×栅宽×元胞数量)、栅长为90 nm的MOSFET器件在1~40 GHz范围内的建模, 测试所得S参数和模型仿真所得S参数能够高度地吻合.     

深亚微米CMOS器件建模与BSIM模型

介绍了深亚微米CMOS器件基于电荷模型、基于表面势模型和基于电导模型的建模方法及其优缺点,并以BSIM系列模型为例,讨论了BSIM系列模型特点及半导体工艺发展对CMOS器件建模方法的影响。     

Large-signal modeling method for power FETs and diodes

Under a large signal drive level, a frequency domain black box model of the nonlinear scattering function is introduced into power FETs and diodes. A time domain measurement system and a calibration method based on a digital oscilloscope are designed to extract the nonlinear scattering function of semiconductor devices. The extracted models can reflect the real electrical performance of semiconductor devices and propose a new large-signal model to the design of microwave semiconductor circuits.     

功率FET和二极管大信号建模方法

Under a large signal drive level,a frequency domain black box model of the nonlinear scattering function is introduced into power FETs and diodes.A time domain measurement system and a calibration method based on a digital oscilloscope are designed to extract the nonlinear scattering function of semiconductor devices.The extracted models can reflect the real electrical performance of semiconductor devices and propose a new large-signal model to the design of microwave semiconductor circuits.     

OFDM系统同步算法研究及其VLSI实现

针对正交频分复用（OFOM, Orthogonal Frequency Division Multiplex）无线传输系统,提出并设计了一种适用于802．11a标准前导序列的同步算法。首先基于接收基带数据能量判断信道空闲状态,再计算数据归一化自相关值检测帧起始位置,最后利用基带数据与参考训练序列的互相关运算检测OFDM符号的起始位置,实现同步功能。算法的硬件实现采用移位加和流水线技术来提高系统的性能与效率。实践表明,所提算法能有效地实现同步并且硬件实现复杂度低,适合于超大规模集成电路（VLSI,Very LargeScale Integration）的实现。     

基于偏心Preissmann格式的高速互连线分析

 将偏心Preissmann格式应用于高速电路互连线分析,导出一种互连线离散模型.通过调整偏心参数,可以获得二阶精度的差分格式.数值仿真表明,该方法能够应用于一般互连线的瞬态分析,改善间断之后的数值扰动现象,并与特征法进行了比较,说明了方法的有效性.     

Two‐dimensional modeling of front contact silicon solar cells

The modeling of a new type of silicon solar cell intended for operation at very high concentration, with all the contacts at its front face, is presented. The two‐dimensional model developed makes use of the theory of the complex variable, and is able to explain the main features of the operation of these cells. It is shown that if all the parameters reach good state‐of‐the‐art values, and with the appropriate layout, this structure can reach 25% efficiency for a range of concentrations wider than any other known silicon cell. Copyright © 2004 John Wiley & Sons, Ltd.     

Novel direct designs for 3-input XOR function for low-power and high-speed applications

Novel direct designs for 3-input exclusive-OR (XOR) function at transistor level are proposed in this article. These designs are appropriate for low-power and high-speed applications. The critical path of the presented designs consists of only two pass-transistors, which causes low propagation delay. Neither complementary inputs, nor V _DD and ground exist in the basic structure of these designs. The proposed designs have low dynamic and short-circuit power consumptions and their internal nodes dissipate negligible leakage power, which leads to low average power consumption. Some effective approaches are presented for improving the performance, voltage levels, and the driving capability and lowering the number of transistors of the basic structure of the designs. All of the proposed designs and several classical and state-of-the-art 3-input XOR circuits are simulated in a realistic condition using HSPICE with 90 nm CMOS technology at six supply voltages, ranging from 1.3 V down to 0.8 V. The simulation results demonstrate that the proposed circuits are superior in terms of speed, power consumption and power-delay product (PDP) with respect to other designs.     

Numerical modeling of fluctuation phenomena in semiconductors and detailed noise study of mid-wave infrared HgCdTe-heterostructure devices

The aim of this paper is to present an effective numerical model of fluctuation phenomena in semiconductor structures with an arbitrarily defined doping profile and variable-band structure. The model enables the spectral intensity of the noise current to be calculated. It is known that the 1/f noise may result in fluctuations of the carrier mobility. It is not clear, however, why strong 1/f noise is observed in reverse-biased HgCdTe nonequilibrium photodiodes when saturation currents are usually very low. In the present paper, we try to answer this question. Although the nonequilibrium mode of operation leads to the reduction of the generation-recombination (g-r) noise, it increases the electric field as well as the band mobility of carriers and its fluctuations. The observed low-frequency noise is due to the fluctuations of current density caused by mobility fluctuations assisted by the electric field.     

基于几何规划的模拟器件建模与电路性能优化

基于分段线性函数,提出一种新的对模拟器件进行建模的方法,并提出乐观、悲观两种数据拟合算法,两种算法均能较好地拟合MOS管参数。模型建立之后,利用几何规划对电路性能进行优化。乐观算法会得到较好的电路性能,但可能不满足约束条件;悲观算法能够严格满足约束条件,但是得到的电路性能未必最优。在此基础上,提出一种基于响应曲面方法的折衷优化算法,能够得到综合考虑电路性能和约束条件的电路设计参数。最后,以两级放大器为优化实例,证明该方法的有效性。     

SiC半导体材料和工艺的发展状况

碳化硅(SiC)是一种宽禁带半导体材料,适用于制作高压、高功率和高温器件,并可以工作在直流到微波频率范围.阐述了SiC材料的性质,详细介绍了SiC器件工艺(掺杂、刻蚀、氧化及金属半导体接触)的最新进展,并指出了存在的问题及发展趋势.     

三维圆柱形电荷俘获存储器件的继续微缩对其性能的影响

本文详细地研究了关键尺寸的继续微缩对三维圆柱形无结型电荷俘获存储器器件性能的影响。通过Sentaurus三维器件仿真器,我们对器件性能的主要评价指标进行了系统地研究,包括编程擦除速度和高温下的纵向电荷损失及横向电荷扩散。沟道半径的继续微缩有利于操作速度的提升,但使得纵向电荷损失, 尤其是通过阻挡层的纵向电荷损失,变得越来越严重。栅极长度的继续微缩在降低操作速度的同时将导致俘获电荷有更为严重的横向扩散。栅间长度的继续微缩对于邻近器件之间的相互干扰有决定性作用,对于特定的工作温度及条件其值需谨慎优化。此外,栅堆栈的形状也是影响电荷横向扩散特性的重要因素。研究结果为高密度及高可靠性三维集成优化提供了指导作用。     

微电子工艺模拟及器件分析的CA方法研究进展

综述了用于微电子工艺模拟和器件分析的元胞自动机（CA）方法的研究进展，分析了现有CA方法的优势，并比较了CA方法与其它方法的优缺点。在此基础上，展望了微电子工艺模拟及器件分析的CA方法的发展前景。对研究采用CA方法模拟微电子加工工艺和进行微电子器件分析具有参考意义。     

一种电迁移测试失效时间判定方法

采用铜大马士革工艺制备了用于电迁移测试的样品,对电迁移测试过程中存在的两类电阻-时间(R-t)特征曲线进行了研究.研究发现采用固定电阻变化率作为失效判定标准所得的失效时间分布曲线不能真实地反映样品的实际寿命,而采用第一次阻值跳变点对应的时间作为失效时间所得的分布曲线则更符合电迁移理论.针对两种失效判定方法所得到的不同结果进行了机理分析,结果表明,采用第一次阻值跳变点对应的时间作为失效时间分析电迁移失效更合理.     

分立器件测试系统软件平台的设计及实现

为解决目前国内分立器件测试系统成本高,可维护性低等特点,开发了一套性价比高、操作简单、自动化程度较高的测试系统。并采用层次化、模块化的软件结构设计方法,设计开发了分立器件测试系统的软件平台。该软件平台可以完成系统硬件资源自检与校准、软件账号管理、流程图测试程序自动转换、测试指标报表生成及打印等一系列功能,并做到测试程序...     

半导体分立器件的可靠性工艺控制方法

重点介绍了国内外半导体器件制造工艺与器件可靠性的相关性报道：工艺缺陷、微缺陷、关键工艺对器件质量和可靠性的影响及其控制方法；还介绍了关键工艺控制点的确定及其参数控制范围以及生产高质量、高可靠性器件的工艺环境的控制要求。     

Perspectives and challenges in nanoscale device modeling

In this paper, we discuss the role of adequate modelling tools in the development of nanoelectronic technology and devices, including both down-the-roadmap Complementary Metal-Oxide-Semiconductor (CMOS) technology and alternative nanodevices. Such tools can enable understanding of the relevant physical mechanisms on the one hand, and performance evaluation and optimization of device structures, on the other hand. Relevant examples are discussed, drawn by our recent activity, including ballistic strained-silicon Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs), stress-induced leakage currents, nanocrystal memories, and silicon nanowire transistors.