Electrical characteristics of large scale integration (LSI) MOSFETs at very high temperatures part II: Experiment

An experimental investigation of the effects of high temperature (25°C to 300°C) on N and P channel MOS transistors is reported. At the device level, the temperature dependences of the electrical parameters are characterized individually; they include the threshold voltage, the channel mobility, and junction leakage currents. Drain current I–V characteristics are obtained for each of the subthreshold, nonsaturation, and saturation regions of operation, with temperature as a parameter. Zero-Temperature-Coefficient (ZTC) points' properties are found to be in good agreement with the theory.     

Scaling merged single-device-well MOSFETs for very large scale integration

Single-Device-Well (SDW) MOSFETs are high density MOSFET structures based on merging two MOSFET devices; a surface channel device and a buried channel device sharing the same device well and the same gate. SDWs offer a potential device area saving of 50%. The merits of the merged SDW MOSFETs are further enhanced in a scaled down MOSFET VLSI technology. This is the subject of this paper.     

超大规模集成电路芯片的激光缺陷检测技术

介绍了激光扫描散射检测超大规模集成电路芯片上缺陷的原理，描述了对芯片沾污质粒子与芯片电路图形缺陷的检测方法，并对它们的特点进行了比较。     

Computer-aided design of an eight bit binary counter N-MOS chip for large scale integration (LSI)

An integrated eight bit synchronous binary counter along with input/output circuits: gate protection, two phase clock, pad-out has been designed for MOS LSI. The counter has a master-slave flip-flop and a combinational logic to generate the next state, and outgoing carry outputs from this stage. The combination logic has been implemented using pass transistors and thus acts as a steering type logic. This type of logic is very fast, consumes lesser power and needs significantly less area for its implementation.Latest CAD techniques: interactive Graphics system of Applicon AGS/860 LSI Design Station, MOS circuit simulation program MSINC and Design Rule Check (DRC) program have been used for design and chip layout. The entire chip has been laid out in the area of 3 × 3 mm² including test devices and structures for testability analysis. The design is based on LOCOS N-MOS (E-D) technology and 8 micron design rules. The Electromask pattern generation (PG) tape has been prepared from Applicon for making chrome masks.A set of six masks have been used for the fabrication of device and die encapsulated in dual-in line package and tested for its performance. Counter works up to 5 MHz clock frequency as expected from design calculations. From 25 stage ring oscillator frequency measurement the gate delay comes out to be 6 nS.The counter design could easily be substituted as a sub-system/building block or cell in any MOS LSI system design where it makes a part of it.     

Electrical characteristics of CdTe:Pb single crystals at high temperatures

The electrical properties of CdTe:Pb single crystals at high temperatures (400–900°C) and under controlled Cd vapor pressure (0.001–3 atm) were investigated for the first time. The temperature and baric dependences of the conductivity and Hall coefficient were measured. Low (in comparison with undoped CdTe) electron concentration indicates an increase in the number of impurity point defects related to the Pb impurity. The results obtained are explained within the Kröger theory of quasi-chemical reactions of defect formation on the assumption that lead may exist in the isolated state (Pb _Cd ⁺ ) and as a component of (Pb _Cd ⁺ V _Cd ^2? )^? associates.     

Electrical characteristics of very thin SiO2deposited at low substrate temperatures

Very thin (≲ 100-Å) films of SiO2have been deposited by a modified plasma-enhanced chemical-vapor deposition (PECVD) process at very low substrate temperatures (≲ 350°C). Low flow rates of reactive gases and a high flow of inert carrier gas were used to lower the deposition rate, ensuring improved dielectric properties and good control over film thickness. Measurements made on MOS capacitors of current-voltage characteristics, electrical breakdown, interface trap density, and mobile ion drift indicate that these very thin PECVD films are approaching thermally grown SiO2in quality and may be suitable as gate dielectrics in device applications.     

Low frequency characteristics of a quasioptical Schottky diode detector part I: Theory

A theoretical study is made of saturation effects of FIR point contacts Schottky diodes when used in the envelope detection mode of operation. A model is described that fits experimental results for radiation wavelength ranging from microwaves down to FIR wavelengths. This model permits the prediction of saturation levels throughout this range.     

Charge loss in metal-nitride-oxide-semiconductor (MNOS) devices at high temperatures

The charge loss from the nitride layer of MNOS transistors has been studied with emphasis on the temperature effects in the range from 25 to 175°C. The trend of major interest is the increase in the logarithmic decay rate of the dominant negative threshold voltage with increasing temperature. This result is believed due to a combination of three temperature related mechanisms: (1) thermal excitation (TE) discharge, (2) Poole-Frenkel emission-drift-capture events and (3) increasing nitride conductivity with increasing temperature.     

Influence of substrate freeze-out on the characteristics of MOS transistors at very low temperatures

The low temperatures current-voltage characteristics of N-channel MOS transistors have been analysed. An excess drain current is observed for intermediate values of drain voltage. This anomalous drain current is explained in terms of substrate freeze-out, since at very low temperatures the MOS structure has a type of floating substrate potential within the depletion region. Due to the increase of the majority carrier current, flowing through the substrate to the source at increasing drain voltage, this substrate potential increases and causes a change of threshold voltage. This change is observed in the current-drain voltage characteristics of the MOSFET. Various experiments, such as measurements of substrate current, effects of temperature, gate and substrate voltages, support this interpretation. MOS transistors with various geometries and various dopings are analysed.     

History dependence of output characteristics ofsilicon-on-insulator (SOI) MOSFETs

It is demonstrated that the drain current overshoot in partially depleted SOI MOSFETs has a significant history dependence or memory effect, even in the absence of impact ionization under low drain biases. The measured output characteristics of partially depleted SOI MOSFETs are shown to be dynamically dependent on their switching history, frequency, and bias conditions, due to the finite time constants of carrier generation (thermal or impact ionization) and recombination in the floating body     

Piezoresistive characteristics of short-channel MOSFETs on (100)silicon

This paper demonstrates that the intrinsic piezoresistive response of the MOSFET channel is independent of length. The reported fall-off of the piezoresistive response of the transistor in short channel devices is shown to be the result of parasitic series resistance in the source of the transistor. At the same time, the experimental results demonstrate that the threshold voltage of the devices is essentially independent of stress. The results are verified for three independent processes     

Annealing of lead zirconate titanate (65/35) thin films for ultra large scale integration storage dielectric applications: Phase transformation and electrical characteristics

Thin film capacitors of Lead Zirconate Titanate (PZT, 400 nm) of Zr/Ti ratio 65/35, deposited by reactive dc-magnetron sputtering, with low leakage current and high charge storge density(’Q _c ) for use as capacitor dielectrics in ultra-large scale integration dynamic random access memory (ULSI DRAM) cells have been fabricated and studied. The equivalent SiO₂ thickness for the optimized film is 5.3å for the fresh film and 9.1å after 10¹⁰ unipolar stress cycles (0 to -3 V). The leakage current density is 1.32 × 10^-7A/cm² for 3 V operation which is equivalent to an effective SiO₂ field of 55 MV/ cm. X-ray diffraction analysis reveals that as-deposited films (T _dep . = 200? C) contain no detectable perovskite phase. Post-deposition annealing is therefore essential, and critical to the fabrication of high quality capacitors for memory applications. The pyrochlore-to-perovskite phase transformation, the evolution of the microstructure, composition and the presence of different phases in the film have been studied as a function of annealing conditions. There is a purely outward radial growth of the interphase boundary, resulting in the increase in the curved surface area of the cylindrical perovskite aggregates throughout the film thickness with increasing thermal budget. The increase in perovskite phase content with annealing time at a constant annealing temperature indicates that a diffusional phase transformation from the pyrochlore to cubic perovskite phase above the Curie temperature occurs as a first step in the formation of the ferroelectric perovskite phase. The variation of two important dielectric properties, charge storage density and leakage current density is reported as a function of the annealing time and temperature. Furthermore, the variation of the charge storage density due to unipolar dynamic electrical stress is studied. The total area under the large-frequency C-V curve (which is the total reversible polarization) increases under unipolar dynamic stress (0 to -3 V) after 10¹⁰ stress cycles. The degradation in charge storage density is found to be primarily due to an increase in remanent polarization caused by the shift in the hysteresis loop as a result of the reduction in the internal bias field under the influence of the unipolar dynamic stress.     

Experimental modelling of high frequency circuits at low audio frequencies part I

At microwave frequencies, frequent use is made in circuit design of the electrical properties of short lengths of resistively terminated transmission line. It will be shown in the following contribution that circuits based on high frequency distributed lines can usefully be modelled at low audio frequencies using lumped element lines.     

Negative bias temperature instabilities in HfSiO(N)-based MOSFETs: Electrical characterization and modeling

Negative bias temperature instabilities (NBTI) in SiO_x(N)/HfSiO(N)/TaN based pMOSFETs are investigated. It is shown that nitrogen-incorporation in the gate stack (either by NH₃ anneals or decoupled plasma nitridation, DPN) result in much enhanced NBTI. Device degradation is mainly due to fast (interface) state generation in the non-nitrided stacks, while a substantial contribution of the defects produced in the nitrided stacks are slow (bulk) states. The kinetics of fast interface states is modeled within a reaction-dispersive transport model, taking into account the dispersive transport of protons generated from the depassivation of trivalent Si dangling bonds at the Si/SiO_x interace (P_b0 centers). The generation of slow states in the nitrided stacks is simulated by an electrochemical model, considering the electric field and hole assisted breaking of nitrogen-related defects, tentatively attributed to Si₂N or Hf₂N dangling bonds. A correlation between NBTI and recovery is also found, namely that enhanced NBTI in nitrided stacks results in enhanced recovery. This suggests that recovery mainly arises from the detrapping of holes at the N-related defects.     

Linearity and power characteristics of SiGe HBTs at high temperatures for RF applications

In this paper, the power gain, power-added efficiency (PAE) and linearity of power SiGe heterojunction-bipolar transistors at various temperatures have been presented. The power characteristics were measured using a two-tone load-pull system. For transistors biased with fixed base voltage, the small-signal power gain and PAE of the devices increase with increasing temperature at low base voltages, while they decrease at high base voltages. Besides, the linearity is improved at high temperature for all voltage biases. However, for devices with fixed collector current, the small-signal power gain, PAE, and linearity are nearly unchanged with temperature. The temperature dependence of power and linearity characteristics can be understood by analyzing the cutoff frequency, the collector current, Kirk effect and nonlinearities of transconductance at different temperatures.     

An advanced finite element strategy for thermal stress field investigation in aluminium interconnections during processing of very large scale integration multilevel structures

An advanced strategy for modelling the thermal stress induced in aluminium interconnections during processing of multilevel structures is presented. The advantage of the approach described is that it allows the residual stresses from one processing step to be used as the initial conditions for a subsequent step. 2D elasto-plastic model (von Mises plastic criterion) is implemented in Finite Element Code and it is shown that even after significant relaxation by plastic deformation, high thermal stress resides in the aluminium line in both width and thickness directions. The technique demonstrated here is for a silicon-glass–aluminium-glass structure. However, it is readily extended to more complex situations and material combinations.     

The near field of dipole antennas, part I: Theory

The theoretical and experimental evaluation of the electromagnetic fields in the immediate vicinity of resonant dipole antennas is presented. This type of antenna is widely used with portable and mobile radio transmitters. The work presented herein has been motivated by the concern that future Radio Frequency Protection Guides with respect to human exposure to nonionizing electromagnetic radiation might be expressed strictly in terms of the intensity squared of the electric or magnetic fields. It is shown in the results that it is possible to detect relatively high intensity electromagnetic (EM) fields in close proximity to resonant dipoles even for very low levels of radiated power (1 mW and less). The paper is divided into a theoretical section and an experimental section because its goals are twofold. First, the formulas for the correct evaluation of the EM fields in the close proximity to dipole antennas are established. Second, it is shown that such EM fields, which can be theoretically predicted and experimentally verified with satisfactory accuracy, are indeed strong enough to violate proposed Radio Frequency Protection Guides even for very low levels of radiated power. Thus portable radios are rendered virtually useless, although the same guides permit exposures to much higher levels of power in the far field. Part I of the paper is essentially theoretical and expresses the fields near dipole antennas in terms of cylindrical waves, which lend themselves to closed form integration. The asymptotic expressions of some components of the field are particularly simple for close distances (in terms of wavelength) from the antenna. The correctness of the solution is checked by evaluating how closely boundary conditions are satisfied. Results have shown that previously used formulas for evaluating field intensity very near dipole antennas can give incorrect values.     

15 GHz频段下会议室内信道大尺度衰落特性测量与分析

传统移动蜂窝频段的严重短缺,使得高频段的开发与利用受到越来越多的关注与研究.采用了基于PN序列的时域测量系统,在15 GHz频段下对会议室环境的直视场景(LOS)和非直视场景(NLOS)进行了信道测量,分析了其大尺度衰落特性,得到了距离和路径损耗的关系,并计算得出室内会议室环境下的路径损耗指数和阴影衰落因子.测量采用了增益为27 dBi的双脊波导天线和全向天线,通过改变发射天线水平角得到某个距离下的测量数据,分析了特定场景下接收功率随角度的变化特性.