High-voltage SOS/MOS devices and circuit elements: Design, fabrication, and performance

High-voltage metal-oxide-semiconductor (HVMOS) transistors fabricated with low-voltage MOS circuits on the same silicon-on-sapphire (SOS) chip are critical for EAROM's and plasma display applications. An examination of the voltage limitations in conventional MOS is described. Several approaches to fabricating HVMOS transistors are analyzed, including the MOS tetrode, the extended drain MOST, and the double diffused MOST. Results of parameter tests on these devices are given and characteristics of HVMOS circuit elements discussed.     

In-process voltage stressing to increase reliability of MOS integrated circuits

Time-dependent dielectric breakdown of gate oxides is one of the principal failure mechanisms of MOS integrated circuits. Voltage stressing of completed devices, which has been used to screen oxide defects and to thereby increase product reliability, is less effective with scaled high-density MOS integrated circuits because of limitations in the voltage which can be applied. Inprocess voltage stressing of silicon wafers, prior to completion of wafer processing, offers a feasible technique for achieving an effective voltage screen. Several possible techniques for inprocess voltage stressing are described, and the advantages and limitations of these are outlined. Data are presented showing typical fast-ramp dielectric breakdown distributions for MOS transistor arrays with an oxide thickness of 35 and 50 nm. Time-dependent dielectric breakdown distribution data on devices from the same wafers indicate that with all MOS transistors of an integrated circuit connected in parallel, as in one type of inprocess voltage stressing, defective oxide sites can be screened in periods of time ranging from a few seconds to hours. Inprocess voltage stressing, by decreasing susceptibility of completed devices to time-dependent dielectric breakdown, can substantially increase MOS integrated circuit reliability.     

Technological design considerations for monolithic MOS switched-capacitor filtering systems

In this paper, various technological and topological considerations for the design of monolithic MOS switched-capacitor (SC) filtering systems are described. The properties of the passive and active devices typically available in depletion-load NMOS and CMOS technologies are presented as they relate to various SC peformance parameters. Layout techniques for improving specific performance parameters are also given. An overview of MOS operational-amplifier design emphasizes technological considerations in the design of high-performance SC systems. Finally, several important techniques are reviewed for maximizing dynamic range in SC circuits.     

Small signal properties of field effect devices

The small signal properties of field effect devices are treated analytically. The analysis is based upon an active, distributed transmission line analogy to the conductive channel of field effect devices. Within the limitations of the gradual channel approximation, a general analysis is presented which is applicable to both junction and MOS field effect devices. Equivalent circuits are obtained which describe field effect device characteristics in the region below saturation as well as in the current saturation region. Effects of parasitic elements on the terminal y parameters in practical devices are considered. Specific device models are considered for junction devices and MOS devices and the more important equivalent circuit parameters are evaluated in terms of the dc terminal voltages.     

Overcoming limitations of lumped MOS models

Describes, at a fundamental level, limitations of the lumped approach to model the transient fast signal (or RF) behavior of MOS devices. Specifically, we analyzed the transient behavior of the relaxation time lumped model. We discussed the pros and cons of a distributed approach as a more accurate (but computationally less efficient) alternative to a lumped model. In the process, we hope to have provided a deeper understanding of the strengths and weaknesses of the MOS transient models for RF applications     

Power M.O.S. devices

In this paper, the major structures and electric properties of the relatively new power MOSFETs are presented. The basic concepts are dealt with first, with a view to increasing the current and voltage capabilities in M.O.S. transistors; and then the way in which they are applied to the so far most promising power structures i.e. V.MOS and VD.MOS transistors, is shown.The electric properties of these devices are then described i.e. threshold voltage, voltage current characteristics: ohmic, saturation and quasi-saturation ranges, first and second breakdown, safe operating area. Some dynamic behavior aspects are also considered. To conclude, one of the fundamental limitations of power MOSFETs is analyzed i.e. the on-state resistance vs. voltage handling capability trade-off and some data for comparison with other power devices is also provided.     

Device mismatch and tradeoffs in the design of analog circuits

Random device mismatch plays an important role in the design of accurate analog circuits. Models for the matching of MOS and bipolar devices from open literature show that matching improves with increasing device area. As a result, accuracy requirements impose a minimal device area and this paper explores the impact of this constraint on the performance of general analog circuits. It results in a fixed bandwidth-accuracy-power tradeoff which is set by technology constants. This tradeoff is independent of bias point for bipolar circuits whereas for MOS circuits some bias point optimizations are possible. The performance limitations imposed by matching are compared to the limits imposed by thermal noise. For MOS circuits the power constraints due to matching are several orders of magnitude higher than for thermal noise. For the bipolar case the constraints due to noise and matching are of comparable order of magnitude. The impact of technology scaling on the conclusions of this work are briefly explored.     

Limitations in microelectronics — II. Bipolar technology

The physical phenomena which will ultimately limit miniaturization of planar bipolar integrated circuits are examined. The maximum packing density is obtained by minimizing the supply voltage and the size of the devices. The minimum transistor size is determined by junction breakdown, punch through and doping fluctuations. For circuits that are fully active the maximum number of circuit functions per chip is determined by power dissipation. The packing density of read-only memories becomes limited by the area occupied by devices and interconnections. The limitations of MOS and bipolar technologies are compared. It is concluded that read-only memories will reach approximately the same performance and packing density with MOS and bipolar technologies, while fully active circuits will reach the highest levels of integration with dynamic MOS or complementary MOS technologies.     

MOS器件的ESD失效

静电放电(ESD)对半导体器件,尤其是金属氧化物半导体(MOS)器件的影响日趋凸显,而相关的研究也是备受关注.综述了静电放电机理和3种常用的放电模型,遭受ESD应力后的MOS器件失效机理,MOS器件的两种失效模式;总结了ESD潜在性失效灵敏表征参量及检测方法;并提出了相应的静电防护措施.     

纳米MOS器件中的超浅结和相关离子掺杂新技术的发展

MOS器件特征尺寸进入纳米领域时如何形成超浅结是一个重要的挑战。文中讨论了纳米 MOS器件对超浅结离子束掺杂技术的特殊要求以及发展超浅结的主要途径 ,介绍了目前超浅结离子掺杂新技术的最新发展 ,并对其前景进行了展望。     

Hydrogen-induced surface space-charge regions in oxide-protected silicon

This paper presents data on the effects of hydrogen heat treatments on oxide-protected silicon. The test vehicle is a metal-oxide-semiconductor (MOS) transistor with its metal gate electrode not yet attached. The device was exposed to a hydrogen-containing atmosphere for various times and temperatures, and the resultant channel resistances were monitored. These resistances were then normalized to sheet resistivities. The experimental techniques and some of the problems encountered are discussed, as well as early application of the data to MOS and bipolar devices.     

Numerical analysis of MOS magnetic field sensors

A new method of numerical analysis of MOS magnetic field sensors is described, which is based on a lumped discrete approach and the application of a general-purpose circuit-analysis program. The channel region of the device is represented by a network of identical L-type circuit cells. A cell consists exclusively of conventional MOS devices, independent voltage sources and controlled current sources, while the magnetic field appears as a parameter in some of these devices. The method allows for an accurate two-dimensional numerical analysis of MOS sensors, including effects which have been neglected hitherto, such as transverse current flow and nonuniform charge density across the channel. Numerical results are given for conventional MOS plates, split-drain MOS devices and distributed current source biased MOS Hall plates.     

MOS器件及电路的总剂量辐射效应测试技术

介绍了半导体器件与电路的总剂量辐射效应及其测试技术,主要分析了MOS器件的效应机理、总剂量效应试验模拟源以及各种模拟源辐射环境的测量方法,最后给出了部分实验结果,并对其进行了讨论。     

Screening methods and experience with MOS memory

This paper describes the experience of Bell-Northern Research and Northern Telecom Ltd. with MOS dynamic RAMS in high reliability switching systems. Various failure mechanisms of the MOS memory devices and the screening procedures, implemented in Northern Telecom Ltd. to weed out weak devices, are explained. The resultant device drop-out rates in manufacturing and the effect of this comprehensive pre-conditioning on the field failure rate of MOS memory cards are discussed.     

Sub-threshold leakage currents in weakly inverted short channel IGFETS

This paper attempts to develop a comprehensive device model suitable for computer aided design, in the sub-threshold mode of operation, for short-channel insulated-gate field-effect transistors (IGFETs). It is shown that, for state-of-the art MOS LSI, employing 4–6 μ channel length devices, the sub-threshold conduction current is influenced by the longitudinal electric field to a significant degree. The device model is found to be in close agreement with experimental data. The limitations of this model for very short channel IGFETs is briefly discussed.     

Analog CMOS building blocks for custom and semicustom applications

Standard analog building blocks developed for use in custom and semicustom LSI and VLSI designs are described. The analog blocks are built using a digital CMOS process modified to include high-value resistors and voltage independent capacitors. Designs for operational amplifiers, programmable voltage sources, comparators, bandgap voltage references, unit resistors, capacitors, and n-p-n devices are discussed. Performance characteristics including unity-gain bandwidth, output drive, output impedance, and common mode range are reviewed. MOS noise data, subthreshold operation, and device matching are analyzed. Layout guidelines are proposed as well as applications and limitations of the analog building blocks.     

Analog CMOS Building Blocks for Custom and Semicustom Applications

Standard analog building blocks developed for use in custom and semicustom LSI and VLSI designs are described. The analog blocks are built using a digital CMOS process modified to include high-value resistors and voltage independent capacitors. Designs for operational amplifiers, programmable voltage sources, comparators, band gap voltage references, unit resistors, capacitors, and n-p-n devices are discussed. Performance characteristics including unity-gain bandwidth, output drive, output impedance, and common mode range are reviewed. MOS noise data subthreshold operation, and device matching are analyzed. Layout guidelines are proposed as well as applications and limitations of the analog building blocks.     

Metal oxide-semiconductor capacitors on silicon carbide

The purpose of the work discussed in this paper is to determine the feasibility of using Silicon Carbide for making surface field effect devices such as MOSFET's. The device used for making such a determination is the MOS capacitor.This paper discusses briefly the oxidation of Silicon Carbide. The techniques used to make MOS capacitors are outlined, and experimental data are presented which show that it is possible to use Silicon Carbide for constructing surface field effect devices.     

Normalized differential conductance to study current conduction mechanisms in MOS structures

In this paper, the conduction mechanisms in MOS structures are investigated using Normalized Differential Conductance (NDC). It is shown that NDC can be applied successfully for the determination of conduction mechanism parameters in MOS devices.The method allows the separation of various components of conduction current and determines the permissible voltage ranges for the determination of the conduction mechanism parameters through the device.The procedure is illustrated by applying it to simulated and experimental current-voltage (I-V) characteristics. The limitations of such parameters extraction are also investigated.A qualitative favorable comparison between experimental data and simulated results is also obtained.     

Experimental characterization of power VDMOS transistors incommutation and a derived model for computer-aided design

The authors present an experimental method for the characterization of MOS power switching transistors that does not involve technological parameters that are not available to designers. The method is based on the time-domain analysis of the commutation performance of the transistor when constant current are injected into its terminals. The analysis of the time-domain waveforms and the knowledge of the internal structure of the MOS devices are sufficient for the evaluation of the transistor capacitances. It is then possible to introduce a simple large-signal model for power MOSFETs that is particularly well suited to the analysis of circuits using the MOS transistor in commutation (e.g., switching power converters or high-efficiency power amplifiers). The authors also present the model implementation in the SPICE 2 program. Comparison between results obtained experimentally and by computer simulation for several circuits confirms the accuracy of the proposed method