Subtle gate oxide defect elimination to improve the reliability of a 32M-bit SRAM product

Tiny defects may escape from in-line defect scan and pass WAT (Wafer Acceptance Test), CP (Chip Probing), FT (Final Test) and SLT (System Level Test). Chips with such kind of defects will cause reliability problem and impact revenue significantly. It is important to catch the defects and derive the prevention strategy earlier in the technology development stage. In this paper, we investigate an SRAM with tiny defects which passed in-line defect scan, WAT, CP and FT but failed in HTOL (High Temperature Operation Life) test, one of the product reliability qualification items. FA (Failure Analysis) reveals gate oxide missing defect is the root cause. The goal is to pass reliability qualification and release product into production on schedule. The failure mechanism, optimization of gate oxide process, enhancement of defect scan and testing methodology will be introduced. Experiment results show very good HTOL performance by the combination of process and testing optimization.     

应用PDCA实现湿度敏感器件的有效控制

伴随信息技术快速发展与电子产品的普及和应用,电子产品的使用寿命和可靠性越来越成为人们关注的焦点。在电子产品的制造过程中,ESD(静电放电)和MSD(湿度敏感器件)成了威胁电子产品质量的两大重要因素,直接影响产品测试的直通率和产品的可靠性。MSD器件的失效像ESD破坏一样,具有一定的隐蔽性。MSD失效在测试过程中,也不一定会表现为完全失效。在各种诱发器件失效的机制中,MSD失效在电子制造过程中占据相当高的比例。在审核多家SMT工厂过程中发现,MSD的控制远比ESD的防护要薄弱。文章从工作实践出发,探讨应用PDCA全面质量管理的思路来实现电子产品制造过程中湿度敏感器件的有效控制。     

MMIC高温工作加速寿命试验失效机理分析

采用恒定功耗高温加速的试验方法,搭建了相关的试验系统,对高温工作寿命试验(HTOL)方法在功率GaAs MMIC领域的应用进行了一些探索。试验获得了对失效机理进行分析所需的失效数,所有样品的失效都是由同一原因引起的。通过监测数据和失效样品的分析,发现存在欧姆接触退化与栅金属下沉两种失效机理,但最终引起失效的机理单一,为栅金属下沉。     

Investigation of BTI characteristics and its behavior on 10 nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack

Bias-Temperature Instability (BTI) is one of the key device reliability concerns for both digital and analog circuit operations. Features of work-function metal (WFM) for V_T modulation in 10 nm FinFET process technology results in WFM dependent BTI characteristics. Similar levels of aging degradation to those of previous 14 nm technology were observed in both DC and AC operations. As BTI-induced V_T variability is expected to increase with 3D fin dimension scaling, such variability must be accurately characterized and considered for circuit designs. This paper reports the impact of transistor- level BTI degradation on circuits by studying Ring Oscillator (RO) and SRAM. The SRAM cell stabilities in terms of SNM (Static Noise Margin) and WRM (Write Margin) were further studied through SRAM HTOL stresses by characterizing V_min shift. Robust 10 nm SRAM and product level HTOL reliability up to 500 h were demonstrated.     

VMOS—A new MOS integrated circuit technology

A new V-groove MOS integrated circuit technology (VMOS) is described. It makes use of preferential etching of silicon to define the channels of the MOS transistors. The fabrication involves either a three or four mask process and is capable of producing either silicon gate or standard metal gate transistors. The technology results in very short channel length devices using non-critical alignment tolerances. Despite the short channel length, the VMOS transistor exhibits lower output conductance and higher breakdown voltage than a standard MOS transistor.A first order theory is presented for the VMOS transistor along with measurements made on test devices of various channel lengths. Some integrated circuit applications of the technology are also presented, including an R-S fiip-flop and a 27-stage bucket brigade shift register. The advantages of the VMOS technology in such applications are discussed.     

Analysis of ESD protection structure behaviour after ageing as new approach for system level reliability of automotive power devices

ESD (electrostatic discharge) protection devices as part of the device pad circuitry of semiconductors are designed for a specific wafer technology and ESD withstanding voltage. After successful qualification they will be released for a usage in high volume products where they must ensure the ESD robustness over the complete product lifetime.All present automotive qualification standards e.g. AEC (automotive electronic council) or JEDEC do not cover the assessment of the typical drifts of the characteristic electrical ESD protection device parameters after application of device specific reliability stress tests under consideration of the target ESD stress [Automotive Electronic Council, AEC-Q100-Rev-F, 2003; Automotive Electronic Council, AEC-Q101-Rev-C, 2005; JEDEC JP-001, Foundry Process Qualification Guideline, 2002].The paper introduces a methodology to characterize ESD protection diodes after ageing by BTS (bias temperature stress) reliability tests. The used devices are partly ESD pre-stressed before application of the reliability test. The influence of the reliability stress on the ESD robustness is evaluated by using an ESD post-stress.The experimental results are presented and discussed. For ESD protection devices release targets for automotive power applications are defined.     

VMOS memory technology

VMOS technology is discussed as it applies to semiconductor memory. A 45-ns 1-kbit static RAM with a die size of 81 mil/spl times/125 mil and a cell area of 3.0 square mils is presented. The device is fabricated with the original grounded-source version of the VMOS process. Design considerations and electrical data are given for a 30-ns scaled version of the RAM with a 55 mil/spl times/80 mil die size and a 1.25-square-mil cell area. Two new VMOS process options are presented. In one option the grounded-source limitation of VMOS is removed by the addition of diffused buried layers. These buried layers can be used as dynamic RAM storage capacitors. Electrical data are presented for a VMOS dynamic RAM cell whose area is 0.36 square mils (6-/spl mu/m rules). In the third VMOS process option, an extra layer of polysilicon is added to the grounded-source process to fabricate an erasable programmable read only memory (EPROM) cell, also with a 0.36-square-mil area.     

SOI集成电路的ESD保护技术研究进展

近年来，随着SOI技术的快速发展，SOI集成电路的ESD保护已成为一个主要的可靠性设计问题。介绍了SOI ESD保护器件方面的最新进展，阐述了在SOI ESD保护器件设计和优化中出现的新问题，并进行了详细的讨论。     

Early detection and prediction of HKMG SRAM HTOL performance by WLR PBTI tests

With technologies scaling down to 28 nm and below, and HKMG (High-κ Metal Gate) process being introduced, the NMOS PBTI (Positive Bias Temperature Instability) becomes a reliability concern due to the higher pre-existing trap density in the HfO₂ film. These traps can lead to electron trapping and device parameters shifts. Degradation of Vccmin read is a dominant factor in SRAM Vccmin degradations, and PD (Pull Down) NMOS PBTI degradation dominates the Vccmin read degradation, especially at HKMG development phase because of the un-optimized HK dielectric process. This paper provides a feasible methodology to evaluate chip level HTOL (High Temperature Operation Life) performance based on device level PBTI test by studying a correlation relationship between device Vt degradation in WLR (Wafer-Level Reliability) NMOS PBTI stressed tests and SRAM Vccmin degradation in HTOL tests. The proven correlation model allows characterization of Vccmin shifts in SRAM HTOL through WLR PBTI tests at HKMG development, and therefore has significant impacts in promoting reliability test efficiency and reduces development times.     

High reliability in PHEMT MMICs with dual-etch-stop AlAs layers for high-speed RF switch applications

We have conducted a thorough investigation on the long-term process reliability for our recently developed dual-etch-stop (DES) pseudomorphic high electron mobility transistor (PHEMT) process using the on-wafer-level accelerated DC and RF biased step stress test up to 320 °C channel temperature as well as package-level three-temperature constant stress lifetest. Devices studied are 0.9-μm-gate InGaAs PHEMTs with two silicon-doped AlAs layers as gate and channel etch-stop materials. High-temperature-operating-life (HTOL) test on our single-pole-double-throw (SPDT) switch products using this DES PHEMT process has also been performed. This article describes the detailed reliability experiments and compares the reliability results of this new DES PHEMT process against the standard non-etch-stop (NES) PHEMT baseline material. Extensive statistical analyses on the DES PHEMT devices derived an activation energy E_a=1.4 eV and a mean-time-to-failure (MTTF) > 10⁷ h at 125 °C, an order of magnitude better than our baseline NES PHEMTs. This study demonstrates and discusses the excellent reliability in the DES PHEMT process for wireless communications applications.     

Failure mechanisms in advanced BCD technology during reliability qualification

During the qualification of a new Advanced Bipolar, CMOS, DMOS (A-BCD) technology some typical failure modes were observed in this SOI process. After a short introduction of the technology and its areas of application three different failure modes will be discussed. The failures initiated during HTOL test are localized with standard PEM/OBIRCH analysis techniques. Main focus will be on the physical defects at the origin of the fail and the different techniques to reveal them. The failures are observed within the Shallow Trench Isolation (STI) module of the High Voltage components and along the edge of the Medium Trench Isolation (MTI). The root causes and the possible corrective actions will be discussed when applicable.     

ESD reliability and protection schemes in SOI CMOS output buffers

The electrostatic discharge (ESD) protection capability of SOI CMOS output buffers has been studied with Human Body Model (HBM) stresses. Experimental results show that the ESD voltage sustained by SOI CMOS buffers is only about half the voltage sustained by the bulk NMOS buffers. ESD discharge current in a SOI CMOS buffer is found to be absorbed by the NMOSFET alone. Also, SOI circuits display more serious reliability problem in handling negative ESD discharge current during bi-directional stresses. Most of the methods developed for bulk technology to improve ESD performance have minimal effects on SOI. A new Through Oxide Buffer ESD protection scheme is proposed as an alternative for SOI ESD protection. In order to improve ESD reliability, ESD protection circuitries can be fabricated on the SOI substrate instead of the top silicon thin film, after selectively etching through the buried oxide. This scheme also allows ESD protection strategies developed for bulk technology to be directly transferred to SOI substrate.<>     

电子产品中的静电防护

介绍了静电的产生机理,静电放电的危害,指出了电子产品生产过程中静电防护的重要性和必要性.并结合电子企业生产实际,对电子产品生产过程中常见的静电防护问题进行了探讨,提出了提高电子产品可靠性的具体措施.     

一种多电源域专用数字电路的静电失效分析及提升研究

在静电放电(ESD)能力考核时,一种多电源域专用数字电路在人体模型(HBM)1 700 V时失效。通过HBM测试、激光束电阻异常侦测(OBIRCH)失效分析方法,定位出静电试验后失效位置。根据失效分析结果并结合理论分析,失效是静电二极管的反向静电能力弱所致。利用晶体管替换静电二极管,并对OUT2端口的内部进行静电版图优化设计。改版后,该电路的ESD防护能力达2 500 V以上。该项研究结果对于多电源域专用数字电路的ESD失效分析及能力提升具有参考价值。     

Determination of potential at the beveled interface between two materials

A numerical method is described to compute the electrostatic potential at the beveled interface between two different materials by solving the two-dimensional Poisson's equation. The bevel angles are discretized in such a manner that an exact expression for the normal component of the electric field can be used. Curved interfaces can be treated. This method has been employed to calculate the potential distribution in a power VMOS device.     

基于人体起电实验外推超低电压研究

随着电子工业技术的飞速发展,电子产品静电放电(electrostatic discharge,ESD)敏感度电压已经低于人体模型(human body model,HBM)电压50 V,然而现有防静电工作区(electrostatic discharge protected area,EPA)配置要求标准只是针对于ES...     

VMOS: high speed TTL compatible MOS logic

VMOS is a new v-groove n-channel MOS logic structure well suited for 5-V high-speed random logic. Compared to a typical gold-doped TTL medium-scale integrated (MSI) circuit, an experimental pin for pin equivalent VMOS circuit is 20 percent faster, four times smaller in area, and six times lower in power dissipation. On-chip VMOS delays are in the 2-3 ns range; off-chip drive capability exceeds 50 MHz with 6 TTL unit loads.     

VMOS ROM

A new v-groove MOS (VMOS) read-only memory (ROM) is presented. The static 16-kbit ROM operates from a single 5-V supply, features typical and worst case access times of 160 ns and 200 ns, respectively, and has a die size of 120/spl times/140 mil/SUP 2/ using 6-/spl mu/m design rules. The purposes for fabricating the VMOS ROM are to demonstrate the large-scale integration (LSI) yield feasibility of the VMOS process, and to provide a vehicle for widely varying circuit and process experiments. It is estimated on the basis of experimental data that two new VMOS process techniques, called `linear' and `self-aligned' VMOS, will reduce the 16-kbit ROM die size to 100/spl times/120 mil/SUP 2/ (6-/spl mu/m rules).     

Failure mechanisms of discrete protection device subjected to repetitive electrostatic discharges (ESD)

High reliability electronic devices need to sustain thousands of electrostatic discharge (ESD) stresses during their lifetime. In this paper, it is demonstrated that repetitive ESD stresses on a protection device such as a bidirectional diode induce progressive defects into the silicon bulk. With “Sirtl etch” failure analysis technique, the defects could be localized quite precisely at the peripheral in/out junctions. The degradation mechanisms during repetitive IEC 61000-4-2 pulses have been investigated on a protection diode with the objective of improving the design for sustaining 1000 pulses at 10 kV level.     

Building in reliability with latch-up, ESD and hot carrier effects on 0.25 μm CMOS technology

In this study, three major reliability aspects, hot carrier effects, latch-up and electrostatic discharge (ESD) have been simultaneously studied on a 0.25 μm complementary metal-oxide silicon (CMOS) technology. For this purpose, three source–drain architectures large angle tilted implementation drain (LATID, MDD, Abrupt) processed on different kinds of substrate (bulk and epitaxial ones) are compared with respect to these three reliability aspects. This work clearly demonstrates the dependence existing between them. The source–drain architecture affects, of course, the hot carrier reliability but also the ESD performances. A thinner epitaxial substrate is effective in reducing latch-up occurrences, but degrades the ESD failure threshold. Consequently, global technology optimisation will be a trade off between these various reliability aspects.