iPad2的不足

苹果iPad 2拥有超薄的外观,最新的iOS 4.3操作系统,强大的A5芯片,快速的CPU和GPU速度,具创新性的应用程序,如GarageBand和iMovie等.iPad 2总体来看是很完美.     

iPad2的不足

<正>苹果iPad 2拥有超薄的外观,最新的iOS 4.3操作系统,强大的A5芯片,快速的CPU和GPU速度,具创新性的应用程序,如GarageBand和iMovie等。iPad 2总体来看是很完美。但iPad 2前后配备的双摄像头品质都不令人满意,i-     

计算机辅助测试性设计中的测试性改善最大化问题研究

基于边界扫描的计算机辅助电路板测试性设计中,面临着“设计复杂性一定时,如何权衡设计使得测试性改善最大”的问题。文章首先建立了该问题的数学描述,然后提出了求解问题的优化算法。仿真实验表明,该算法能够得到较优化的电路板测试性设计方案。     

软件的可测试性设计

软件产品开发规模的扩大和数量的增长迫切需要找到一种方法来增加软件测试的有效性。可测试性设计可以增强软件的可测试性,降低测试的强度。该文讨论了软件可测试性的特征和影响软件测试的因素,以及改进软件可测试性设计的几种方法。建议在软件开发的整个周期中融入软件的可测试性的设计。     

Testability transformation

A testability transformation is a source-to-source transformation that aims to improve the ability of a given test generation method to generate test data for the original program. We introduce testability transformation, demonstrating that it differs from traditional transformation, both theoretically and practically, while still allowing many traditional transformation rules to be applied. We illustrate the theory of testability transformation with an example application to evolutionary testing. An algorithm for flag removal is defined and results are presented from an empirical study which show how the algorithm improves both the performance of evolutionary test data generation and the adequacy level of the test data so-generated.     

Design for Testability for Complete Test Coverage

Some design-for-testability techniques, such as level-sensitive scan design, scan path, and scan/set, reduce test pattern generation of sequential circuits to that of combinational circuits by enhancing the controllability and/or observability of all the memory elements. However, even for combinational circuits, 100 percent test coverage of large-scale circuits is generally very difficult to achieve. This article presents DFT methods aimed at achieving total coverage. Two methods are compared: One, based on testability analysis, involves the addition of test points to improve testability before test pattern generation. The other method employs a test pattern generation algorithm (the FAN algorithm). Results show that 100 percent coverage within the allowed limits is difficult with the former approach. The latter, however, enables us to generate a test pattern for any detectable fault within the allowed time limits, and 100 percent test coverage is possible.     

Designing CMOS Circuits for Switch-Level Testability

Conventional testing techniques often fail to be effective for CMOS combinational circuits, since most of their switch-level faults cannot be detected by stuck-at-fault testing. The alternative is to design for testability. The design techniques presented here for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-on switch-level faults. The circuit is implemented with specially designed gates that have no undetectable stuck-on faults. An inverting buffer is inserted between logic gates, and two FETs are added to each logic gate to make it testable for stuck-on faults.     

基于微处理器的可测性设计

由于微处理器结构复杂，测试困难，作者在微处理器设计中插入内建自测试（BIST）电路，对指令译码部件的可编程逻辑阵列（PLA）电路和执行部件的控制只读存储器（CROM）电路进行测试。模拟结果表明，微处理器可分别在测试模式与正常工作模式下运行。在测试模式下，微处理器芯片中近40％的晶体管可用自检办法解法。     

机载计算机的可测试性工程设计（DFT）

安装在飞机上的嵌处式计算机,称为机载计算机,它的可测试性设计是整个设计中的非常重要的方面,设计要求在每次飞行前,机载计算机地测试,确定机载设备的完好性;在空中飞行中,需要对计算机进行实时测试,以确保计算机运行的正确性。当测试发现故障时,应立刻告警或进行应急处理。本在介绍机载计算机的可测试性设计原理和测试分类的基础上,提出了在不同的测试级别上的可测试性工程设计技术。     

8位RISC_CPU可测性设计

本文介绍了一款RISC_CPU的可测性设计,为了提高芯片的可测性,采用了扫描设计和存储器内建自测试,这些技术的使用为该芯片提供了方便可靠的测试方案.     

Design for Testability for Highly Reconfigurable Component-Based Systems

Highly-reconfigurable component-based systems, i.e., systems that are built form existing components and are distributed in many versions and configurations, are becoming increasingly popular.The design and verification of such systems presents new challenges. In this paper we propose a design approach that facilitates analysis and testing of different configurations by identifying and tracking relations among requirements, logic components and resources. The approach proposed in the paper allows for easily identifying different dependencies among resources, components and requirements and thus spotting the tests that must be re-executed to assure the desired level of quality.     

Testing Logic Networks and Designing for Testability

VLSI has brought exciting increases in circuit density and performance capability. But it has also aggravated the problem of chip, component and system testing. Here are some approaches to dealing with that problem.     

装备测试性试验与评价的综合设计

在讨论测试性试验与评价分类、测试性试验与评价方法适用性的基础上,结合飞机研制工程实际,提出了综合考虑产品层级、综合利用各种技术、综合考虑研制与鉴定的试验与评价方案。     

软件测试性度量框架研究

针对当前软件测试性度量框架适用范围有限、无法扩展的问题,提出一个新的度量框架。分析软件测试性概念,使用层次分析法得到新的框架结构。总结框架扩展方法,将测试性特性和影响因素加入到框架以进行软件测试性度量。其稳定性保证了框架对任何软件都具有相同的测试性度量过程和计算方法,可扩展性使得框架能随着软件技术的发展不断完善,两者为框架的通用性提供了保证。     

一种电子系统测试性模型的研究

测试性是系统和设备的一种便于测试和诊断的重要设计特性,对现代的航空电子设备、武器装备等复杂系统的维护性、可靠性和可用性有很大影响。在对测试性建模理论进行研究的基础上,借鉴多信号流图模型和eXpress信息模型,提出了一种适合电子系统的测试性模型——ESTIM(electrotic system testability information model)模型,该模型在表示方法上与EDA软件相兼容,可结合功能相关性和故障模式相关性方便地对电子系统进行测试性分析。     

武器装备纵向测试性研究

针对测试性工程中的纵向测试性和纵向测试兼容性问题进行研究。分析了测试兼容性设计的重要作用;深入研究了武器装备研制、生产和使用各个阶段中维修体制的确定与级别划分、测试容差、测试数据接口、被测对象与测试设备接口等工程环节的兼容性设计要求,纵向测试性设计要求保证了武器装备全寿命周期测试诊断的一致性和兼容性,该研究对提高武器装备的测试性水平和实现武器装备一体化测试,具有重要意义。     

Testability Analysis at Switch Level for CMOS Circuits

In this paper we propose a controllability and observability measure at switch level for CMOS circuits based on the cost analysis approach.The complexityof the algorithm is nearly linear.