Power Consumption of Asymptotically Adiabatic Static Logic Gates

A computer simulation is conducted of power consumption in the 1n–1p type of asymptotically adiabatic static logic gate. The increase is estimated in dissipation due to violation of any single condition of thermodynamic reversibility. The dissipation characteristics obtained are compared with those of quasi-adiabatic gates of the 2n–2n2p and the efficient charge-recovery logic (ECRL) type.     

New All-nMOS Quasi-adiabatic Dynamic Logic

A new type of quasi-adiabatic dynamic MOS logic is proposed, which uses only n-channel FETs. With this approach, an N-input logic gate has N + 2 devices. The term quasi-adiabatic means that most of the energy delivered to the load capacitor returns to the power supply. The gates can be powered with two- or three-phase twin clock pulses. Dissipation limits are estimated. A P-SPICE simulation is presented.     

Pulse Noise Immunity in Saturated Logic Gates

This paper develops techniques for assessing the inherent pulse noise immunity of saturated logic gates, with a view towards determining their ability to operate reliably in a pulse noise environment. A test method has been outlined for specifying and measuring this noise immunity. Although this method is applicable to all forms of saturated logic, the low level T /sup 2/ L gate has been singled out for experiment because of its high speed capability. Using both discrete component and microcircuit gates of this type, close correlation was obtained between experimental results and calculations based on internal parameters of the individual devices.     

门电路构成的多谐振荡器的仿真方法

给出了用于仿真的门电路多谐振荡器的实际电路结构，在发现直接应用OrCAD Capture提供的门电路模型，对门电路多谐振荡器进行仿真失败的前提下，提出了创建由子电路模型构成新元件，然后对电路进行仿真的方法。实际的仿真结果表明该方法正确，应用效果良好，这一方法可以解决含门电路多谐振荡器电路的仿真问题，并对其他复杂电路的仿真具有重要参考价值。     

量子逻辑门核磁共振实验的仿真实现

利用核磁共振(NMR)实验技术来实现量子计算，是当前各种验证量子算法最为有效的方法之一。对如何设计核磁共振(NMR)脉冲序列来实现各种量子逻辑门，如量子控非门、toffoli门等进行了研究。并在量子仿真器(QCE)上进行实验验证。     

忆阻器实现逻辑门的方法研究

在分析忆阻器特性及相关文献的基础上提出了一种只使用忆阻器元件实现基本逻辑门的电路方案,理论分析及Spice仿真实验结果证实了方案的可行性．所设计的逻辑门电路简单,实现的逻辑门无需时序操作就能工作,其在电路尺寸、集成密度、电路功耗等方面拥有很大的优势．     

SoC设计中的低功耗逻辑综合策略

介绍了一种SoC(片上系统)电路的高效逻辑综合方法,用工具对功耗关键模块插入时钟门控单元来降低功耗,并用工具提取不带时钟门控模块的约束条件来优化相应带门控的模块,使SoC在最高主频率、面积和功耗等方面达到最优,且时序收敛较快.采用该方法对Unity805plus SoC芯片进行综合,取得比自顶向下、自底向上等传统综合方法更好的效果,在最差情况下最高频率为200 MHz,面积为8 773 410μm2,功耗为724.920 4 mW.在ULTRA60上运行时间为14h.[关键词:逻辑综合,SoC,时序收敛     

Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates

Decreased power supply levels have reduced the tolerance to voltage changes within power distribution networks in CMOS integrated circuits. High on-chip currents, required to charge and discharge large on-chip loads while operating at high frequencies, produce significant transient IR voltage drops within a power distribution network. These transient IR voltage drops can affect the propagation delay of a CMOS logic gate, creating delay uncertainty within data paths. Analytical expressions characterizing these transient IR voltage drops are presented in this paper. The peak value of these transient IR voltage drops is within 6% as compared to SPICE. Circuit- and layout-level design constraints are also discussed to manage the peak value of the transient IR voltage drops. The propagation delay of a CMOS logic gate based on these analytical expressions is within 5% of SPICE while the estimate without considering transient IR voltage drops can exceed 20% for a 20 power line.     

Reliability of Power Gaas FET's-Au Gates and Al-Au Linked Gates

An investigation of the reliability of two types of commercial microwave power GaAs FET's has been carried out. Mean-time-to-failure data for a device mounted face-up with Al gates but without an Al-Au couple is presented and similar data for a "flip-chip" mounted Au-refractory gate device is reviewed. The failure mechanisms for both devices are described.     

Quasi-adiabatic ternary CMOS logic

Adiabatic switching is one technique for designing low power ICs. To diminish its expensive silicon area requirements a quasi-adiabatic ternary logic is proposed. The performances of a half adder using this logic have been obtained, showing a 65% area saving with respect to adiabatic binary logic     

含逻辑门的雷达组网作战效能评估研究

为了充分考虑雷达组网系统中若干子层重要指标对整体效能的影响,更加贴切地反映装备的真实效能,将逻辑门的思想应用到雷达组网作战效能指标的聚合中,构建了基于逻辑门的雷达组网作战效能评估指标层次体系;并应用模糊综合评价法,对系统中主要指标进行评估,解决了类似于一票否决式指标对雷达组网系统整体效能的影响问题,为合理评价该系统效能提供了一种方法。     

Fault Diagnosis in Lab-on-Chip Using Digital Microfluidic Logic Gates

Fault diagnosis is needed for a lab-on-chip to facilitate defect tolerance using reconfiguration. Previously proposed techniques for reading test outcomes and for pulse-sequence analysis are cumbersome and error-prone. We present a fault-diagnosis method to locate a single defective cell and multiple rows/columns with defective cells in a digital microfluidic array. The proposed method can also locate an unknown number of rows/columns-under-test with defective cells. It utilizes digital microfluidic exclusive-or gates to implement an output compactor. The microfluidic compactor can compress 2 ^r distinct test outcomes to a r-droplet signature. This approach obviates the need for capacitive sensing test-outcome circuits for analysis. We analyze the probability of misdiagnosis and use the compression ratio as a measure to evaluate the proposed fault-diagnosis method.     

Dual-Modulus Prescaler Based on Transmission Gates and Pseudo-PMOS Logic

The Dual Modulus Prescaler is a critical block in CMOS systems like high speed frequency synthesizers. The design of high divide-by-value, high speed and low power dual modulus prescaler, however, remains a design challenge. In order to face the challenge, this paper introduces an idea of using transmission gates and pseudo-PMOS logic in realization of the dual modulus prescaler. The topology of the prescaler proposed in this paper is different from the prior designs primarily in two ways: (i) it uses transmission gates in the critical path and (ii) the D-flip flops used in the synchronous counter are comprised of pseudo-PMOS invertors and ratioed latches. A design of the pseudo-PMOS logic based DFF is introduced and used in the proposed prescaler design. Based on the proposed topology, a dual-modulus divide-by-127/128 prescaler is implemented in 0.35 m CMOS technology. Its maximum operating frequency is observed as 2.4 GHz. It consumes 4.8 mW power from a 3 V supply. Circuit operations and measurement results are provided. The silicon estate required is only 0.06 mm². There is no flip flop and logic gate in the critical path. The proposed topology is suitable firstly for the high speed and high divide-by-value prescaler designs. Secondly, it reduces: (i) design complexity, (ii) power consumption and (iii) load to preceding circuit.     

Implementation of Multi-Valued Logic Gates Using Full Current-Mode CMOS Circuits

In this paper, a novel multi-valued logic gate set is designed by using only current-mode CMOS circuits. The gate set consists of min, max, inverter, literal, and cyclic operators based on a current-mode, versatile, novel threshold topology. They are shown to exhibit better static and dynamic behavior and consume less area compared to previous MVL design topologies and binary-logic counterparts. The gate circuits are investigated in terms of analog design aspects, such as mismatch and noise. The proposed topology is compared to previous topologies in terms of attainable radix and DC characteristics. A radix-8 multiplex function and a radix-8 full-adder circuit is designed to demonstrate the advantages of new current-mode multi-valued logic circuits.     

基于差分传输管预充电逻辑的功耗恒定性电路改进设计

通过分析差分传输管预充电逻辑(DP2L)的电路结构,发现该电路还无法达到完全的功耗恒定特性,仍然存在被功耗攻击的风险.针对该问题,该文对DP2L的电路结构进行改进,并用Hspice对改进前后的电路进行模拟仿真测试.实验表明:改进后的DP2L电路结构具有更好的功耗恒定特性,更能满足该逻辑电路的设计要求.     

SOA-Based Ultrafast Multifunctional All-Optical Logic Gates With PolSK Modulated Signals

In this paper, we propose a novel scheme for ultrafast multifunctional all-optical logic gates, which can achieve not only simple logic gates including AND, NOR, $ {S_{1}}{bar S_{2}} $, $ {bar S_{1}}{S_{2}} $, XNOR, and XOR but also complex logic gates including half adder, half subtracter, decoder, and comparer based on four-wave mixing in semiconductor optical amplifiers (SOAs) with polarization-shift-keying (PolSK) modulated signals. A comprehensive polarization-dependent broadband dynamic model of this kind of ultrafast multifunctional all-optical logic gates is presented. By numerical simulation, the multifunctional all-optical logic gates are theoretically realized at 40 Gbit/s. The effects of two input signal powers, injected current, frequency detuning, and polarization dependence of SOA on the output performance of the multifunctional all-optical logic gates are theoretically investigated in detail. The results indicate that this scheme is free of pattern effect due to using the PolSK modulation format. Moreover, the nice eye opening of the logic gates indicates the good performance of the proposed ultrafast multifunctional all-optical logic gates. This scheme is potential for applications in future high bit rate optical networks.      

基于RM型三变量通用逻辑门的查表设计

本文讨论了逻辑函数的RM展开与分类，给出了基于逻辑函数RM展开的三变量函数P分类表、接线顺序表以及P分类代表函数的接线方案。在此基础上提出了基于RM型三变量通用逻辑门的查表设计方法，并给出了具体设计实例。     

Multichannel Carbon-Nanotube FETs and Complementary Logic Gates With Nanowelded Contacts

A high-performance multichannel carbon-nanotube field-effect transistor (MC-CNTFET) has been built by applying an array of parallel nanowelded single-walled carbon nanotubes (SWCNTs) as the channels. The SWCNT channel array with good directional and spatial control was obtained by the ac electric-field alignment of SWCNTs on a specially designed electrode. An ultrasonic nanowelding technique was utilized to achieve the reliable and highly transparent contacts between SWCNT channels and electrodes. Both p- and n-MC-CNTFETs fabricated exhibit high performance. Key transistor performance parameters, transconductance and carrier mobility reach 50.2$muhboxS$and 7160$hboxcm^2cdothboxV^-1cdothboxs^-1$for p-MC-CNTFETs, and 36.5$muhboxS$and 5311$hboxcm^2cdothboxV^-1cdothboxs^-1$for n-MC-CNTFETs, respectively. Using the authors' techniques, complementary inverters with a high gain of up to 31.2 have also been demonstrated.     

Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization

Logic gates as repeaters (LGRs)-a methodology for delay optimization of CMOS logic circuits with resistance-capacitance (RC) interconnects is described. The traditional interconnect segmentation by insertion of repeaters is generalized to segmentation by distributing logic gates over interconnect lines, reducing the number of additional, logically useless inverters. Expressions for optimal segment lengths and gate scaling are derived. Considerations are presented for integrating LGR into a VLSI design flow in conjunction with related methods. Several logic circuits have been implemented, optimized and verified by LGR. Analytical and simulation results were obtained, showing significant improvement in performance in comparison with traditional repeater insertion, while maintaining low complexity and small area     

三种低压高速低耗BiCMOS三态逻辑门

采用0.35μm B iCM O S工艺技术,设计了三种高性能的B iCM O S三态逻辑门电路,并提出了改进三态门电路结构和优化器件参数的方法和措施。仿真和实验结果表明,所优化设计的B iCM O S三态门的电源电压均小于3.3 V,工作速度比常用的CM O S三态门快约5倍,功耗在60 MH z下仅高出约2.2~3.7 mW,而延迟-功耗积却比该常用的CM O S三态门平均降低了38.1%,因此它们特别适用于低压、高速、低功耗的数字系统。