Power Consumption of Asymptotically Adiabatic Static Logic Gates

A computer simulation is conducted of power consumption in the 1n–1p type of asymptotically adiabatic static logic gate. The increase is estimated in dissipation due to violation of any single condition of thermodynamic reversibility. The dissipation characteristics obtained are compared with those of quasi-adiabatic gates of the 2n–2n2p and the efficient charge-recovery logic (ECRL) type.     

New All-nMOS Quasi-adiabatic Dynamic Logic

A new type of quasi-adiabatic dynamic MOS logic is proposed, which uses only n-channel FETs. With this approach, an N-input logic gate has N + 2 devices. The term quasi-adiabatic means that most of the energy delivered to the load capacitor returns to the power supply. The gates can be powered with two- or three-phase twin clock pulses. Dissipation limits are estimated. A P-SPICE simulation is presented.     

门控逻辑信号的非易失性数字电位计

本设计实例描述了一个非易失性门控功能的简单替代方案,通常实现门控功能要使用PAL(可编程逻辑阵列)、GAL(门阵列逻辑)或CPLD(复杂可编程逻辑器件).     

基于常规逻辑门和原理图方式的可逆逻辑描述

针对可逆逻辑综合在设计较大规模可逆逻辑电路(ALU)时遇到的瓶颈问题。文中借用现行EDA技术的逻辑描述和验证能力,可逆逻辑门的功能表达式为依据,设计具有等功能的常规逻辑组合电路,通过等功能代换的方法,设计实现以常规原理图方式描述的可逆ALU。仿真图中显示的16种运算结果表明,该方法具有一定的可行性和有效性。     

门电路构成的多谐振荡器的仿真方法

给出了用于仿真的门电路多谐振荡器的实际电路结构，在发现直接应用OrCAD Capture提供的门电路模型，对门电路多谐振荡器进行仿真失败的前提下，提出了创建由子电路模型构成新元件，然后对电路进行仿真的方法。实际的仿真结果表明该方法正确，应用效果良好，这一方法可以解决含门电路多谐振荡器电路的仿真问题，并对其他复杂电路的仿真具有重要参考价值。     

Pulse Noise Immunity in Saturated Logic Gates

This paper develops techniques for assessing the inherent pulse noise immunity of saturated logic gates, with a view towards determining their ability to operate reliably in a pulse noise environment. A test method has been outlined for specifying and measuring this noise immunity. Although this method is applicable to all forms of saturated logic, the low level T /sup 2/ L gate has been singled out for experiment because of its high speed capability. Using both discrete component and microcircuit gates of this type, close correlation was obtained between experimental results and calculations based on internal parameters of the individual devices.     

忆阻器实现逻辑门的方法研究

在分析忆阻器特性及相关文献的基础上提出了一种只使用忆阻器元件实现基本逻辑门的电路方案,理论分析及Spice仿真实验结果证实了方案的可行性．所设计的逻辑门电路简单,实现的逻辑门无需时序操作就能工作,其在电路尺寸、集成密度、电路功耗等方面拥有很大的优势．     

量子逻辑门核磁共振实验的仿真实现

利用核磁共振(NMR)实验技术来实现量子计算，是当前各种验证量子算法最为有效的方法之一。对如何设计核磁共振(NMR)脉冲序列来实现各种量子逻辑门，如量子控非门、toffoli门等进行了研究。并在量子仿真器(QCE)上进行实验验证。     

电路抗老化设计中基于门优先的关键门定位方法

随着CMOS工艺尺寸不断缩小,尤其在65 nm及以下的CMOS工艺中,负偏置温度不稳定性(NBTI)已经成为影响CMOS器件可靠性的关键因素。提出了一种基于门优先的关键门定位方法,它基于NBTI的静态时序分析框架,以电路中老化严重的路径集合内的逻辑门为优先,同时考虑了门与路径间的相关性,以共同定位关键门。在45 nm CMOS工艺下对ISCAS基准电路进行实验,结果表明:与同类方法比较,在相同实验环境的条件下,该方法不仅定位关键门的数量更少,而且对关键路径的时延改善率更高,有效地减少了设计开销。     

SoC设计中的低功耗逻辑综合策略

介绍了一种SoC(片上系统)电路的高效逻辑综合方法,用工具对功耗关键模块插入时钟门控单元来降低功耗,并用工具提取不带时钟门控模块的约束条件来优化相应带门控的模块,使SoC在最高主频率、面积和功耗等方面达到最优,且时序收敛较快.采用该方法对Unity805plus SoC芯片进行综合,取得比自顶向下、自底向上等传统综合方法更好的效果,在最差情况下最高频率为200 MHz,面积为8 773 410μm2,功耗为724.920 4 mW.在ULTRA60上运行时间为14h.[关键词:逻辑综合,SoC,时序收敛     

Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates

Decreased power supply levels have reduced the tolerance to voltage changes within power distribution networks in CMOS integrated circuits. High on-chip currents, required to charge and discharge large on-chip loads while operating at high frequencies, produce significant transient IR voltage drops within a power distribution network. These transient IR voltage drops can affect the propagation delay of a CMOS logic gate, creating delay uncertainty within data paths. Analytical expressions characterizing these transient IR voltage drops are presented in this paper. The peak value of these transient IR voltage drops is within 6% as compared to SPICE. Circuit- and layout-level design constraints are also discussed to manage the peak value of the transient IR voltage drops. The propagation delay of a CMOS logic gate based on these analytical expressions is within 5% of SPICE while the estimate without considering transient IR voltage drops can exceed 20% for a 20 power line.     

Reliability of Power Gaas FET's-Au Gates and Al-Au Linked Gates

An investigation of the reliability of two types of commercial microwave power GaAs FET's has been carried out. Mean-time-to-failure data for a device mounted face-up with Al gates but without an Al-Au couple is presented and similar data for a "flip-chip" mounted Au-refractory gate device is reviewed. The failure mechanisms for both devices are described.     

Quasi-adiabatic ternary CMOS logic

Adiabatic switching is one technique for designing low power ICs. To diminish its expensive silicon area requirements a quasi-adiabatic ternary logic is proposed. The performances of a half adder using this logic have been obtained, showing a 65% area saving with respect to adiabatic binary logic     

量子逻辑门中的编码量子位研究

本文提出在量子编码中用量子字节控制量子字节的设想,具体分析了字节被控编码法防止或纠正逻辑运算错误的量子线路,该编码既适用于量子逻辑门的防错和纠错,也适用于防止量子计算机存储单元的解相干。该编码法量子位使用效率为５０％,且防错和纠错过程简单明了,并有单个逻辑双态双轨技术提供实验基础,因此该方案实现的可能性大。     

含逻辑门的雷达组网作战效能评估研究

为了充分考虑雷达组网系统中若干子层重要指标对整体效能的影响,更加贴切地反映装备的真实效能,将"逻辑门"的思想应用到雷达组网作战效能指标的聚合中,构建了基于"逻辑门"的雷达组网作战效能评估指标层次体系;并应用模糊综合评价法,对系统中主要指标进行评估,解决了类似于"一票否决"式指标对雷达组网系统整体效能的影响问题,为合理评价该系统效能提供了一种方法。     

Solid-State Homojunction Electrochemical Transistors and Logic Gates on Plastic

Organic electrochemical transistors (OECTs) have attracted significant attention due to their unique ionic–electronic charge coupling, which holds promise for use in a variety of bioelectronics. However, the typical electronic components of OECTs, such as the rigid metal electrodes and aqueous electrolytes, have limited their application in solid-state bioelectronics that requires design flexibility and a variety of form factors. Here, the fabrication of a solid-state homojunction OECT consisting of a pristine polymer semiconductor channel, doped polymer semiconductor electrodes, and a solid electrolyte is demonstrated. This structure combines the photo-crosslinking of all of the electronic OECT components with the selective doping of the polymer semiconductor. Three Lewis acids (gold (III) chloride (AuCl₃), iron (III) chloride (FeCl₃), and copper (II) chloride (CuCl₂) ) are utilized as dopants for the metallization of the polymer semiconductor. The AuCl₃-doped polymer semiconductor with an electrical conductivity of ≈100 S cm⁻¹ is successfully employed as the source, drain, and gate electrodes for the OECT, which exhibited a high carrier mobility of 3.4 cm² V⁻¹ s⁻¹ and excellent mechanical stability, with negligible degradation in device performance after 5000 cycles of folding at a radius of 0.1 mm. Homojunction OECTs are then successfully assembled to produce NOT, NAND, and NOR logic gates.     

Dual-Modulus Prescaler Based on Transmission Gates and Pseudo-PMOS Logic

The Dual Modulus Prescaler is a critical block in CMOS systems like high speed frequency synthesizers. The design of high divide-by-value, high speed and low power dual modulus prescaler, however, remains a design challenge. In order to face the challenge, this paper introduces an idea of using transmission gates and pseudo-PMOS logic in realization of the dual modulus prescaler. The topology of the prescaler proposed in this paper is different from the prior designs primarily in two ways: (i) it uses transmission gates in the critical path and (ii) the D-flip flops used in the synchronous counter are comprised of pseudo-PMOS invertors and ratioed latches. A design of the pseudo-PMOS logic based DFF is introduced and used in the proposed prescaler design. Based on the proposed topology, a dual-modulus divide-by-127/128 prescaler is implemented in 0.35 m CMOS technology. Its maximum operating frequency is observed as 2.4 GHz. It consumes 4.8 mW power from a 3 V supply. Circuit operations and measurement results are provided. The silicon estate required is only 0.06 mm². There is no flip flop and logic gate in the critical path. The proposed topology is suitable firstly for the high speed and high divide-by-value prescaler designs. Secondly, it reduces: (i) design complexity, (ii) power consumption and (iii) load to preceding circuit.     

Fault Diagnosis in Lab-on-Chip Using Digital Microfluidic Logic Gates

Fault diagnosis is needed for a lab-on-chip to facilitate defect tolerance using reconfiguration. Previously proposed techniques for reading test outcomes and for pulse-sequence analysis are cumbersome and error-prone. We present a fault-diagnosis method to locate a single defective cell and multiple rows/columns with defective cells in a digital microfluidic array. The proposed method can also locate an unknown number of rows/columns-under-test with defective cells. It utilizes digital microfluidic exclusive-or gates to implement an output compactor. The microfluidic compactor can compress 2 ^r distinct test outcomes to a r-droplet signature. This approach obviates the need for capacitive sensing test-outcome circuits for analysis. We analyze the probability of misdiagnosis and use the compression ratio as a measure to evaluate the proposed fault-diagnosis method.     

基于相关性分离的逻辑电路敏感门定位算法

随着CMOS器件特征尺寸进入纳米量级,因高能粒子辐射等造成的电路失效问题日益严重,给电路可靠性带来严峻挑战。现阶段,准确评估集成电路可靠性,并以此为依据对电路进行容错加固,以提高电路系统可靠性变得刻不容缓。然而,由于逻辑电路中存在大量扇出重汇聚结构,由此引发的信号相关性导致可靠性评估与敏感单元定位面临困难。该文提出一种基于相关性分离的逻辑电路敏感门定位算法。先将电路划分为多个独立电路结构(ICS);以ICS为基本单元分析故障传播及信号相关性影响;再利用相关性分离后的电路模块和反向搜索算法精准定位逻辑电路敏感门单元;最后综合考虑面向输入向量空间的敏感门定位及针对性容错加固。实验结果表明,所提算法能准确、高效地定位逻辑电路敏感单元,适用于大规模及超大规模电路的可靠性评估与高效容错设计。     

基于差分传输管预充电逻辑的功耗恒定性电路改进设计

通过分析差分传输管预充电逻辑(DP2L)的电路结构,发现该电路还无法达到完全的功耗恒定特性,仍然存在被功耗攻击的风险.针对该问题,该文对DP2L的电路结构进行改进,并用Hspice对改进前后的电路进行模拟仿真测试.实验表明:改进后的DP2L电路结构具有更好的功耗恒定特性,更能满足该逻辑电路的设计要求.