Integration of Trench-Isolated Through-Wafer Interconnects with 2D Capacitive Micromachined Ultrasonic Transducer Arrays

This paper presents a method to provide electrical connection to a 2D capacitive micromachined ultrasonic transducer (CMUT) array. The interconnects are processed after the CMUTs are fabricated on the front side of a silicon wafer. Connections to array elements are made from the back side of the substrate via highly conductive silicon pillars that result from a deep reactive ion etching (DRIE) process. Flip-chip bonding is used to integrate the CMUT array with an integrated circuit (IC) that comprises the front-end circuits for the transducer and provides mechanical support for the trench-isolated array elements. Design, fabrication process and characterization results are presented. The advantages when compared to other through-wafer interconnect techniques are discussed.     

Fabricating capacitive micromachined ultrasonic transducers with wafer-bonding technology

Introduces a new method for fabricating capacitive micromachined ultrasonic transducers (CMUTs) that uses a wafer bonding technique. The transducer membrane and cavity are defined on an SOI (silicon-on-insulator) wafer and on a prime wafer, respectively. Then, using silicon direct bonding in a vacuum environment, the two wafers are bonded together to form a transducer. This new technique, capable of fabricating large CMUTs, offers advantages over the traditionally micromachined CMUTs. First, forming a vacuum-sealed cavity is relatively easy since the wafer bonding is performed in a vacuum chamber. Second, this process enables better control over the gap height, making it possible to fabricate very small gaps (less than 0.1 /spl mu/m). Third, since the membrane is made of single crystal silicon, it is possible to predict and control the mechanical properties of the membrane to within 5%. Finally, the number of process steps involved in making a CMUT has been reduced from 22 to 15, shortening the device turn-around time. All of these advantages provide repeatable fabrication of CMUTs featuring predictable center frequency, bandwidth, and collapse voltage.     

A Capacitive Micromachined Ultrasonic Transducer Array for Minimally Invasive Medical Diagnosis

A capacitive micromachined ultrasonic transducer (CMUT) array for minimally invasive medical diagnosis has been developed. Unlike traditional ultrasonic transducers, which generally use a bulky piece of substrate, this transducer array was integrated on a 40--thick micromachined silicon substrate into a probe shape with a typical shank width of 50-80 and a shank length of 4-8 mm. For 1-D arrays, 24-96 CMUT devices were integrated on one such silicon probe and formed an accurately configured phase array. In addition to miniaturization, reduction of the substrate thickness also decreases the intertransducer crosstalk due to substrate Lamb waves. Due to its miniature size, this array can be placed or implanted close to the target tissue/organ and can perform high-resolution high-precision diagnosis and stimulation using high-frequency ultrasounds. The issue of conflict between resolution and penetration depth of ultrasonic diagnosis can therefore be resolved. A two-layer polysilicon surface micromachining process was used to fabricate this device. Suspended polysilicon membranes of diameters ranging from 20 to 90 and thicknesses from 1.0 to 2.5 were used to generate and detect ultrasounds of frequencies ranging from 1 to 10 MHz. B-mode imaging using this transducer array has been demonstrated.     

A Gap Reduction and Manufacturing Technique for Thick Oxide Mask Layers With Multiple-Size Sub-$mu$m Openings

This paper introduces a technique for the fabrication of thick oxide hard masks on top of a substrate with adjustable opening sizes in the sub-$mu$m regime, while the only lithography step involved has$mu$m-scale resolution. This thick oxide mask layer with sub-$mu$m openings is suitable for etching deep narrow trenches in silicon using deep reactive ion etching (DRIE) tools. Openings of less than 100 nm are realized in a 1.5-$mu$m-thick oxide layer, while the original lithographically defined feature sizes are larger than 1$mu$m in width. This method, combined with modified high aspect ratio DRIE recipes, shows a great potential for single-mask batch-fabrication of high frequency low-impedance single crystalline resonators on silicon-on-insulator (SOI) substrates. Dry-etched trenches with aspect ratios as high as 60:1 are fabricated in silicon using the gap reduction technique to realize 200 nm opening sizes in an oxide mask layer. Various resonator structures with sub-$mu$m capacitive gaps are also fabricated on a SOI substrate using a single-mask process. Measurement results from high-frequency and high-quality factor (Q) all single crystal silicon resonators are presented.1684     

基于BOE硅腐蚀现象的硅纳米线制作

介绍一种硅纳米线制作方法.在SOI顶层硅上制作硅纳米梁,通过离子注入形成pnp结构,利用新发现的没有特殊光照时BOE溶液腐蚀pn结n型区域现象,结合BOE溶液氧化硅腐蚀,实现硅纳米线制作.制作完全采用传统MEMS工艺,具有工艺简单,成本低,可控,可靠性好,可批量制作等优点.利用该方法制作出了厚50 nm,宽100 nm的单晶硅纳米线,制作的纳米线可用于一维纳米结构电学性能研究、谐振器研究等.     

Design of bossed silicon membranes for high sensitivity microphone applications

This paper deals with the design optimization of new high sensitivity microphones in silicon on insulator (SOI) technology for gas sensing applications. A novel geometry of bossed silicon membranes used as mechanical transducer has been studied by finite element modelling. Device fabrication is achieved from SOI substrates through deep backside anisotropic etching and shallow front side reactive ion etching to define a bossed sensing membrane with two reinforced areas. Thus, the influence of thin film stresses on the device performance is largely decreased. Polysilicon gauges are located on the reinforced areas to get a better linearity in pressure.     

Arrays of monocrystalline silicon micromirrors fabricated using CMOS compatible transfer bonding

In this paper, we present CMOS compatible fabrication of monocrystalline silicon micromirror arrays using membrane transfer bonding. To fabricate the micromirrors, a thin monocrystalline silicon device layer is transferred from a standard silicon-on-insulator (SOI) wafer to a target wafer (e.g., a CMOS wafer) using low-temperature adhesive wafer bonding. In this way, very flat, uniform and low-stress micromirror membranes made of monocrystalline silicon can be directly fabricated on top of CMOS circuits. The mirror fabrication does not contain any bond alignment between the wafers, thus, the mirror dimensions and alignment accuracies are only limited by the photolithographic steps. Micromirror arrays with 4/spl times/4 pixels and a pitch size of 16 /spl mu/m/spl times/16 /spl mu/m have been fabricated. The monocrystalline silicon micromirrors are 0.34 /spl mu/m thick and have feature sizes as small as 0.6 /spl mu/m. The distance between the addressing electrodes and the mirror membranes is 0.8 /spl mu/m. Torsional micromirror arrays are used as spatial light modulators, and have potential applications in projection display systems, pattern generators for maskless lithography systems, optical spectroscopy, and optical communication systems. In principle, the membrane transfer bonding technique can be applied for integration of CMOS circuits with any type of transducer that consists of membranes and that benefits from the use of high temperature annealed or monocrystalline materials. These types of devices include thermal infrared detectors, RF-MEMS devices, tuneable vertical cavity surface emitting lasers (VCSEL) and other optical transducers.     

The SOI DAWN process for three-dimensional silicon micromachining and its applications

A DRIE assisted wet anisotropic bulk micromachining (DAWN) process is demonstrated to fabricate various three-dimensional MEMS devices on a silicon-on-insulator (SOI) wafer. This SOI DAWN process can realize thin film structures, reinforced (thin film) structures, and thick structures with totally different mechanical characteristics. Various passive and active mechanical components, including flexible springs, rigid structures, and actuators, have been fabricated using the SOI DAWN process and have been further integrated to create MEMS devices which are flexible as well as movable in both in-plane and out-of-plane directions. This SOI DAWN process has been successfully applied to produce various multi-DOF devices made of single crystal silicon (SCS).     

Fabrication of an hermetically packaged silicon resonator on LTCC substrate

The design, fabrication and packaging process of silicon resonators capable of the integration of LSI (Large Scale Integration) have been developed on the basis of packaging technology using an LTCC (Low Temperature Co-fired Ceramic) substrate. The structures of silicon resonators are defined by deep reactive ion etching (DRIE) on a silicon on insulator (SOI) wafer and then transferred onto the LTCC substrate and hermetically sealed by anodic bonding technique. The measured resonant frequency of a micromechanical bulk acoustic mode silicon resonator after packaging at 0.02 Pa is 20.24 MHz with a quality factor of 50,600.     

Implantable multichannel electrode array based on SOI technology

This work presents a new method of fabricating implantable multielectrode arrays on lightly doped single-crystal silicon. Such arrays are essential tools for electrical stimulation and recording of nerve signals. Our new microfabrication process, based on silicon-on-insulator (SOI) technology, inherently has excellent control over the final probe thickness without wet etching. The needle shanks are 6 mm long and 80 /spl mu/m wide. Here the thickness of the probe, 25 /spl mu/m, is defined by the device layer thickness on the SOI wafer. Our new sprinkler fluidic channel, which has holes spaced 50 /spl mu/m apart along its 6 mm length, permits the perfusion of a large area of tissue with any desired neurotransmitter or other drug. The probes fabricated here are tested in the cat primary visual cortex; data recorded from adjacent neurons was used to characterize their orientation tuning. The sprinkler channel was characterized, and flowrate through the channel is a linear function of the applied pressure.     

Fabrication of a rotary micromirror for fiber-optic switching

The implementation of all-optical telecommunication networks requires more efficient optical-to-optical wavelength routing devices to replace the conventional optical-to-electrical cross connects. In this paper, we demonstrate a novel rotary micromirror for directly fiber-optic switching. To fabricate this electrostatically actuated rotary micromirror, a very simple micromachining process has been developed using SOI wafer and DRIE technology. Based on this one-mask process, all the components for an NxN cross-connect with 2N-switch-architecture can be fabricated on a monolithic silicon substrate, including the optic fiber couplers, electrostatic comb drives and reflective vertical mirror arrays.     

Fabrication and characterization of DRIE-micromachined electrostatic microactuators for hard disk drives

In this paper, deep micromachined three-dimensional (3-D) electrostatic microactuators used for dual-stage positioning system of hard disk drives are reported. Actuators with parallel-arranged comb drives enhance the electrostatic driving force. By using proper flexures, secondary stage actuators will drive the magnetic head with fast response and high accuracy. Fabrication of the actuators starts with a 200-μm-thick n-type silicon wafer, and it is subsequently bonded to a Pyrex glass substrate, which can be called silicon-on-glass process. This process is more cost-effective than the SOI wafer process, and the high aspect ratio structures with large thickness also provide good strength and reliability for the microactuators. Deep RIE and wafer bonding techniques were utilized to fabricate the electrostatic actuators. The fabricated actuators were statically and dynamically characterized for three different designs of straight-flexures, folded-flexures and quad-flexures with bandwidth of 7.15, 5.85 and 15.85 kHz, respectively. With proper designed flexures, the proposed microactuators would fulfill the requirements of the dual-stage servo of hard disk drives.     

Membrane microcantilever arrays fabrication with PZT thin films for nanorange movement

Lead zirconate titanate (PZT) piezoelectric thin films have been prepared by sol-gel method to fabricate microcantilever arrays for nano-actuation with potential applications in the hard disk drives. In order to solve the silicon over-etching problem, which leads to a low production yield in the microcantilever fabrication process, a new fabrication process using DRIE etching of silicon from the front side of the silicon wafer has been developed. Silicon free membrane microcantilevers with PZT thin films of 1 μm in thickness have been successfully fabricated with almost 100% yield by this new process. Annealing temperature and time are critical to the preparation of the sol-gel PZT thin film. The fabrication process of microcantilever arrays in planar structure will be presented. Key issues on the fabrication of the cantilever are the compatible etching process of PZT thin film and the compensation of thin film stress in all layers to obtain a flat multi-layer structure.     

Sacrificial wafer bonding for planarization after very deep etching

A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a wafer bond step followed by an etch back. Results of polymer bonding followed by dry etching and anodic bonding combined with KOH etching are discussed. The polymer bonding has been applied in a strain based membrane pressure sensor to pattern the strain gauges and to provide electrical connections across a deep corrugation in a thin silicon nitride membrane by metal bridges     

Toward Flexible Thermoelectric Flow Sensors: A New Technological Approach

A new technological approach on thin flexible sensors is presented. As proof of concept, a thermoelectric flow sensor on a 10-mum-thick polyimide foil has been realized. The advantages of silicon as a thermoelectric material and the stability of low-pressure chemical vapor deposition (LPCVD)-silicon nitride as a protective coating are combined with the flexibility of polymer substrates. The thermoelectric flow sensor is fabricated on a standard silicon wafer for handling purposes. Only the functional layers that are embedded in 600 nm of LPCVD-silicon nitride are transferred onto a 10-mum-thick polyimide. The bulk silicon has been removed using deep reactive ion etching. Samples have been fabricated and tested, proving the potential of this new technological concept. The first characterization results show that the sensor layout has to be adapted to the properties of the polymer substrate.     

Factorial experimental design applied to DRIE for optimised process in power electronics applications requiring high-aspect ratio trenches

A reliable factorial experimental design was applied to DRIE for specifically producing high-aspect ratio trenches. These trenches are to be used in power electronics applications such as active devices: deep trench superjunction MOSFET (DT-SJMOSFET) and passive devices: 3D integrated capacitors. Analytical expressions of the silicon etch rate, the verticality of the profiles, the selectivity of the mask and the critical loss dimension were extracted versus the process parameters. The influence of oxygen in the passivation plasma step was observed and explained. Finally, the analytical expressions were applied to the devices objectives. A perfectly vertical trench 100-μm deep was obtained for DT-SJMOSFET. Optimum conditions for reaching high-aspect ratio structures were determined in the case of high-density 3D capacitors.     

Micromachining of buried micro channels in silicon

A new method for the fabrication of micro structures for fluidic applications, such as channels, cavities, and connector holes in the bulk of silicon wafers, called buried channel technology (BCT), is presented in this paper. The micro structures are constructed by trench etching, coating of the sidewalls of the trench, removal of the coating at the bottom of the trench, and etching into the bulk of the silicon substrate. The structures can be sealed by deposition of a suitable layer that closes the trench. BCT is a process that can be used to fabricate complete micro channels in a single wafer with only one lithographic mask and processing on one side of the wafer, without the need for assembly and bonding. The process leaves a substrate surface with little topography, which easily allows further processing, such as the integration of electronic circuits or solid-state sensors. The essential features of the technology, as well as design rules and feasible process schemes, will be demonstrated on examples from the field of μ-fluidics     

Improved process flow for buried channel fabrication in silicon

The fabrication of microchannels using MEMS technology always attracted the attention of researchers and designers of microfluidic systems. Our group focused on realizing buried fluidic channels in silicon substrates involving deep reactive ion etching. To meet the demands of today’s complex microsystems, our aim was to create passive microfluidics in the bulk Si substrate well below the surface, while retaining planarity of the wafer. Therefore additional lithographic steps for e.g. integrating circuit elements are still possible on the chip surface. In this paper, a more economic process flow is applied which also contains a selective edge-masking method in order to eliminate under-etching phenomenon at the top of the trenches to be filled. The effect of Al protection on the subsequent etch steps is also discussed. Applying the proposed protection method, our group successfully fabricated sealed microchannels with excellent surface planarity above the filled trenches. Due to the concept, the integration of the technology in hollow silicon microprobes fabrication is now available.     

High aspect-ratio combined poly and single-crystal silicon (HARPSS)MEMS technology

This paper presents a single-wafer high aspect-ratio micromachining technology capable of simultaneously producing tens to hundreds of micrometers thick electrically isolated poly and single-crystal silicon microstructures. High aspect-ratio polysilicon structures are created by refilling hundreds of micrometers deep trenches with polysilicon deposited over a sacrificial oxide layer. Thick single-crystal silicon structures are released from the substrate through the front side of the wafer by means of a combined directional and isotropic silicon dry etch and are protected on the sides by refilled trenches. This process is capable of producing electrically isolated polysilicon and silicon electrodes as tall as the main body structure with various size capacitive air gaps ranging from submicrometer to tens of micrometers. Using bent-beam strain sensors, residual stress in 80-μm-thick 4-μm-wide trench-refilled vertical polysilicon beams fabricated in this technology has been measured to be virtually zero. 300-μm-long 80-μm-thick polysilicon clamped-clamped beam micromechanical resonators have shown quality factors as high as 85 000 in vacuum. The all-silicon feature of this technology improves long-term stability and temperature sensitivity, while fabrication of large-area vertical pickoff electrodes with submicrometer gap spacing will increase the sensitivity of micro-electromechanical devices by orders of magnitude     

Characterization of capacitive micromachined ultrasonic transducers

This paper describes numerical and experimental characterization of capacitive micromachined ultrasonic transducers (CMUTs) for ultrasound transmission. Simulations based on a finite elements method to model the electromechanical behaviour of CMUTs and to determine the dimensions of elementary cells are presented. In particular, we analyse how the collapse voltage and the capacitance are affected by different parameters of a circular cell and by different bias voltages. The fill factor is defined as the ratio of the top electrode radius to the membrane radius and we study the influence of the fill factor in the performances of CMUTs. The fabrication process of a CMUT uses anodic bonding of a SOI wafer on a borosilicate glass substrate and we compare experimental results with numerical results in terms of eigenfrequencies, bandwidth, quality factor and capacitance for non-metallized and metallized membranes.