A High Dynamic Range Programmable CMOS Front-End Filter with a Tuning Range from 1850 to 2400 MHz

This paper presents a highly programmable front-end filter and amplifier intended to replace SAW filters and low noise amplifiers (LNA) in multi-mode direct conversion radio receivers. The filter has a 42 MHz bandwidth, is tunable from 1850 to 2400 MHz, achieves a 5.8 dB NF, –25 dBm in-band 1-dB input compression point (ICP) and 0 dBm out-of-band ICP while drawing 26 mA from a 2.5 V supply.     

High dynamic range 60 MHz powerline front-end IC

Presented for the first time, is a novel broadband powerline front-end realised in 0.25 mum SiGe BiCMOS with superior performance. The frequency range of the transmitter (TX) and the direct conversion receiver (RX) exceeds 60 MHz with a very wide dynamic range up to 99.5 dB for the lowest channel bandwidth. The integrated IF filter is tunable from 1 up to 8 MHz. The measured input-referred noise of the TX with low third intermodulation distortion (IMD3) is -140 and 144.5 dBm/Hz for the RX.     

A parallel structure for CMOS four-quadrant analog multipliers andits application to a 2-GHz RF downconversion mixer

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 μm N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under a single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV_p-p at both multiplier inputs. The -3 dB bandwidth is 2.2 MHz and the DC current is 2.3 mA. By using the proposed multiplier as a mixer-core and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5 μm single-poly-double-metal N-well CMOS technology. The experimental results have shown that, under 3 V supply voltage and 2 dBm LO power, the mixer has -1 dB conversion gain, 2.2 GHz input bandwidth, 180 MHz output bandwidth, and 22 dB noise figure. Under the LO frequency 1.9 GHz and the total DC current 21 mA, the third-order input intercept point is +7.5 dBm and the input 1 dB compression point is -9 dBm     

A 1.5-V 0.7–2.5-GHz CMOS Quadrature Demodulator for Multiband Direct-Conversion Receivers

An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was implemented in a 0.13-mum CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9-33 kHz 1/f-noise corner. The measured IIP3 is 4 dBm for a 0.1-MHz IF frequency and 10 dBm for a 1-MHz IF frequency. The total chip draws 20 to 24 mA from a single 1.5-V supply.     

A D‐Band Balanced Subharmonically‐Pumped Resistive Mixer Based on 100‐nm mHEMT Technology

A D‐band subharmonically‐pumped resistive mixer has been designed, processed, and experimentally tested. The circuit is based on a 180° power divider structure consisting of a Lange coupler followed by a λ/4 transmission line (at local oscillator (LO) frequency). This monolithic microwave integrated circuit (MMIC) has been realized in coplanar waveguide technology by using an InAlAs/InGaAs‐based metamorphic high electron mobility transistor process with 100‐nm gate length. The MMIC achieves a measured conversion loss between 12.5 dB and 16 dB in the radio frequency bandwidth from 120 GHz to 150 GHz with 4‐dBm LO drive and an intermediate frequency of 100 MHz. The input 1‐dB compression point and IIP3 were simulated to be 2 dBm and 13 dBm, respectively.     

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards     

A broadband RF 65 nm CMOS front-end for cable TV reception

A novel broadband RF front-end in 65 nm CMOS technology is presented. The front-end serves to precondition the incoming RF spectrum for further processing in a cable TV receiver architecture where RF channel selection and down conversion are done in digital domain. The analog front-end consists of a broadband highly linear low-noise amplifier followed by a variable gain RF amplifier. An original broadband circuit topology for the amplifiers is adopted.The fabricated front-end exhibits a bandwidth of 50-1050 MHz, a variable gain, which spans from 12 to 37 dB with a 0.2 dB step, an OIP3 of 28.4 dBm (77.5 dBmV), an OIP2 of 65 dBm (114 dBmV), and a noise figure of 5.8 dB, dissipating 125 mW at 1.2 V supply, and a core silicon area of 0.4 mm².     

Time-variant analysis and design of a power efficient ISM-band quadrature receiver

In this work a 2.2 GHz quadrature receiver front-end suitable for low-power applications is presented. The low-noise amplifier, the mixer and the voltage-controlled oscillator are merged into a single stage, making the circuit capable of extreme current reuse while keeping it still functional at low supply voltage. A careful linear time-variant analysis is proven to be necessary to accurately predict the conversion gain and the bandwidth of the downconverter. A prototype, implemented in a 90 nm CMOS technology, validates the theoretical analysis, showing 27 dB of downconversion gain over a 14 MHz base-band bandwidth; the noise figure is 13 dB with a flicker corner frequency of 200 kHz; the input-referred 1 dB compression point is −23.7 dBm. The circuit draws only 1.3 mA from a 1.0 V supply.     

A 14 mW 2.5 MS/s 14 bit Σ∆ Modulator Using Split-Path Pseudo-Differential Amplifiers

This paper presents the design and experimental results of a 1.25 MHz signal bandwidth 14 bit CMOS SigmaDelta modulator. With our proposed switched-capacitor split-path pseudo-differential amplifiers, this modulator achieves high power efficiency, high sampling frequency, and small die area. A new signal and reference front-end sampling network eliminates the input common-mode voltage and reduces power consumption and linearity requirement of the opamp. A prototype chip has been designed and fabricated in a 0.25 mum CMOS technology with a core area of 0.27 mm². Experimental results show that an 84 dB dynamic range is achieved over a 1.25 MHz signal bandwidth when clocked at 125 MHz. The power dissipation is 14 mW at 2.4 V including on-chip voltage reference buffers.     

A 20 GHz microwave sampler

A microwave sampler circuit which operates over the frequency band of 1-20 GHz and has a number of novel features is described. These features include a wideband microstrip-to-slot balun and a wideband active isolator the function of which is to reduce the local oscillator to RF leakage from the input port of the sampler. The signal-to-noise ratio over the input bandwidth is greater than 20 dB at an input power level of -32 dBm. This signal-to-noise ratio was measured in an IF bandwidth of 175 MHz and includes the contribution from the IF amplifier. The sampler, which is made on alumina using MIC techniques, has an integrated impulse generator driven with a sinusoidal local oscillator of only 20 dBm over the frequency band of 250-350 MHz. The IF signal is in the 10-175-MHz band. The RF input VSWR is better than 2:1 up to 20 GHz, and the oscillator to RF breakthrough is better than -58 dBm (-78 dBc) when driven with a local oscillator of 20 dBm. This unusually low leakage was achieved by using the active isolator prior to the sampling circuit     

2.4 GHz ISM-Band Receiver Design in a 0.18 μm Mixed Signal CMOS Process

This letter presents the design and measurement results of a fully integrated CMOS receiver front-end and voltage controlled oscillator (VCO) for 2.4 GHz industrial, scientific and medical (ISM)-band application. For low cost design, this receiver has been fabricated with a 0.18 mum thin metal CMOS process with a top metal thickness of only 0.84 mum. The receiver integrates radio frequency (RF) front-end (a single-ended low-noise amplifier (LNA) with on-chip spiral inductors and a double balanced down conversion mixer), VCO and local oscillation buffers on a single chip together with an internal output buffer. To obtain the high-quality factor inductor in LNA, VCO and down conversion mixer design, patterned-ground shields (PGS) are placed under the inductor to reduce the effect from image current of resistive Si substrate. Moreover, in VCO and mixer design, due to the incapability of using thick top metal layer of which the thickness is over 2 mum, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via arrays along the metal traces is adopted to compensate the Q -factor degradation. In this letter, the receiver achieves a conversion gain of 23 dB, noise figure of 8.1 dB and P1 dB of -20 dBm at 39 MHz with 21 mW power dissipation from a 1.8 V power supply. It occupies a whole circuit area of 2 mm².     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

A 1024-QAM Analog Front-End for Broadband Powerline Communication Up to 60 MHz

A high performance analog front-end (AFE) for broadband powerline communication between 1.6 and 60 MHz is presented. The frequency division multiplexing AFE supports optimum channel selection, avoids disturbing RF signals and allows co-existence with other users of the spectrum. The direct-conversion receiver operates linearly up to a + 18 dBm input level. Tunable low-pass filters, integrated into the receive path, support a wide class of service requirements by channel bandwidth selection. The dynamic range is 99.5 dB for 2 MHz channels, and 90.5 dB for 16 MHz channels. Error vector magnitude measurements are presented for a single-carrier 1024-QAM and a 1024-carrier 64-QAM signal as function of frequency and channel attenuation. For 1024-QAM, the error vector magnitude (EVM) is below or equal to 1.2% rms up to 60 dB of attenuation, whereas the 1024-carrier 64-QAM performs well up to 80 dB of attenuation. The presented chip was fabricated in a 0.25 mum SiGe BiCMOS process, and the measured power consumption from a single 2.5 V supply is 668 mW.     

A two-path bandpass ΣΔ modulator for digital IFextraction at 20 MHz

Oversampled bandpass A/D converters based on sigma-delta (ΣΔ) modulation can be used to robustly digitize the types of narrowband intermediate frequency (IF) signals that arise in radios and cellular systems. This paper proposes a two-path architecture for a fourth-order, bandpass modulator that is more tolerant of analog circuit limitations at high sampling speeds than conventional implementations based on the use of switched-capacitor biquadratic filters. An experimental prototype employing the two-path topology has been integrated in a 0.6-μm, single-poly, triple-metal CMOS technology with capacitors synthesized from a stacked metal structure. Two interleaved paths clocked at 40 MHz digitize a 200-kHz bandwidth signal centered at 20 MHz with 75 dB of dynamic range while suppressing the undesired mirror image signal by 42 dB. At low input signal levels, the mixing of spurious tones at DC and f_s/2 with the input appears to degrade the performance of the modulator; out-of-band sinusoidal dither is shown to be an effective means of avoiding this degradation. The experimental modulator dissipates 72 mW from a 3.3 V supply     

A GaAs double-balanced dual-gate FET mixer IC for UHF receiver front-end applications

A double-balanced dual-gate FET mixer has been developed for application in the front-end circuit of UHF receivers. A 6-8-dB conversion gain has been obtained without an additional matching circuit over a wide frequency range from 100-800 MHz with good suppression of RF/LO feedthrough by more than 20 dB and third-order intermodulatian product of -60 dB.     

Broadband electronically tunable planar active radiating elementsand spatial power combiners using notch antennas

A Gunn device has been integrated with two types of active planar notch antennas. The first types uses a coplanar waveguide (CPW) resonator an a stepped-notched antenna with bias tuning to achieve a bandwidth of 275 MHz centered at 9.33 GHz with a power output of 14.2±1.5 dBm. The second type uses a CPW resonator with a varactor for frequency tuning to achieve a bandwidth of over 1.3 GHz centered at 9.6 GHz with a power output of 14.5±0.8 dBm. This is equivalent to over 14% electronic tuning bandwidth. Both configurations exhibit a very clean and stable output signal. A theoretical circuit model was developed to facilitate the design. The model agrees well with experimental results. Injection-locking experiments on the second configuration show a locking gain of 30 dB with a locking bandwidth of 30 MHz at 10.2 GHz. Power combining experiments of two-varactor-tuned CPW active notch antenna elements in a broadside configuration have achieved well over 70% combining efficiency throughout the wide tuning range. The circuits have advantages of small size, low cost, and excellent performance     

2.7 V 50 MHz IF sampling ΔΣ modulator with +37 dBV IIP3

The design and experimental results of a 2.7 V 50 MHz switched-capacitor DS modulator in a 0.35 μm BiCMOS process are presented. The circuit is targeted for the IF section of a radio receiver in a GSM cellular phone. It combines frequency downconversion with analogue to digital conversion by directly sampling an input signal from an IF of 50 MHz. The measured peak signal-to-noise ratio for a 100 kHz bandwidth is 81 dB with a 53 MHz blocking signal and the measured IIP3 for IF input is +36.9 dBV     

A 2.4-GHz sub-mW CMOS receiver front-end for wireless sensors network

A 2.4-GHz fully integrated CMOS receiver front-end using current-reused folded-cascode circuit scheme is presented. A configuration utilizing vertically stacked low-noise amplifier (LNA) and a folded-cascode mixer is proposed to improve both conversion gain and noise figure suitable for sub-mW receiver circuits. The proposed front-end achieves a conversion gain of 31.5dB and a noise figure of 11.8dB at 10MHz with 500-/spl mu/A bias current from a 1.0-V power supply. The conversion gain and noise figure improvements of the proposed front-end over a conventional merged LNA and single-balanced mixer are 11dB and 7.2dB at 10MHz, respectively, with the same power consumption of 500/spl mu/W.     

A CMOS channel-select filter for a direct-conversion wirelessreceiver

A highly selective and linear switched-capacitor channel-select filter is fabricated in 1-μm CMOS for a direct-conversion wireless receiver operating in the 902-928 MHz ISM band. The filter selects a 230-kHz wide channel and attenuates by at least 50 dB from 320 kHz to 57 MHz. The input IP3 is +30 dBm, the input-referred noise in the passband is 70 nV/√Hz, and the circuit takes 4.6 mA from a 3.3 V supply. Direct subsampling of the 915 MHz RF input signal by the filter front-end is also demonstrated with only a small degradation in linearity. The input noise voltage is halved in a redesign while keeping the current drain unchanged