Design of edge termination for GaN power Schottky diodes

The GaN Schottky diodes capable of operating in the 300–700-V range with low turn-on voltage (0.7 V) and forward conduction currents of at least 10 A at 1.4 V (with corresponding forward current density of 500 A/cm²) are attractive for applications ranging from power distribution in electric/hybrid electric vehicles to power management in spacecraft and geothermal, deep-well drilling telemetry. A key requirement is the need for edge-termination design to prevent premature breakdown because of field crowding at the edge of the depletion region. We describe the simulation of structures incorporating various kinds of edge termination, including dielectric overlap and ion-implanted guard rings. Dielectric overlap using 5-μm termination of 0.1–0.2-μm-thick SiO₂ increases the breakdown voltage of quasi-vertical diodes with 3-μm GaN epi thickness by a factor of ∼2.7. The use of even one p-type guard ring produces about the same benefit as the optimized dielectric overlap termination.     

Schottky barriers on n-GaN grown on SiC

Characteristics of Schottky barriers fabricated on n-type GaN were investigated. The barriers were formed by vacuum thermal evaporation of Cr, Au, and Ni. Current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the barriers were measured in a wide temperature and current density range. Fundamental parameters (barrier height and built-in potential) of the Schottky barriers were determined. The dependence of the barrier ideality factor on doping concentration in GaN was measured. Correlation between the barrier height and metal work function was observed. The electron affinity for GaN was determined using both C-V and I-V characteristics. The current flow mechanism through the barriers is discussed.     

Optimization design on breakdown voltage of AlGaN/GaN high-electron mobility transistor

Simulations are carried out to explore the possibility of achieving high breakdown voltage of GaN HEMT (high-electron mobility transistor). GaN cap layers with gradual increase in the doping concentration from 2×10¹⁶ to 5×10¹⁹ cm^-3 of N-type and P-type cap are investigated, respectively. Simulation results show that HEMT with P-doped GaN cap layer shows more potential to achieve higher breakdown voltage than N-doped GaN cap layer under the same doping concentration. This is because the ionized net negative space charges in P-GaN cap layer could modulate the surface electric field which makes more contribution to RESURF effect. Furthermore, a novel GaN/AlGaN/GaN HEMT with P-doped GaN buried layer in GaN buffer between gate and drain electrode is proposed. It shows enhanced performance. The breakdown voltage of the proposed structure is 640 V which is increased by 12% in comparison to UID (un-intentionally doped) GaN/AlGaN/GaN HEMT. We calculated and analyzed the distribution of electrons'' density. It is found that the depleted region is wider and electric field maximum value is induced at the left edge of buried layer. So the novel structure with P-doped GaN buried layer embedded in GaN buffer has the better improving characteristics of the power devices.     

n-GaN肖特基势垒紫外光探测器的电子辐照效应

研究了n型Au/GaN肖特基势垒紫外光探测器的电子辐照失效机理.从实验中观测到,随着电子辐照注量的不断增加,Au/GaN间辐照诱生的界面态引起器件的击穿电压明显减小,反向漏电流逐渐增大.辐照诱生的深能级缺陷导致紫外光探测器对较长波长光的吸收,使得UV探测器中可见光成分的背景噪声增加.同时,对辐照后的GaN肖特基紫外光探测器进行了100℃以下的退火处理,退火后,器件的电流-电压特性有所改善.     

300V以上硅基新型JBS肖特基二极管的制备

为了在保留传统肖特基二极管正向压降低、电流密度大优点的基础上,使其反向击穿电压提高到了300 v以上,我们采用硅材料做为衬底,肖特基结区采用蜂房结构,终端采用两道场限环结构加一道切断环结构,所制备的肖特基二极管在正向电流10A时,正向压降仅为0.79 V;同时在施加300 V反向电压时,反向漏电流在5μA以下.     

High voltage degradation of GaN High Electron Mobility Transistors on silicon substrate

We have electrically stressed GaN High Electron Mobility Transistors on Si substrate at high voltages. We observe a pattern of device degradation that differs markedly from previous reports in GaN-on-SiC HEMTs. Similarly to these devices, the gate leakage current of GaN-on-Si HEMTs increases by several orders of magnitude at a certain critical voltage and this increase is irreversible. However, in contrast with devices on SiC, the critical voltage varies substantially across the wafer, even over short distances, with values as high as 75 V being observed. In addition, for voltages below the critical voltage, we observe a prominent degradation in the drain current and the source and drain resistances, something not observed in devices on SiC. This degradation is almost completely recoverable under UV illumination. We attribute these results to the high mismatch that exists between GaN and Si that leads to a large concentration of electrically active traps and a lower and non-uniform initial strain in the AlGaN barrier. This is evidenced by observed correlations between threshold voltage and maximum drain current in fresh devices and their corresponding critical voltages.     

击穿电压提高的AlGaN/GaN/AlGaN双异质结特性

本文论述了AlGaN/GaN双异质结高电子迁移率晶体管的特性,该结构使用Al组分为7%的AlGaN来代替传统的GaN作为缓冲层。Al0.07Ga0.93N缓冲层增加了二维电子气沟道下方的背势垒高度,有效提高了载流子限阈性,从而造成缓冲层漏电的显著减小以及击穿电压的明显提高。对于栅尺寸为0.5100μm,栅漏间距为1μm的器件,AlGaN/GaN 双异质结器件的击穿电压（~100V）是常规单异质结器件的两倍（~50V）。本文中的双异质结器件在漏压为35V、频率为4GHz下,最大输出功率为7.78W/mm,最大功率附加效率为62.3%,线性增益为23dB。     

Characteristics of AlGaN/GaN/AlGaN double heteroj unction HEMTs with an improved breakdown voltage

正We studied the performance of AlGaN/GaN double heterojunction high electron mobility transistors (DH-HEMTs) with an AlGaN buffer layer,which leads to a higher potential barrier at the backside of the twodimensional electron gas channel and better carrier confinement.This,remarkably,reduces the drain leakage current and improves the device breakdown voltage.The breakdown voltage of AlGaN/GaN double heterojunction HEMTs (~ 100 V) was significantly improved compared to that of conventional AlGaN/GaN HEMTs(~50 V) for the device with gate dimensions of 0.5 x 100μm and a gate-drain distance of 1μm.The DH-HEMTs also demonstrated a maximum output power of 7.78 W/mm,a maximum power-added efficiency of 62.3%and a linear gain of 23 dB at the drain supply voltage of 35 V at 4 GHz.     

A novel high-voltage device structure with an N~+ ring in substrate and the breakdown voltage model

A novel high-voltage device structure with a floating heavily doped N~+ ring embedded in the substrate is reported,which is called FR LDMOS.When the N~+ ring is introduced in the device substrate,the electric field peak of the main junction is reduced due to the transfer of the voltage from the main junction to the N~+ ring junction, and the vertical breakdown characteristic is improved significantly.Based on the Poisson equation of cylindrical coordinates,a breakdown voltage model is developed.The numerical results indicate that the breakdown voltage of the proposed device is increased by 56%in comparison to conventional LDMOS.     

X波段GaN HEMT的研制

采用双台面隔离工艺,实现了器件有源区隔离,隔离电压大于250 V/10μA.通过对金属化前和介质膜淀积前的预处理过程的改进,实现了较理想的肖特基势垒特性,电压也得到了大幅度提高,理想因子n值小于1.7,源漏击穿电压大于50 V/1 mA,栅源击穿电压大于40 V/1 mA,最终实现器件X波段连续波输出功率20 W,功率增益7 dB,功率密度8 W/mm.     

基于多频超声的变压器油击穿电压传播特性研究

随着智能化电网规模的逐步扩大,对电网的供电质量和安全可靠运行的要求也越来越高.变压器作为电力系统中最核心的设备之一,承担着整个电网的输变电任务,其稳定的运行状态关乎到电力系统的安全运行.通过对变压器油的日常监督,提前预测变压器油的击穿电压对于保证电力变压器以及电网的稳定安全运行具有现实意义.本文通过研究多频超声检测技术...     

衬底浮空N 环高压器件新结构与击穿电压模型

提出带有衬底重掺杂N 环的高压器件新结构,称为FR LDMOS。在衬底中引入高掺杂N 环,漏极偏压由环结和漂移区主结分担,降低了主结电场,纵向击穿特性获得显著改善。基于柱坐标Poisson方程,建立击穿电压模型。结果表明：FR LDMOS较常规器件击穿电压提高56%。     

衬底偏压对硅基高压器件新结构击穿电压特性的影响

提出基于衬底偏压技术的double RESURF结构,称为Sb double RESURF LDMOS。在n型衬底和n型漂移区之间嵌入p型外延层,阻挡器件阻断状态下的纵向电流通路,改变体内电场分布。衬底偏压加强漂移区电荷共享效应,降低漏极下方纵向电场峰,该技术对提高薄漂移区横向功率器件的纵向击穿电压尤其重要。结果表明,在保持较小导通电阻下,该结构较常规LDMOS击穿电压提高97%。     

4H-SiC TSOB结势垒肖特基二极管静态特性

为增强器件的反向耐压能力,降低器件的漏电功耗,采用Silvaco TCAD对沟槽底部具有SiO₂间隔的结势垒肖特基二极管(TSOB)的器件特性进行了仿真研究。通过优化参数来改善导通压降(V_F)-反向漏电流(I_R)和击穿电压的折衷关系。室温下,沟槽深度为2.2 μm时,器件的击穿电压达到1 610 V。正向导通压降为2.1 V,在V_F=3 V时正向电流密度为199 A/cm²。为进一步改善器件的反向阻断特性,在P型多晶硅掺杂的有源区生成一层SiO₂来优化漂移区电场分布,此时改善的器件结构在维持正向导通压降2.1 V的前提下,击穿电压达到1 821 V,增加了13%。在1 000 V反向偏置电压下,反向漏电流密度比普通结构降低了87%,有效降低了器件的漏电功耗。普通器件结构的开/关电流比为2.6×10³(1 V/-500 V),而改善的结构为1.3×10⁴(1 V/-500 V)。     

Investigation of Al Schottky junction on n-type CdS film deposited on polymer substrate

A systematic study has been made on the behavior of Al/n-CdS thin film junction on flexible polymer substrate (polyethylene terephthalate, PET) grown using thermal evaporation method. Temperature dependence of I-V measurements for this junction has been done which closely follow the equations of Schottky barrier junction dominated by thermionic emission mechanism. Intrinsic and contact properties such as barrier height, ideality factor and series resistance have been calculated from I-V characteristics. The barrier height of Al/n-CdS junction is found to increase with increase in temperature whereas ideality factor and series resistance decrease with increase in temperature.     

A new SOI high voltage device based on E-SIMOX substrate

A new NI (n+ charge islands) high voltage device structure based on E-SIMOX (epitaxy-the separation by implantation of oxygen) substrate is proposed. It is characterized by equidistant high concentration n+-regions on the top interface of the dielectric buried layer. Inversion holes caused by the vertical electric field (Ev) are located in the spacing of two neighboring n+-regions on the interface by the force from lateral electric field (EL) and the compositive operation of Coulomb's forces with the ionized donors in the undepleted n+-regions. This effectively enhances the electric field of dielectric buried layer (EI) and increases breakdown voltage (Vb). An analytical model of the vertical interface electric field for the NI SOI is presented, and the analytical results are in good agreement with the 2D simulative results. EI = 568 V/μm and VB = 230 V of NI SOI are obtained by 2D simulation on a 0.375-μm-thick dielectric layer and 2-μm-thick top silicon layer. The device can be manufactured by using the standard CMOS process with addition of a mask for implanting arsenic to form NI. 2-μm silicon layer can be achieved by using epitaxy SIMOX technology (E-SIMOX).     

一种新的基于E-SIMOX衬底的SOI高压器件

本文提出一种新的基于E-SIMOX衬底的n+电荷岛结构的SOI高压器件（NI SOI）。该结构在SOI器件介质层上界面注入形成一系列等距的高浓度n+区。纵向电场（EV）所形成的反型电荷将被来自横向电场（EL）的电场力和未耗尽n+区内高浓度电离施主杂质的库仑力综合作用下固定于界面两个n+之间,从而能有效的提高介质场（EI）,增强器件的击穿电压（VB）。提出的NI SOI的纵向解析模型与二维仿真结果相吻合。对0.375μm的介质层,2μm顶层硅的NI SOI 器件,EI =568V/μm和VB =230V。该器件在工艺上通过注入砷形成高浓度n+区,使用外延技术得到2μm的顶层硅(即E-SIMOX技术),它除了增加一张掩模版以外,和常规的CMOS工艺完全兼容。     

介质基板电容分压器幅度线性度研究

高功率电脉冲装置常使用电容分压器来监测其电压值。电容分压器的幅度线性度表征了分压器在大电压与小电压下分压比的一致程度,线性度的好坏直接关系到监测的电压值的准确程度。本文通过对介质基板电容分压器进行原理分析,并通过仿真软件在脉宽为200 ns的矩形脉冲高压源(500 V～4 kV)与半高宽约为10μs的冲击高压源(10～100 kV)下分别对介质基板电容分压器的性能进行仿真,并设计加工。之后分别采用两种高压源对分压器进行实验研究,结果显示,介质基板电容分压器的幅度线性度在500 V～100 kV之内为1.16%,线性度较好,可以将小信号下校准的分压比用于大信号的测量中。     

Low dark current and internal gain mechanism of GaN MSM photodetectors fabricated on bulk GaN substrate

Metal-semiconductor-metal ultraviolet photodetectors are fabricated on low-defect-density homoepitaxial GaN layer on bulk GaN substrate. The dislocation density of the homoepitaxial layer characterized by cathodoluminescence mapping technique is ∼5 × 10⁶ cm⁻². The photodetector with a high UV-to-visible rejection ratio of up to 1 × 10⁵ exhibits a low dark current of <2 pA at room temperature under 10 V bias. The photo-responsivity of the photodetector gradually increases as a function of applied bias, resulting in a photodetector quantum efficiency exceeding 100% at above medium bias. The photo-responsivity also shows a dependence on the incident optical power density and illumination conditions. The internal gain mechanism of the photodetector is attributed to photo-generated holes trapped at the semiconductor/metal interface as well as high-field-induced image-force lowering effect.