Laser-assisted bumping for flip chip assembly

A novel laser-assisted chip bumping technique is presented in which bumps are fabricated on a carrier and subsequently transferred onto silicon chips by a laser-driven release process. Copper bumps with gold bonding layers and intermediate nickel barriers are fabricated on quartz wafers with pre-deposited polyimide layers, using UV lithography and electroplating. The bumps are thermosonically bonded to their respective chips and then released from the carrier by laser machining of the polyimide layer, using light incident through the carrier. Bumps of 60 to 85 μm diameter and 50 μm height at a pitch of 127 μm have been fabricated in peripheral arrays. Parallel bonding and subsequent transfer of arrays of 28 bumps onto test chips have been successfully demonstrated. Individual bump shear tests have been performed on a sample of 13 test chips, showing an average bond strength of 26 gf per bump     

Single chip bumping and reliability for flip chip processes

Processes of bump deposition based on mechanical procedures together with their reliability data are summarized in this paper. The stud bumping of gold, palladium, and solder is described and also a novel bumping approach for fine pitch solder deposition down to 100 μm pitches using thermosonic bonding on a modified wedge–wedge bonding machine. This wedge bumping doesn’t require a wire flame-off process step. Because of this, no active atmosphere is necessary. The minimum pad diameter which can be bumped using the solder wedge bumping is 50 μm, up to now. This bumping process is highly reproducible and therefore well-suited for different flip chip soldering applications. Palladium stud bumps provide a solderable under bump metallization. Results from aging of lead/tin solder bumps on palladium are shown. The growth of intermetallics and its impact on the mechanical reliability are investigated.     

Technical challenges of stencil printing technology for ultra fine pitch flip chip bumping

Stencil printing remains the technology route of choice for flip chip bumping because of its economical advantages over traditionally costly evaporation and electroplating processes. This paper provides the first research results on stencil printing of 80 and 60 μm pitch peripheral array configurations with Type 7 Sn63/Pb37 solder paste. In specific, the paste particle size ranges from 2 to 11μm with an average particle size of 6.5 μm taken into account for aperture packing considerations. Furthermore, the present study unveils the determining role of stencil design and paste characteristics on the final bumping results. The limitations of stencil design are discussed and guidelines for printing improvement are given. Printing of Type 7 solder paste has yielded promising results. Solder bump deposits of 25 and 42 μm have been demonstrated on 80 μm pitch rectangular and round pads, respectively. Stencil printing challenges at 60 μm pitch peripheral arrays are also discussed.     

Plasma reflow bumping of Sn-3.5 Ag solder for flux-free flip chip package application

A new flux-free reflow process using Ar+10%H/sub 2/ plasma was investigated for application to solder bump flip chip packaging. The 100-/spl mu/m diameter Sn-3.5wt%Ag solder balls were bonded to 250-/spl mu/m pitch Cu/Ni under bump metallurgy (UBM) pattern by laser solder ball bonding method. Then, the Sn-Ag solder balls were reflowed in Ar+H/sub 2/ plasma. Without flux, the wetting between solder and UBM occurred in Ar+H/sub 2/ plasma. During plasma reflow, the solder bump reshaped and the crater on the top of bump disappeared. The bump shear strength increased as the Ni/sub 3/Sn/sub 4/ intermetallic compounds formed in the initial reflow stage but began to decrease as coarse (Cu,Ni)/sub 6/Sn/sub 5/ grew at the solder/UBM interface. As the plasma reflow time increased, the fracture mode changed from ductile fracture within the solder to brittle fracture at the solder/UBM interface. The off-centered bumps self-aligned to patterned UBM pad during plasma reflow. The micro-solder ball defects occurred at high power prolonged plasma reflow.     

A testing method and device for intrinsic stress measurement inwafer bumping process

A novel concept and the related testing methodology of a sensing device is presented. This device is used to determine the local intrinsic stresses induced in wafer processes such as metallization and bumping. The sensing device is essentially a pressure sensor structure with a specified membrane thickness. This sensing wafer is put into the processes which are under investigation and is processed together with the production wafers. During the process, the membrane is deformed due to the process induced intrinsic stress. The membrane deformation is either monitored continuously or measured after each process step by an optical method. Intrinsic stresses are calculated from the measured membrane deformations     

A novel bumping process for fine pitch Sn–Cu lead-free plating-based flip chip solder bumps

Electroplating is the best process for the manufacture of fine pitch flip chip solder bumps. However, certain unstable electroplating parameters usually cause poorer coplanarity, which affects packaging reliability and yield. This paper attempts to utilize a CMP-like polisher to reduce the nonuniform height deviation after electroplating. The optimization of three major polishing parameters—pad hardness, loading pressure, and polishing speed—enables the polisher to have a higher material removal rate (MRR) and an easier manipulation as compared with chemical mechanical polishing (CMP). After polishing at a pitch size of 100 μm, the overall coplanarity could be decreased sharply from 33±2.5 μm (coplanarity=7.5%) to 28±1 μm (coplanarity=3%) and it even reached 26±0.5 μm (coplanarity=1%) after reflow.     

An area-efficient LDMOS-SCR ESD protection device for the I/O of power IC application

Lateral Double diffused Metal Oxide Semiconductor (LDMOS) transistors are widely used in HV output circuit and its Electrostatic Discharge (ESD) problem have been well studied. LDMOS embed Silicon Controlled Rectifier (LDMOS-SCR) can be used to improve LDMOS ESD robustness. In order to further enhance the ESD self-protection capability of LDMOS-SCR, a new device LDMOS-SCR with a floating P+ implant region (FP-LDMOS-SCR) is proposed in this paper. Due to the floating P+ implant region is placed near the drain end, It2 of the new FP-LDMOS-SCR device increases obviously, compared with traditional LDMOS and LDMOS-SCR devices. The FP-LDMOS-SCR′s It2 with one floating P+ is 1.3 A and that with two floating P+ is 2.7 A. The results of Technology Computer Aided Design (TCAD) simulations will be presented in this paper to help analysis the physical mechanism and observe the ESD behavior of the LDMOS-SCR. The proposed FP-LDMOS-SCR, same driver capability with LDMOS, can be applied in HV output circuit and also provide its ESD self-protection through shunted ESD stress to ground.     

Stacked-NMOS triggered silicon-controlled rectifier for ESDprotection in high/low-voltage-tolerant I/O interface

A stacked-NMOS triggered silicon-controlled rectifier (SNTSCR) is proposed as the electrostatic discharge (ESD) clamp device to protect the mixed-voltage I/O buffers of CMOS ICs. This SNTSCR device is fully compatible to general CMOS processes without using a thick gate oxide to overcome the gate-oxide reliability issue. ESD robustness of the proposed SNTSCR device with different layout parameters has been investigated in a 0.35 μm CMOS process. The HBM ESD level of the mixed-voltage I/O buffer with the stacked-NMOS channel width of 120 μm can be obviously improved from the original ~2 kV to be greater than 8 kV by this SNTSCR device with device dimensions of only 60 μm/0.35 μm     

Redistribution in wafer level chip size packaging technology for high power device applications: Process and design considerations

The main investigation presented in this work is focused on the design and fabrication of redistribution in wafer level chip scale package (RDL in WLCSP) for high power device application. The design considers higher carrier loading incorporated with the dimensional broadening in both lateral and thickness direction of the metal redistribution layer. The lateral broadening shortens the channels of electrical isolation, while the thickness broadening evolves the conventional sputtering into the present electro-plating achieved Cu metallization layer. The innovation brings about the challenge for high power RDL in WLCSP. In this study, the interplay between structural design, process interactions, and possible solutions for high power RDL in WLCSP are presented. To address the arguments, two designs of experiment are conducted. We demonstrate the determinative influence factors, resultant from process interactions, toward the adhesive properties beyond the conventional wisdom.     

一种高速I~2C总线从器件接口IP核的设计与实现

本文介绍了I2C总线的工作过程,使用图形化设计工具,采用HDL-Verilog高级硬件描述语言按照自顶向下的设计方法完成了I2C从器件模式的IP核设计。通过特殊的设计思路,可实现高速数据传输。对此IP核用FPGA进行了验证,最终把它作为一个独立IP成功的应用于ASIC芯片设计中。     

Hybridization of FDTD and device behavioral-modeling techniques [interconnected digital I/O ports]

We present a systematic methodology for the electromagnetic modeling of interconnected digital I/O ports. Digital drivers and receivers are represented through behavioral models based on radial basis functions expansions. Such a technique allows a very accurate representation of nonlinear/dynamic effects as well as switching behavior of real-world components by means of carefully identified discrete-time models. The inclusion of these models into a finite-difference time-domain solver for full-wave analysis of interconnected systems is presented. A rigorous stability analysis shows that use of nonlinear/dynamic discrete-time models can be easily integrated with standard full-wave solvers, even in the case of unmatched sampling time. A set of numerical examples illustrates the feasibility of this method.     

The influence of stud bumping stress on device degradation in scaled MOSFETs

This paper presents the effect of area bumping on device degradation in scaled metal-oxide-semiconductor field-effect transistors (MOSFETs). We have investigated the gate channel length dependence of g_m degradation after stud bumping above the MOSFETs and changes in the charge pumping currents for those devices. The von Mises’s equivalent stress is used to simulate the distribution of mechanical stress at the gate edges. From the relationship between the distribution of the von Mises’s equivalent stress and the change in the charge pumping currents after stud bumping, we show that stress concentrates within 0.1 μm of the gate edges. Furthermore, by estimating the amount of increased interface-state density we predicted that stud bumping stress greatly influences the device degradation of scaled MOS devices.     

功率再利用法提高I/O效率

在定制IC的开发过程中,控制功耗以使手持式产品中电池工作寿命最长,是一个更需要优先考虑因素.I/O驱动器的功耗在这一功耗中占有很大的比重,特别是当芯片是I/O密集型的,而且还必须向外部存储器或外设传送高速率数据时.Adiabatic Logic公司的IP(知识产权)用一个"功率再利用"I/O单元解决了这一问题,因为这一I/O单元可以将驱动外部线路的总功耗降低75%."Adiabatic"这个词表示一个没有损失或增加能量的过程.     

Bus-invert coding for low-power I/O

Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit. While it is generally accepted that because of the large capacitances involved much of the power dissipated by an IC is at the I/O little has been specifically done for decreasing the I/O power dissipation. We propose the bus-invert method of coding the I/O which lowers the bus activity and thus decreases the I/O peak power dissipation by 50% and the I/O average power dissipation by up to 25%. The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power     

A low-power chipset for a portable multimedia I/O terminal

This paper presents the design of a low-power chipset for a portable multimedia terminal that supports pen input, speech I/O, text/graphics output, and one-way full-motion video. Its power consumption was minimized using an approach that involves optimization at all levels of the design, including extended voltage scaling, reduced swing logic, and switched capacitance reduction through operation reduction, choice of number representation, exploitation of signal correlations, self-timing to eliminate glitching, logic design, circuit design, and physical design. The entire chipset, which performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression, and D/A conversion, is implemented in 1.2 μm CMOS and operates from a 1.1 V supply while consuming less than 5 mW     

N-MOS JK master/slave flip flop design for use in high speed control and counting applications

An N-MOS version of the JK master/slave flip flop with preset and clear inputs has been designed for use in high speed control and counting applications.For the chip layout design, fast transient response and the low power dissipation, component density has been reduced using A-O-I (AND-OR-INVERT) gate. The transient analysis has been done using Spice 2G.6 program.The chip size is 124λ × 103λ (λ = 4 micron) and dissipates power of 0.715 mW.     

一种信号处理机的高速I／O接口结构

本文介绍了一种以TMS320C25为核心的信号处理机的高速I/O接口.在数据流图分析的基础上,讨论了高速I/O接口的功能与性能要求,重点分析了I/O接口的硬件结构及其功能的实现原理,该I/O接口可以与PC机配合构成独立的、通用的数据采集处理与分析系统.     

Double-sided cooling for high power IGBT modules using flip chiptechnology

A new technique for the packaging of IGBT modules has been developed. The components are sandwiched between two direct bond copper (DBC) substrates with aluminum nitride. Wire bonds are replaced with flip chip solder bumps, which allows cooling of components on both sides. Microchannel heat sinks are directly integrated in the package to decrease the thermal resistance of the module. Thus, a very compact module with high thermal performance is obtained. A prototype with two insulated gate bipolar transistors (IGBTs) and four diodes associated in parallel was realized and tested. In this paper, the innovative packaging technique is described, and results of thermal tests are presented