Metallized ultra-shallow-junction device technology for sub-0.1μm gate MOSFET's

This paper describes a new ultra-thin SOI-CMOS structure offering reduced parasitic diffusion-layer resistance. It addresses ways to deal with the ultra-shallow junctions required by sub-0.1 μm MOSFET's. Based on a CVD tungsten process we experimentally investigate the characteristics of selectively grown tungsten used in the source and drain region made in SOI layers of various thicknesses ranging from 10 to 100 nm. We also investigate certain CMOS device characteristics. The SOI-CMOS structure, with low parasitic diffusion-layer resistance and good contact characteristics for ultra-shallow junction devices exhibits superior device performance and high scalability     

Novel contact hole fabrication using selective liquid-phasedeposition instead of reactive ion etching

This work forms a contact hole utilizing the selectively liquid-phase deposited (S-LPD) silicon-oxide technique instead of the conventional reactive ion etching (RIE). The n⁺/p junction diode with contact hole formed by S-LPD exhibits an order of magnitude less reverse current, larger forward current, smaller ideality factor, and better thermal stability than that formed by RIE. A Schottky junction with S-LPD contact hole also possesses several excellent characteristics, including ideality factor, reverse current and barrier height, even without sintering treatment. These characteristics confirm the effectiveness of the S-LPD technique in replacing conventional RIE to form contact holes, particularly for future ultra-shallow junctions     

Advanced model and analysis of series resistance for CMOS scalinginto nanometer regime. I. Theoretical derivation

An advanced series resistance model is developed to accurately predict source/drain (S/D) series resistance of complementary metal-oxide semiconductor (CMOS) in the nanometer regime. The series resistance is modeled by division into four resistance components named SDE-to-gate overlap, S/D extension, deep S/D, and silicide-diffusion contact resistance, considering the nonnegligible doping-dependent potential relationship in MOS accumulation region due to scaled supply voltage, current behavior related to heavily doped ultra-shallow source/drain extension (SDE) junction, polysilicon gate depletion effects (PDE), lateral and vertical doping gradient effect of SDE junction, silicide-diffusion contact structure, and high-κ dielectric sidewall. The proposed model well characterizes unique features of nanometer-scale CMOS and is useful for analyzing the effect of source/drain parameters on CMOS device scaling and optimization     

n/p ultra-shallow junction formation with plasma immersion ion implantation

n⁺/p ultra-shallow junctions formed by PH₃ plasma immersion ion implantation (PIII) have been studied and diodes with good electrical characteristics have been obtained. The influence of annealing conditions and carrier gas on junction depth and sheet resistance have been studied. It is found that a higher content of H and/or He in silicon can slow down the diffusion of phosphorus and the activation ability of implanted dopant ions in silicon; a shallower junction can been obtained with He rather than H₂ as the carrier gas; and the influence of annealing at 850°C for 20 s on sheet resistance is opposite to that of annealing at 900°C for 6 s on sheet resistance. In addition, mechanisms of unusual electrical characteristics for some diodes are discussed and analyzed in this paper.     

Effects of AsH3 surface treatment for the improvement of ultra-shallow area-selective regrown GaAs sidewall tunnel junction

Low-temperature (290°C) area-selective regrowth by molecular layer epitaxy (MLE) was applied for the fabrication of an ultra-shallow sidewall (50 nm) GaAs tunnel junction. Fabricated tunnel junctions have shown a record peak current density up to 35,000 A/cm². It is shown that the tunnel junction characteristics are strongly dependent on the sidewall orientation and the AsH₃ surface treatment conditions just prior to regrowth. The effects of AsH₃ surface treatment are discussed in view of the control of surface stoichiometry.     

Formation of silicided,ultra-shallow junctions using low thermal budget processing

The tradeoffs involved in alternative processes for the formation of ultra shallow junctions are described. Low energy implantation, preamorphization to eliminate channeling and low thermal budget processing are adequate to form junctions that are 0.1 to 0.3μm deep. For junctions less than about 100 nm, however, the enhanced diffusion resulting from the amorphization implant reduces its benefits. Athermal diffusion can result in considerable junction motion even when low thermal budget processing is used. Junctions this shallow typically require silicide or metal cladding to reduce the sheet resistance; however, the dopant redistribution associated with siliciding pre-existing junctions increases the contact resistance which diminishes the potential benefit of silicidation. In addition, high leakage can result from excessive silicon consumption. While the use of silicide as a diffusion source can overcome some of the limitations of silicided junctions, this technique can be especially hindered by slow dopant diffusion or compound formation in the silicide and by the limited thermal stability of the silicide. One outstanding issue associated with silicide diffusion sources is understanding the seemingly enhanced diffusivity of dopant in the silicon.     

Ultra-thin-base Si bipolar transistor using rapid vapor-phasedirect doping (RVD)

A novel doping method called rapid vapor-phase direct doping (RVD) is developed to form ultra-shallow junctions. The base region of a conventional bipolar transistor is formed by this method, and in ultra-narrow 25-nm base is obtained. The Gummel plot of this device shows almost ideal characteristics. This result suggests that this method does not induce any defects which cause a leakage current. RVD is a thermal diffusion method using hydrogen as a carrier gas and B₂ H₆ as a source gas. In this method, the impurity atoms directly diffuse from the vapor phase into silicon by a rapid thermal process without a boron-glass layer or metallic boron layer. By varying the source gas flow rate, doping time, and temperature, ultra-shallow junctions below 40 nm with controlled surface concentrations are successfully formed. An ultra-shallow 20-nm junction with surface boron concentration of 4×10¹⁸ cm^-3 is obtained at 800°C for 5 min with B₂H₆ flow rate of 30 ml/min     

Optical,non-destructive characterization of ultra-shallow junctions

As ULSI technology moves below the 180 nm technology node, tight control of the depth of ultra-shallow junctions (USJ), such as those used in source-drain extensions, becomes critical. The problem is one of both local control and uniformity over the full area of 200 and 300 mm wafers. This paper describes the status of carrier illumination™ (CI), an optical method for measuring the active junction depth for ultra-shallow source-drain extensions. It features a non-destructive, high throughput measurement with a spot size of less than 2 μm. This provides rapid uniformity measurements on patterned wafers, enabling in-line control of USJ processes. CI is based on injecting excess carriers that line up with the active doping profile. These carriers act as a “contrast agent” allowing an optical interferometer to measure their profile. The active junction depth may then be deduced from the interferometer signal. This paper first describes the CI measurement and motivation for its development. It then presents a summary of qualification results on PMOS and NMOS process flows. These demonstrate use of the measurement at the process steps associated with extension and source/drain (SD) formation, on both bare and patterned wafers. Correlation is shown to SIMS, SRP, sheet resistance, and transistor and test structure electrical measurements.     

Shallow source/drain extensions for deep submicron MOSFETs using spin-on-dopants

Spin-on-dopants and rapid thermal processing have been used to form ultra-shallow n/sup +/-p junctions with metallurgical junction depths as shallow as 12 nm as determined by secondary ion mass spectroscopy. The electrical junction depth and the total charge concentration have been measured in the vicinity of the junction using electron holography and are shown to be consistent with activation efficiencies of 80%. The ultra-shallow junctions have been used as the source and drain contacts of sub-100-nm gate length MOSFETs. From electrical measurements, the authors extract a lateral diffusion length for the source and drains that is comparable to the vertical extent of the n/sup +/-p junctions.     

The influence of Ge-implantation on the electrical characteristicsof the ultra-shallow junction formed by using silicide as a diffusionsource

The electrical characteristics of ultra-shallow p⁺/n junctions formed by implanting a 60 keV Ge⁺ into a TiSi₂ layer have been studied. A very low reverse leakage current density (≅0.4 nA/cm² at -5 V) and a very good forward ideality factor n (≅1.001) were achieved in these ultra-shallow p ⁺/n junctions. From the secondary ion mass spectrometry (SIMS) analysis, the junction depth was measured to be 600 Å and the surface concentration was about 3 times higher than that of the conventional samples     

Effect of rapid thermally nitrided titanium films contacting silicided and nonsilicided junctions

The effect of rapid thermally nitrided titanium films contacting silicided (titanium disilicided) and nonsilicided junctions has been studied in the temperature range of 800 to 900°C. The rapid thermal nitridation of titanium films used as diffusion barriers between aluminum and silicon, has a major impact on shallow junction complementary metal oxide semiconductor technologies. During the process of rapid thermal nitridation, the dopants in the junctions undergo a redistribution and affect the electrical properties of shallow junction structures. This work focuses on using novel contact resistance structures to measure the variation in electrical parameters for rapid thermally nitrided titanium films annealed at different temperatures. The self-aligned silicide (salicide) junctions in this study were formed using rapid thermally annealed titanium films. Electrical contact resistance testers were used to measure the interface contact resistance between the salicide and silicon, as well as between the metal and the salicide. The results show that the interface contact resistance to the p⁻ diffused salicided junctions increases with rapid thermal nitridation of the additional titanium film, whereas the interface contact resistance to the n⁻ diffused salicided junction shows a decrease. Further, as a function of the rapid thermal annealing temperature (for fixed titanium thickness), the nonsalicided diffusions show an increase in the interface contact resistance. The boron profiles at the TiSi₂/Si interface obtained using secondary ion mass spectroscopy show an excellent qualitative agreement with the electrical results for each of the conditions discussed. The films were also characterized using Rutherford back-scattering spectrometry and transmission electron microscopy and the results show good agreement with the measured variation in electrical parameters. These results also show that as the anneal temperature is increased, the TiN thickness increases, further the change in the silicide/silicon interface position with the nitridation of the additional titanium layer was verified. This work was carried out when the author was working at AT&T Bell Labs     

Study of base series resistance losses in single and double emitter silicon solar cells through simulations and experiments

This work focuses on base series resistance influence on the performance of single and double emitter rear point contact silicon solar cells. This study is performed through measurements on experimental devices with different rear contact sizes and spacings, which were designed and fabricated using standard silicon integrated circuit technology, while the results were compared with simulation data based on a 3D model developed at our institute. Simulation and experimental results show that the series resistance of the double junction structure is significantly lower compared to the single junction equivalent. In addition, it was demonstrated that the operation of both junctions under slightly different voltages improves device efficiency. Copyright © 2008 John Wiley & Sons, Ltd.     

Photoinduced Contact Evolution and Junction Rearrangement in Two-Dimensional van der Waals Heterostructure

Devices based on 2DMs van der Waals (vdW) heterostructures always compose of multiple contacts. Due to the instability of nanoscale 2DMs and interfaces, these contacts can be affected by the operation-induced photo or thermal effect. They can trigger the evolution of junctions and rearrange the junctions across a device, which are detrimental for applications. Herein, vdW heterostructure of indium selenide (InSe) and black phosphorus (BP) on Au electrodes are investigated to reveal the contact evolution and its relation to device performance. During operation, light irradiation changes the I–V characteristics from symmetry to strong rectification. Photocurrent mapping and Kelvin-probe force microscopy (KPFM) reveal triple junctions in this heterostructure, i.e., Au-InSe junction, InSe homojunction, and InSe-BP heterojunction. The variation of I–V characteristics of vdW heterostructure is ascribed to the evolution of Au-InSe junction from quasi-ohmic junction with a near-zero work function difference (Δφ) to a strong Schottky junction (Δφ = ≈0.27 eV). The stabilized device demonstrates distinguished time-domain response at individual junctions and overall device, indicating the evolution of contacts and the consequent opposite junction directions degrade the overall device performance. This research emphasizes the importance of dealing with heterogeneous contacts and junction directions in designing vdW heterostructure photodetectors.     

Plasma doping for ultra-shallow junctions

Plasma doping (PD) processes utilizing PH₃/He and B₂H₆/He plasmas to fabricate CMOS devices are presented. The applications of PD in ultra-shallow junctions are discussed. Low contamination levels and good device characteristics have been achieved. Based on its superior features such as low cost, high throughput, very low implant energy, low contamination, etc., this novel doping technique has been demonstrated as a good candidate for the next generation microelectronics.     

Controllable Switching between Highly Rectifying Schottky and p–n Junctions in an Ionic MoS2 Device

Semiconductor junctions are of great significance for the development of electronic and optoelectronic devices. Here, controllable switching is demonstrated from a Schottky junction to a p–n junction in a partially ionic liquid-gated MoS₂ device with two types of metal contacts. Excellent rectification behavior with a current on-off ratio exceeding 10⁶ is achieved in both Schottky and p–n junction modes. The formation of Schottky junction at the Pd electrode/MoS₂ contact and p–n junction at the p-MoS₂/n-MoS₂ interface is revealed by spatially resolved photocurrent mappings. The switching between the two junctions under ionic gate modulation is correlated with the evolution of the energy band, further validated by the finite element simulation. The device exhibits excellent photodetection properties in the p–n junction mode, including an open circuit voltage up to 0.84 V, a responsivity of 0.24 A W⁻¹, a specific detectivity of 1.7 × 10¹¹ Jones, a response time of hundreds of microseconds and a linear dynamic range of up to 91 dB. The electric field control of such high-performance Schottky and p–n junctions opens up fresh perspectives for studying the behavior of junction and the development of 2D electronic devices.     

Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS

Source/drain (S/D) engineering for ideal box-shaped junction formation using laser annealing (LA) combined with pre-amorphization implantation (PAI) is proposed and implemented in device integration for sub-100-nm CMOS on an SOI substrate. Modeling analysis for the resistance component associated with junction profile abruptness demonstrates that a noticeable reduction in parasitic series resistance with technology generation can be achieved through junction profile slope engineering. From the experimental results of LA, it is found that PAI not only controls the ultrashallow junction depth precisely, but also reduces the laser energy fluence required for impurity activation. In addition, laser annealing energy can be further reduced by use of SOI substrates in the device integration, indicating the implementation feasibility of LA to CMOS integration with an enlarged process window margin. The proposed S/D engineering is verified by the sheet resistance of junctions and the fabricated device current characteristics exhibiting substantially improved short-channel performance with higher current capability due to the box-shaped junction profile as compared with conventional rapid thermally-annealed (RTA) devices.     

Integrity of shallow junction CMOS structures with Ti/TiN/Al---Si---Cu and Ti/TiN/Al---Cu contact metallization

Shallow junction complementary metal oxide semiconductor (CMOS) structures (0.25 and 0.35 μm depth) were studied using sputter deposited Ti/TiN/Al---Si---Cu and Ti/TiN/Al---Cu films for contact metallization. Single contact Van de Pauw patterns (to measure the breakdown voltage) as well as large junction area structures with multiple contact windows were used for electrical measurements. An increase in the RTA temperature used to silicide the contacts increased the Si consumption in the junctions and resulted in degradation of junctions yields. The thickness of the Ti layer had a larger influence on the stability of the junction than the thickness of the TiN layer (in the range of thicknesses studied). Al---Si(0.75 wt%)---Cu(0.5 wt%) films are more stable than Al---Cu(0.5 wt%) films for junction spiking. The Al---Cu films are more reactive, and the interdiffusion of Ti into the Al---Cu films makes the junctions less stable. The annealing temperature and post wafer fabrication is critical in maintaining stability of junctions. The junction depths, and dopants (BF₂-p- and As n-implanted) used in forming the junctions affect the breakdown voltages and junction yields. The BF₂ implanted junctions are more stable than arsenic implanted junctions.     

Arsenic Junction Thermal Stability and High-Dose Boron-Pocket Activation During SPER in nMOS Transistors

In this letter, thermal stability of arsenic (As) junctions formed by solid-phase epitaxial regrowth and their impact on device performance are investigated. If the temperature does not exceed 800 degC, a 35% junction sheet-resistance improvement over the conventional rapid thermal anneal is observed. The overlap junction resistance is not degraded and transistors, processed exclusively with lowly doped drain junctions, show a significant performance gain. High boron (B)-pocket dose leads to good transistor short-channel effect control, overcoming the B deactivation issue. The impact of B-pocket-related counterdoping and channel-mobility degradation on device characteristics are investigated. In the presence of heavily doped substrates, band-to-band tunneling is the dominant mechanism driving the reverse-bias junction leakage and is higher than the trap-assisted tunneling contribution related to the end-of-range defects     

Very-high-speed silicon bipolar transistors with in-situ dopedpolysilicon emitter and rapid vapor-phase doping base

We present a detailed study of the performance of very-high-speed silicon bipolar transistors with ultra-shallow junctions formed by thermal diffusion. Devices are fabricated with double-polysilicon self-aligned bipolar technology with U-groove isolation on directly bonded SOI wafers to reduce the parasitic capacitances. Very thin and low resistivity bases are obtained by rapid vapor-phase doping (RVD), which is a vapor diffusion technique using a source gas of B₂H₆. Very shallow emitters are formed by in-situ phosphorus doped polysilicon (IDP) emitter technology with rapid thermal annealing (RTA). In IDP emitter technology, the emitters are formed by diffusion from the in-situ phosphorus doped amorphous silicon layer. Fabricated transistors are found to have ideal I-V characteristics, large current gain and low emitter resistance for a small emitter. Furthermore, a minimum ECL gate delay time of 15 ps is achieved using these key techniques. Analyses of the high performance using circuit and device simulations indicate that the most effective delay components of an ECL gate are cut-off frequency and base resistance. A high cut-off frequency is achieved by reducing the base width and active collector region. In this study, RVD is used to achieve both high cut-off frequency and low base resistance at the same time     

Process limitation and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF₂, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi ₂ p⁺/n and n⁺/p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi₂ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n⁺/p and p⁺/n junctions with junction depths of 0.12 to 0.20 μm below the TiSi₂. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 μm can be fabricated with such junctions