Programmable interconnects speed system verification

A family of CMOS integrated circuits called field programmable interconnect components (FPICs) that can provide designers with the high-density interconnect architectures for making programmable hardware a reality is discussed. The FPIC devices address a broad spectrum of interconnect needs, including system prototypes and breadboards, user-specific/configurable printed circuit boards (PCBs), application configurable processors, test interfaces, and programmable connector and switching matrix applications. Using FPIC devices for system prototyping, in conjunction with other programmable components (programmable logic devices (PLDs), field programmable gate arrays (FPGAs), microprocessors, microcontrollers, DSP, and programmable memory) enhance the design verification process, allowing faster, more flexible, and thorough product integration. Field programmable circuit boards (FPCBs) designed to take advantage of the high density interconnect and observability of FPIC devices and a FPIC/FPCB development environment are described     

On the use of interpolated second-order polynomials for efficientfilter design in programmable downconversion

Interpolated second-order polynomials (ISOPs) are proposed to design efficient cascaded integrator-comb (CIC)-based decimation filters for a programmable downconverter. It is shown that some simple ISOPs can effectively reduce the passband droop caused by CIC filtering with little degradation in aliasing attenuation. In addition, ISOPs are shown to be useful for simplifying halfband filters that usually follow CIC filtering. As a result, a modified halfband filter (MHBF) is introduced which is simpler than conventional halfband filters. The proposed decimation filter for programmable downconverter is a cascade of a CIC filter, an ISOP, MHBFs, and a programmable finite impulse response filter. A procedure for designing the decimation filter is developed. In particular, an optimization technique that simultaneously designs the ISOP and programmable FIR filters is presented. Design examples demonstrate that the proposed method leads to more efficient programmable downconverters than existing ones     

A variable threshold voltage inverter for CMOS programmable logiccircuits

A programmable input threshold voltage inverter compatible with double gate transistors fabrication processes is presented. Such a circuit is useful as a programmable input threshold buffer for general purpose circuits that can he included In both TTL and CMOS environments, or can be used as low cost analog programmable comparator. A prototype is fabricated and measured     

Eddy Current Brakes for Haptic Interfaces: Design, Identification, and Control

We describe the design of an eddy current brake for use as programmable viscous damper for haptic interfaces. Unlike other types of programmable brakes, eddy current brakes can provide linear, programmable physical damping that can be modulated at high frequency. These properties makes them well suited as dissipative actuators for haptic interfaces. We overview the governing physical relationships, and describe design optimization for inertial constraints. A prototype haptic interface is described, and experimental results are shown that illustrate the improvement in stability when simulating a stiff wall that is made possible using programmable eddy current dampers.      

Design and implementation of a delay-optimized universal programmable routing circuit for FPGAs

This paper presents a universal field programmable gate array (FPGA) programmable routing circuit,focusing primarily on a delay optimization. Under the precondition of the routing resource's flexibility and routability, the number of programmable interconnect points (PIP) is reduced, and a multiplexer (MUX) plus a BUFFER structure is adopted as the programmable switch. Also, the method of offset lines and the method of complementary hanged end-lines are applied to the TILE routing circuit and the I/O routing circuit, respectively. All of the above features ensure that the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. Meanwhile, the BUFFER driver is optimized to decrease the signal delay by up to 5%. The proposed routing circuit is applied to the Fudan programmable device (FDP) FPGA, which has been taped out with an SMIC 0.18-μm logic 1P6M process. The test result shows that the programmable routing resource works correctly, and the signal delay over the chip is highly uniform and predictable.     

Multidomain Network Based on Programmable Networks: Security Architecture

This paper proposes a generic security architecture designed for a multidomain and multiservice network based on programmable networks. The multiservice network allows users of an IP network to run programmable services using programmable nodes located in the architecture of the network. The programmable nodes execute codes to process active packets, which can carry user data and control information. The multiservice network model defined here considers the more pragmatic trends in programmable networks. In this scenario, new security risks that do not appear in traditional IP networks become visible. These new risks are as a result of the execution of code in the programmable nodes and the processing of the active packets. The proposed security architecture is based on symmetric cryptography in the critical process, combined with an efficient manner of distributing the symmetric keys. Another important contribution has been to scale the security architecture to a multidomain scenario in a single and efficient way.     

Requirements of a Middleware for Managing a Large, Heterogeneous Programmable Network

Programmable networking is an increasingly popular area of research in both industry and academia. Although most programmable network research projects seem to focus on the router architecture rather than on issues relating to the management of programmable networks, there are numerous research groups that have incorporated management middleware into the programmable network router software. However, none seem to be concerned with the effective management of a large heterogeneous programmable network. The requirements of such a middleware are outlined in this paper. There are a number of fundamental middleware principles that are addressed in this paper; these include management paradigms, configuration delivery, scalability and transactions. Security, fault tolerance and usability are also examined—although these are not essential parts of the middleware, they must be addressed if the programmable network management middleware is to be accepted by industry and adopted by other research projects.     

基于现场可编程门阵列的数控延时器的设计

给出一种基于现场可编程门阵列(FPGA)的数控延时器的设计方法.首先详细介绍使用计数器的串联实现可控延时的方法,接着讨论不同延时范围下该数控延时器的改进方案,最后分析延时误差及延时精确度.延时器的外部接口仿照AD9501设计.     

支持未来网络创新的可编程虚拟化路由器技术

未来互联网体系结构、协议、算法需要在试验网络中进行评估与验证。可编程虚拟化路由器是构建未来互联网试验床的核心设备。由可编程虚拟化路由器构建的试验床可以在一个物理网络上构建多个独立虚拟网络,实现不同体系结构并行实验验证。相比传统路由器,可编程虚拟化路由器需要具备虚拟化与灵活可编程的特点。文章给出一种支持未来网络创新的可编程虚拟化路由器平台——PEARL。PEARL具有可编程、虚拟化隔离与高性能的特点,可满足未来互联网试验床建设要求。     

程控滤波器

为了适应工程应用中幅度和频率变化范围很宽的信号,设计了一种增益、频响特性和截止频率可程控的程控滤波器。系统以单片机和FPGA为控制核心,由可控增益放大、程控滤波、椭圆滤波、频率特性测试4部分组成。其中,可控增益放大部分以AD603为核心,级联三路固定增益放大;程控滤波部分巧妙地将两个二阶状态变量滤波级联,并将DAC等效为数控电阻,使得截止频率可调。实验结果表明,整个系统工作稳定,可以很好的实现程控滤波的功能。     

单次可编程金属-分子-金属器件

提出了一种单次可编程的金属-分子-金属器件. 该器件利用一种经过改良的Rotaxane LB膜作为功能层,可以和应用于场编程门阵列电路中的无机反熔丝器件相比拟,将在有机可编程电路和容错电路等方面有较广泛的应用. 所有的加工工艺都是低温工艺,使得该器件可以和其他有机器件集成. 电学测试表明该器件有良好的单次编程能力,其击穿电压为2.2V,关态电阻为15kΩ,而开态电阻为54Ω. 据分析,这一特性是由非对称的电极结构和金属原子在高电场作用下穿透了分子薄膜所造成的.     

A field programmable analog array for CMOS continuous-time OTA-Cfilter applications

A programmable high-frequency operational transconductance amplifier (OTA) is proposed and analyzed. A general configurable analog block (CAB) is presented, which consists of the proposed programmable OTA, programmable capacitor and MOSFET switches. Using the CABs, the universal tunable and field programmable analog array (FPAA) can be constructed, which can realize many signal-processing functions, including filters. A tuning circuit is also discussed. The proposed OTA has been simulated and fabricated in CMOS technology. The results show that the OTA has the transconductance tunable/programmable in a wide range of 700 times and the -3-dB bandwidth larger than 20 MHz. A universal 5×8 CAB array has been fabricated. The chip has also been configured to realize OTA-C 60-kHz and 500-kHz bandpass filters based on ladder simulation and biquad cascade     

An improved stator flux estimation for speed sensorless stator fluxorientation control of induction motors

This paper proposes a programmable low pass filter (LPF) to estimate stator flux for speed sensorless stator flux orientation control of induction motors. The programmable LPF is developed to solve the DC drift problem associated with a pure integrator and a LPF. The pole of the programmable LPF is located far from the origin in order to decrease the time constant with the increasing speed. In addition, the programmable LPF has a phase/gain compensator to estimate exactly stator flux in a wide speed range. Consequently, the drift problem is much improved and the stator flux is exactly estimated in the wide speed range. The validity of the proposed programmable LPF is verified by speed sensorless vector control of a 2.2 kW three-phase induction motor     

Microwave photonic filter with tunability, reconfigurability and bipolar taps

A new microwave photonic filter structure realising fully programmable RF filtering that can tune the filter centre frequency and also reconfigure the filter shape, while exhibiting multiple taps and bipolar taps, is presented. It is based on a new arbitrary spectrum slicing technique using a multi-port programmable wavelength processor, based on liquid crystal on silicon pixels, which offers programmable finite impulse response filtering using software control. Experimental results demonstrate a high-order microwave filter with tunability, reconfigurability, bipolar taps, and with high free spectral range.     

Hierarchical interconnection structures for field programmable gatearrays

Field programmable gate arrays (FPGA's) suffer from lower density and lower performance than conventional gate arrays. Hierarchical interconnection structures for field programmable gate arrays are proposed. They help overcome these problems. Logic blocks in a field programmable gate array are grouped into clusters. Clusters are then recursively grouped together. To obtain the optimal hierarchical structure with high performance and high density, various hierarchical structures with the same routability are discussed. The field programmable gate arrays with new architecture can be efficiently configured with existing computer aided design algorithms. The k-way min-cut algorithm is applicable to the placement step in the implementation. Global routing paths in a field programmable gate array can be obtained easily. The placement and global routing steps can be performed simultaneously. Experiments on benchmark circuits show that density and performance are significantly improved     

基于可编程超表面的Wi-Fi信号调控

可编程超表面是由可调谐的单元在二维平面上组成的平面阵列,具有任意、动态操控电磁波波前的能力,是微波领域前沿研究方向之一.尽管目前基于可编程超表面的电磁调控研究已取得丰硕进展,但是现有技术都需要采用专用发射源主动馈电超表面,这不仅增加了实际系统的复杂性和成本,而且在一定程度上限制了这些技术在现实环境中的应用.因此,该文提...     

程控滤波器

为了适应工程应用中幅度和频率变化范围很宽的信号,设计了一种增益、频响特性和截止频率可程控的程控滤波器。系统以单片机和FPGA为控制核心,由可控增益放大、程控滤波、椭圆滤波、频率特性测试4部分组成。其中,可控增益放大部分以AD603为核心,级联三路固定增益放大;程控滤波部分巧妙地将两个二阶状态变量滤波级联,并将DAC等效为数控电阻,使得截止频率可调。实验结果表明,整个系统工作稳定,可以很好的实现程控滤波的功能。     

基于SRAM配置技术的FPGA测试方法研究

在FPGA的设计生产过程中,FPGA的测试是一个至关重要的环节.分析了基于SRAM配置技术的FPGA的结构组成及FPGA的基本测试方法.针对6000门可编程资源的FPGA,提出了一种基于阵列和长线线与测试CLB以及采用总线测试开关矩阵相结合的方法.该方法较利用与门或门传递错误信息的所需测试配置次数减少了一半,从而加快了测试速度.     

延迟优化的统一可编程互连电路设计和实现

本文设计了一种对可编程逻辑单元CLB和可编程输出单元IOB均具有统一结构的可编程互连电路。通过偏移互连线和回线技术,使得同种可编程互连线的负载分布均匀,保证了可编程逻辑器件FPGA芯片中信号传输的可预测性和规整性;同时,设计过程中对编程点和驱动器电路进行专门的优化设计,减少了5%延时。运用该互连电路到实例FPGA芯片--FDP芯片中,流片后实测数据表明：该可编程互连电路中各种互连线功能正确,可以正确地完成各种信号的互连,整个芯片的延迟统一而且可预测。     

Digitally programmable accurate current sources for logarithmiccontrol of the amplification or attenuation in a gain cell

A method for realizing current sources driving a current equal to a programmable fraction of a reference current is discussed. The multiplication factor is determined by the digitally programmable power of a selected radix that is set by the ratio between the areas of two emitters. The number of identical current sources can be expanded a virtually unlimited amount without loss of accuracy or an increase in complexity. Several applications are possible; here, however, the focus is on applying this technique to digitally programmable logarithmic amplifiers or attenuators. A radix of 1.122 allows a gain cell to be programmed in decibel steps