100V高压CMOS工艺关键技术的研究

提出了一种新的双栅氧(dual gate oxide,DGO)工艺,有效提高了薄栅氧器件与厚栅氧器件的工艺兼容性,同时提高了高低压器件性能的稳定性.在中国科学院微电子研究所0.8μm n阱标准CMOS工艺基础上设计出高低压兼容的100V高压工艺流程,并流片成功.实验结果表明,高压n管和高压p管的关态击穿电压分别为168和-158V,可以在100V高压下安全工作.     

双栅氧CMOS工艺研究

双栅氧工艺(dual gate oxide)在高压CMOS流程中得到了广泛的应用,此项工艺可以把薄栅氧器件和厚栅氧器件集成在同一个芯片上.文章介绍了常用的两种双栅氧工艺步骤并分析了它们的优劣.在此基础上,提出了一种实现双栅氧工艺的方法.     

用于200V电平位移电路的薄层SOI高压LDMOS

文章基于1.5μm厚顶层硅SOI材料,设计了用于200 V电平位移电路的高压LDMOS,包括薄栅氧nLDMOS和厚栅氧pLDMOS。薄栅氧nLDMOS和厚栅氧pLDMOS都采用多阶场板以提高器件耐压,厚栅氧pLDMOS采用场注技术形成源端补充注入,避免了器件发生背栅穿通。文中分析了漂移区长度、注入剂量和场板对器件耐压的影响。实验表明,薄栅氧nLDMOS和厚栅氧pLDMOS耐压分别达到344 V和340 V。采用文中设计的高压器件,成功研制出200 V高压电平位移电路。     

Self-aligned maskless chan stops for IGFET integrated circuits

Many IGFET integrated circuits incorporate a region of enhanced doping under the field oxide to eliminate the possibility of spurious inversion layers causing leakage between devices. Using chemical predeposition technology, this typically requires a photolithographic step to define the region of enhanced doping. This paper describes a structure in which a nonselective implantation that forms an enhanced doping over the entire wafer is selectively compensated through windows patterned in the field oxide to form gate oxide regions. Threshold voltage control is excellent and identical to control devices fabricated without chan stops. The channel hole mobility is normal and no undesirable effects have been observed if care is exercised in controlling the implanted doses. MOS characteristics are normal and are not affected by residual ion damage. Typical parameters for p-channel devices are shown for various levels of compensation, resulting in gate threshold voltages ranging from -0.5 →-2.2 V for p-channel devices. The field threshold is -18.V for a 7000 Å thick field oxide and hole mobilities range from 190 to 290 cm²/V.s.     

Output buffer for +3.3 V applications in a 180 nm +1.8 V CMOS technology

A new output buffer realized with low-voltage (+1.8 V) devices to drive high voltage signals for +3.3 V interface, such as peripheral component interconnect extended (PCI-X) applications in a 180 nm CMOS process is proposed in this paper. As PCI-X is a +3.3 V interface, the high voltage gate–oxide stress poses a serious problem to design PCI-X I/O circuits in a 180 nm CMOS process. The performance of the proposed output buffer is examined using Cadence software and the model parameters of a 180 nm CMOS process. The experimental results have hither to confirm that the proposed output buffer can be successfully operated at 100 MHz frequency without suffering high voltage gate–oxide overstress in the +3.3Vinterface.Anew level converter realized with +1.8Vdevices that can convert 0/1Vvoltage swing to 0/3.3 V voltage swing is also presented in this paper. The simulation results have confirmed that the proposed level converter can be operated accurately without any voltage drop. The topology, however, reports low sensitivity and has features suitable for VLSI implementation. The proposed circuits are suited for low power design without performance degradation.     

90nm pMOSFET脱耦等离子体制备氮氧化硅的负偏压温度失稳性(英文)

MOSFET器件继续微缩则闸极氧化层厚度将持续减小,在0.13μm的技术闸极二氧化硅的厚度必须小于2nm,然而如此薄的氧化层直接穿透电流造成了明显的漏电流。为了降低漏电流,二氧化硅导入高浓度的氮如脱耦等离子体氮化制备氮氧化硅受到高度重视。然而,脱耦等离子体氮化制备氮氧化硅的一项顾虑是pMOSFET负偏压温度的失稳性。在此研究里测量了脱耦等离子体氮化制备氮氧化硅pMOSFET负偏压温度失稳性,并且和传统的二氧化硅闸电极比较,厚度1.5nm的脱耦等离子体氮化制备氮氧化硅pMOSFET和厚度1.3nm的二氧化硅pMOSFET经过125℃和10.7MVcm的电场1h的应力下比较阈值电压,结果显示脱耦等离子体氮化制备氮氧化硅pMOSFET在负偏压温度应力下性能较差。在15%阈值电压改变的标准下,延长10年的寿命,其最大工作电压是1.16V,可以符合90nm工艺1V特操作电压的安全范围内。     

单片集成GaAs增强／耗尽型赝配高电子迁移率晶体管

介绍了单片集成GaAs增强／耗尽型赝配高电子迁移率晶体管（PHEMT）工艺。借助栅金属的热处理过程,形成了热稳定性良好的Pt／Ti／Pt／Au栅。AFM照片结果表明Pt金属膜表面非常平整,2nm厚度膜的粗糙度RMS仅为0．172nm。通过实验,我们还得出第一层Pt金属膜的厚度和退火后的下沉深度比大概为1：2。制作的增强型／耗尽型PHEMT的闽值电压（定义于1mA／mm）、最大跨导、最大饱和漏电流密度、电流增益截止频率分别是＋0．185／-1．22V、381．2／317．5mS／mm、275／480mA／mm、38／34GHz。增强型器件在4英寸圆片上的阈值电压标准差为19mV。     

90 nm pMOSFET脱耦等离子体制备氮氧化硅的负偏压温度失稳性

MOSFET器件继续微缩则闸极氧化层厚度将持续减小,在0.13μm的技术闸极二氧化硅的厚度必须小于2 nm,然而如此薄的氧化层直接穿透电流造成了明显的漏电流.为了降低漏电流,二氧化硅导入高浓度的氮如脱耦等离子体氮化制备氮氧化硅受到高度重视.然而,脱耦等离子体氮化制备氮氧化硅的一项顾虑是pMOSFET负偏压温度的失稳性.在此研究里测量了脱耦等离子体氮化制备氮氧化硅pMOSFET负偏压温度失稳性,并且和传统的二氧化硅闸电极比较,厚度1.5 nm的脱耦等离子体氮化制备氮氧化硅pMOSFET和厚度1.3 nm的二氧化硅pMOSFET经过125℃和10.7MV/cm的电场1 h的应力下比较阈值电压,结果显示脱耦等离子体氮化制备氮氧化硅pMOSFET在负偏压温度应力下性能较差.在15%阈值电压改变的标准下,延长10年的寿命,其最大工作电压是1.16 V,可以符合90 nm工艺1 V特操作电压的安全范围内.     

双栅氧LDMOS器件工艺技术的研究与改进

双栅氧LDMOS器件刻蚀过程中极易造成多晶硅残留现象,降低了栅极和源区之间的击穿电压.改进了制备双栅氧LDMOS器件的方法,对于70 nm以下的栅氧厚度,采用保留整个厚栅氧器件区域栅氧的刻蚀方法,同时用一次多晶工艺代替二次多晶工艺,消除了多晶硅残留现象,减少了工艺步骤,提高了成品率;对于厚度大于70 nm或者100 nm的厚栅氧器件,除了以上的改进措施,还增加了一步光刻工艺,分别单独形成高压和低压器件的源漏区域.通过这些方法,解决了多晶残留问题,得到了性能更好的LDMOS器件,大大提高了成品率.     

Improved high-voltage lateral RESURF MOSFETs in 4H-SiC

High-voltage lateral RESURF metal oxide semiconductor field effect transistors (MOSFETs) in 4H-SiC have been experimentally demonstrated, that block 900 V with a specific on-resistance of 0.5 Ω-cm² . The RESURF dose in 4H-SiC to maximize the avalanche breakdown voltage is almost an order of magnitude higher than that of silicon; however this high RESURF dose leads to oxide breakdown and reliability concerns in thin (100-200 nm) gate oxide devices due to high electric field (>3-4 MV/cm) in the oxide. Lighter RESURF doses and/or thicker gate oxides are required in SiC lateral MOSFETs to achieve highest breakdown voltage capability     

Elimination of surface state induced edge transistors in high voltage NMOSFETs for flash memory devices

The abnormal leakage failure in high voltage NMOSFETs is investigated by measuring the subthreshold hump characteristics. Gated diode, width and substrate bias dependence of the I_D-V_GS characteristics, and two-terminal I-V measurements between the source and the drain reveal that the hump characteristic is caused by the surface states, not by the gate field crowding at STI edges. The numerical calculation shows that the high voltage NMOSFETs are very delicate to leakage failure by a small amount of surface state (10¹¹ /cm²), due to the thick gate oxide and very low doping concentration for high voltage operation (>25 V). A thermal oxidation with the thickness of 1.0 nm successfully eliminates the parasitic corner transistors without changing electrical characteristics of the targeted transistors in current state of the art flash memory devices.     

Effects of ionizing radiation on SOI/CMOS Devices fabricated in zone-melting-recrystallized Si films on SiO2

The effects of ionizing radiation on SOI/CMOS devices fabricated in zone-melting-recrystallized Si films on SiO2-coated Si substrates have been investigated as a function of the negative bias applied to the substrate during irradiation and measurement. For these devices, which have a thin gate oxide 10 nm thick, the optimum substrate bias is - 5 V. For total doses up to 10⁷rad(Si), with this bias they exhibit low subthreshold leakage currents (<0.2-pA/µm channel width), small threshold voltage shifts (<-0.18 V for n-channel devices and <-0.46 V for p-channel devices) and very little transconductance degradation (<5 percent).     

薄膜SOI上大于600 V LDMOS器件的研制

针对600 V以上SOI高压器件的研制需要,分析了SOI高压器件在纵向和横向上的耐压原理。通过比较提出薄膜SOI上实现高击穿电压方案,并通过仿真预言其可行性。在埋氧层为3μm,顶层硅为1.5μm的注氧键合(Simbond)SOI衬底上开发了与CMOS工艺兼容的制备流程。为实现均一的横向电场,设计了具有线性渐变掺杂60μm漂移区的LDMOS结构。为提高纵向耐压,利用场氧技术对硅膜进行了进一步减薄。流片实验的测试结果表明,器件关态击穿电压可达600 V以上(实测832 V),开态特性正常,阈值电压提取为1.9 V,计算开态电阻为50Ω.mm2。     

0.18-μm fully-depleted silicon-on-insulator MOSFET's

High-performance 0.18-μm gate-length fully depleted silicon-on-insulator (FD-SOI) MOSFET's were fabricated using 4-nm gate oxide, 35-nm thick channel, and 80-nm or 150-nm buried oxide layer. An elevated source/drain structure was used to provide extra silicon during silicide formation, resulting in low source/drain series resistance. Nominal device drive currents of 560 μA/μm and 340 μA/μm were achieved for n-channel and p-channel devices, respectively, at a supply voltage of 1.8 V. Improved short-channel performance and reduced self-heating were observed for devices with thinner buried oxide layers     

GaAs-MISFETs with insulating gate films formed by direct oxidation and by oxinitridation of recessed GaAs surfaces

Direct oxidation by an ultraviolet (UV) and ozone process and oxinitridation (plasma nitridation after oxidation) of GaAs surfaces were used to form nanometer-scale gate insulating layers for depletion-type recessed gate GaAs-MISFETs. The drain current-drain voltage characteristics of the oxide gate devices exhibit lower transconductance (max. 40 mS/mm), lower breakdown voltage and smaller gate capacitance than the oxinitrided gate devices. The presence of hysteresis in the oxide gate devices is also apparent. The maximum transconductance of the oxinitrided gate devices is 110 mS/mm and they have a sharper pinch-off, compared to the oxide gate devices. In addition, no hysteresis is observed in their current voltage curves. The current gain cutoff frequency of 1.4 /spl mu/m gate-length FETs for both types is 6 GHz. These results correspond well with results obtained from characterization of these insulating films.     

氧分压对铟镓锌氧薄膜晶体管性能影响

采用标准的液晶显示屏基板制备工艺制备出铟镓锌氧薄膜晶体管(IGZO-TFT),通过调节IGZO薄膜工艺中氧分压,研究不同氧分压对TFT器件电学性能的影响。实验结果表明,所有器件都展现出良好的电学特性,随着氧分压从10%增加到50%,TFT的阈值电压由0.5 V增加到2.2 V,而亚阈值摆幅没有发生变化。在栅极施加30 V偏压3600 s后,随着氧分压的增加,阈值电压向正向的漂移量由1 V增加到9 V。经过分析得出高氧分压的IGZO-TFT器件中载流子浓度低,建立相同导电能力的沟道时所需要栅极电压会更大,阈值电压会增加。而在金属-绝缘层-半导体(MIS)结构中低载流子浓度会导致有源层能带弯曲的部分包含更多与电子陷阱相同的能态,栅介质层(GI)会俘获更多的电子,造成阈值电压漂移量较大的现象。     

栅氧化层制程对IC产品可靠性的影响

栅氧化层变薄的趋势使得栅氧化层制程对IC产品可靠性的影响成为业界关注的焦点之一。在0.18μm工艺的基础上,针对6V器件对应的氧化层,设计了两种不同的栅氧化层生长方式,并对这两种方法生长的栅氧化层进行了电压扫描的可靠性测试验证,并结合失效分析的结果对氧化层质量进行了分析。实验结果表明,将湿氧法(WGO)与高温氧化物沉积(HTO)工艺相结合,极大地提高了栅氧化层厚度的均匀性,增强了产品可靠性。     

DC-DC降压芯片使能保护电路的设计

文中主要对DC-DC降压芯片电路进行研究,重点设计了使能保护电路模块。该电路模块设计了1.5 V和2.5 V两个比较电压点。当UEN小于1.5 V,整个芯片关断。当UEN超过1.5 V但小于2.5 V时,电源供电正常。当使能UEN大于2.5 V后,整个芯片正常工作。电路采用CMSC1μm5 V/40 V HVCMOS工艺中的5 V低压器件来构建,并在Cadence软件下进行了仿真验证。     

Plasma-induced micro breakdown in small-area MOSFETs

We investigated the impact of latent plasma-induced damage (PID) on the reliability of nMOSFETs with small gate area and gate-oxide thickness of 3.2 nm. To this purpose, we stressed 1500 devices with different antenna areas by using a staircase-like stress voltage and by monitoring the gate leakage at the gate voltage V/sub G/=+2 V. The stress was always stopped because of an abrupt jump in the gate current. The statistics obtained for the breakdown current are characterized by two different oxide-breakdown modes. The first is the well-known hard breakdown (HB), while the second one, which we called micro breakdown (MB), can be modeled as a double trap-assisted tunneling (D-TAT) mechanism and is characterized by a very small leakage current (around 100 pA at the gate voltage V/sub G/=2 V). In devices with large antenna, i.e., more prone to be damaged by plasma processing, the number of microbroken oxides is larger and breakdown occurs at lower voltages than in reference devices (non plasma damaged). Conversely, the hard breakdown statistics shows only a weak dependence on the gate antenna ratio of plasma damaged devices. This has been explained by considering the intrinsic nature of latent plasma-induced oxide defects, linked to the different generation mechanisms involved in micro breakdown and hard breakdown phenomena.     

Fabrication of 4H-SiC n-channel IGBTs with ultra high blocking voltage

Owing to the conductivity modulation of silicon carbide (SiC) bipolar devices,n-channel insulated gate bipolar transistors (n-IGBTs) have a significant advantage over metal oxide semiconductor field effect transistors (MOSFETs) in ultra high voltage (UHV) applications.In this paper,backside grinding and laser annealing process were carried out to fabricate 4H-SiC n-IGBTs.The thickness of a drift layer was 120 μm,which was designed for a blocking voltage of 13 kV.The n-IGBTs carried a collector current density of 24 A/cm2 at a power dissipation of 300 W/cm2 when the gate voltage was 20 V,with a differential specific on-resistance of 140 mΩ·cm2.