Lead-Free Solder Films Via Novel Solution Synthesis Routes

We report two novel routes, sol-gel and electroless plating, for the synthesis of lead-free solders. Novel processes with these routes were developed and demonstrated for Sn-Ag-Cu, Sn-Ag systems to achieve thin bonding layers for assembly of fine pitch integrated circuits onto substrates. Sol-gel route can be used to accurately control the final alloy composition and incorporate additives leading to the designed thermomechanical properties. In this process, the inorganic polymer solutions were spin coated and then heat-treated in a reducing atmosphere to form thin films of lead-free solders. The presence of Ag and Cu enabled easy reduction of tin oxide to tin at 400degC that was not possible with Sn precursor. With the alternate solution reduction (electroless plating) approach, bonding layers can be deposited at almost room temperatures directly on organic substrates. With this approach, the deposition selectively occurs on the metal bonding pads, which eliminates the need for any lithography. Using this approach, electroless Sn-Ag films were demonstrated on organic laminates. These thin film synthesis routes can enable short interconnections that are critical for high density, high frequency, and embedded active component packaging.     

Intermetallic Formation of Copper Pillar With Sn–Ag–Cu for Flip-Chip-On-Module Packaging

Copper pillar interconnects are a popular interposing option due to the advantages of small pillar size and good thermal and electrical performance, making copper pillar interconnects very useful for high-frequency and high-density flip-chip-on-module (FCOM) packages. However, the challenges associated with the technology include controlling the formation of brittle intermetallic compounds (IMC) and weak interfaces during heat-related processes, and preventing copper migration during bonding and reliability testing. As the reliability of the joint is significantly affected by the property of the surface finish, it is important to understand the influence of different surface finishes on the reliability of copper pillar interconnections. This paper focuses on Ni/Au-capped, Sn-capped, Sn–2.5Ag-capped, and organic solderability preservative (OSP)-capped copper pillar interconnections with lead-free Sn–3.0Ag–0.5Cu solder paste in FCOM packages. The types, morphology, and distribution of IMC formed in the bulk solder, the copper pillar/SAC, and copper pad/ENIG/SAC interfaces during multiple reflows ( 265 $~^{circ}{hbox {C}}$ ) and reliability testing [thermal cycle (TC), autoclave (AC), high-temperature storage (HTS), and thermal shock ([TS)] were investigated using a scanning electron microscope with energy dispersive X-ray (SEM-EDX). The feasibility and reliability of these copper-pillar FCOM systems were also compared and evaluated. The reliability results show that OSP-capped copper pillar interconnects are the best interposing option in terms of reliability and performance.      

Low-k compatible all-copper flip-chip connections

A novel fabrication technique using electroless copper deposition has been used to produce all-copper, chip-to-substrate connections. This process replaces solder by electrolessly joining copper pillars on the chip and substrate. The electroless copper joints were annealed at 180 °C after plating. A model was developed to explore methods for lowering the stress within the copper pillar, especially at the point where the pillar intersects the chip surface. The acceptable stress level within the copper pillars is a function of the on-chip dielectric material and the on-chip interconnect structures. In order to avoid fracture of the on-chip dielectric, the stress in the copper pillars should be less than the current lead-free solders that the all-copper pillars would be replacing. A polymer collar surrounding the copper pillars was used to support the pillars and improves thermo-mechanical reliability. The improvement in stress-reduction, ultimately leading to higher reliability was studied as a function of elastic modulus of the polymer collar support. It has been shown that the pillar stress generated during temperature cycling can be reduced by increasing the modulus of the pillar support and changing the shape of the copper pillars. Finally, three high-contrast photodefinable collar materials were characterized and tested. Nano-indentation experiments were performed to measure the mechanical properties of each material and shear tests were performed to verify the benefits of the higher elastic modulus collars.     

Wafer-Lever Hermetic Package with Through-Wafer Interconnects

This paper reports a new wafer-level hermetic packaging structure with the features of low processing cost and high I/O density by using wet and dry sequentially etched through-wafer vias for the interconnects of a microelectro mechanical systems (MEMS) device. A thin Si wafer cap and wafer-level fabrication processes such as deep reactive ion etching (DRIE) and KOH etching, bottom-up copper filling, and Sn solder bonding were adopted. The hermeticity and bonding strength of the structure are evaluated. Preliminary results show that the hermeticity can meet the requirement of the criterion of MIL-STD 883E, method 1014.9, and the bonding strength is up to 8 MPa.     

Hygrothermal Failures From Small Defects in Lead-Free Solder Reflowed Electronic Packages

Steam-driven delamination failure is a main failure mode in electronics packages during solder reflow. Steam pressures built up within interfaces in packages are sensitive functions of the reflow temperature. The switch to lead-free soldering will raise re-flow temperature by more than 20degC and double the equilibrium saturated steam pressure within defects in the package. The effects of saturated steam driven interfacial failure was analyzed using finite element in this study. Analyses revealed that packages which are thin and made using high thermal conductivity materials are at higher risk of failure than conventional packages made using standard materials. This suggests that electronics made with thick and inexpensive encapsulants are less prone to failure when switched to lead-free solder. Portable and mobile electronics which have low profiles and are made of high thermal conductive encapsulants are at higher risk when switched to lead-free solder reflow. Moreover, the study found that the critical temperature for failure is dependent on the defect size in the package. Reduction of initial defect size can reduce failures in high risk packages in lead-free solder reflow.     

印制板通孔上晕圈产生的原因

论述了制造多层电路板时,通孔上晕圈产生的原因主要是氧化铜膜的溶解,通过对氧化铜膜的还原、腐蚀和化学镀铜等方法可以抑制晕圈的产生。     

Localized Ligand Induced Electroless Plating (LIEP) Process for the Fabrication of Copper Patterns Onto Flexible Polymer Substrates

The “ligand induced electroless plating (LIEP) process” is a simple process to obtain localized metal plating onto flexible polymers such as poly(ethylene terephtalate) and polyvinylidene fluoride sheets. This generic and cost‐effective process, efficient on any common polymer surface, is based on the covalent grafting by the GraftFast process of a thin chelating polymer film, such as poly(acrylic acid), which can complex copper ions. The entrapped copper ions are then chemically reduced in situ and the resulting Cu⁰ species act as a seed layer for the electroless copper growth which, thus, starts inside the host polymer. The present work focuses on the application of the LIEP process to the patterning of localized metallic tracks via two simple lithographic methods. The first is based on a standard photolithography process using a positive photoresist masking to prevent the covalent grafting of PAA in designated areas of the polymer substrate. In the second, the patterning is performed by direct printing of the mask with a commercial laser printer. In both cases, the mask was lifted off before the copper electroless plating step, which provides ecological benefits, since only the amount of copper necessary for the metallic patterning is used.     

表面镀铜悬浮厚单晶硅螺线MEMS电感

报道了一种由悬浮在玻璃衬底上的表面镀铜平面单晶硅螺线构成的新型MEMS电感,可消除衬底损耗及减小电阻损耗.采用一种硅玻璃键合-深刻蚀成型释放工艺并结合无电镀技术制作该电感,形成厚约40μm的硅螺线,在硅螺线表面镀有高保形厚铜镀层,在铜镀层表面镀有起钝化保护作用的薄镍镀层.该电感的自谐振频率超过15GHz,在11.3GHz下,品质因子达到约40,电感值超过5nH.基于该电感的简化等效电路模型,采用一种特征函数法进行了参数提取,模拟结果与测量结果符合得很好.     

45 nm芯片铜互连结构低k介质层热应力分析

采用铜互连工艺的先进芯片在封装过程中,铜互连结构中比较脆弱的低介电常数(k)介质层,容易因受到较高的热机械应力而发生失效破坏,出现芯片封装交互作用(CPI)影响问题.采用有限元子模型的方法,整体模型中引入等效层简化微小结构,对45 nm工艺芯片进行三维热应力分析.用该方法研究了芯片在倒装回流焊过程中,聚酰亚胺(PI)开口、铜柱直径、焊料高度和Ni层厚度对芯片Cu/低κ互连结构低κ介质层应力的影响.分析结果显示,互连结构中间层中低κ介质受到的应力较大,易出现失效,与报道的实验结果一致;上述四个因素对芯片低κ介质中应力影响程度的排序为:焊料高度＞PI开口＞铜柱直径＞Ni层厚度.     

细间距图形电路无氰化学镀金工艺研究

采用市售无氰化学金工艺在线宽/间距(50μm/50μm)精细图形电路表面化学镀金。镀层表面均匀一致,厚度可达2μm以上,无镀金层溢出现象。新的化学镀金工艺作为微带板可焊性表面处理技术之一,兼具可选择区域镀、可接触导通、良好的键合性能,能兼容各种助焊剂,对于细间距图形电路表面处理具有十分重要的意义。     

Interconnecting to aluminum- and copper-based semiconductors (electroless-nickel/gold for solder bumping and wire bonding)

Electroless nickel and immersion gold plating technologies (e-Ni/Au) have traditionally been used almost exclusively within the electronics industry to create a solderable surface on substrate materials, e.g. laminate boards. Recent advances in these plating technologies, along with the inherent low costs associated with electroless plating processes, have enabled the extension of their utilization into a variety of semiconductor applications, e.g. wafer level pad metallization. This paper describes the electroless nickel and immersion gold processes for both aluminum- and copper-based semiconductors. The nickel plating bath is a hypophosphite-based solution and the gold bath is a cyanide-free sulfate-based solution. For aluminum-based integrated circuits a zincation process is used to initiate nickel growth, and for copper, palladium is used to catalyze the surface. Tight control of the chemistries, equipment, and run-time process variables are required to ensure repeatability. Thin film Auger analysis of the as-plated films shows well-defined layers of high purity gold and nickel/phosphorous. Adhesion of the e-Ni/Au layers was evaluated by measuring the load required to shear I/O pads plated with tall nickel bumps. Integrity of the nickel was further evaluated by subjecting the structures to multiple temperature cycles and test for pad shear strength. Results show no degradation in shear load or failure mode.The deposition of nickel and gold onto the I/O pad surfaces enables the subsequent use of both wire bond and flip chip (lead-based and lead-free alloys) interconnect methods. The integrity of gold wire bonds to the e-Ni/Au plated I/O pad was evaluated using ball shear, wire pull, and the corresponding failure analysis of each. Results show values well above product specifications, with wire pull failure modes in the wire and intermetallic failure in the ball shear studies. For flip chip applications, the e-Ni/Au layer was evaluated using stencil-printing technology to deposit several different solder alloys. In the current investigation, two test vehicles were successfully bumped with both 63Sn/37Pb and 90Pb/10Sn lead-based solder alloys, as well as the 95.5Sn/3.8Ag/0.7Cu lead-free alloy. In order to evaluate the compatibility of these alloys with the electroless nickel layer, solder bump shear tests were performed as a function of number of reflow cycles. Results show no degradation in shear load or failure mode among all three of the alloys tested, indicating no critical nickel consumption (i.e., excessive intermetallic growth) during reflow. Additional tests were performed comparing nickel under-bump-metallurgy (UBM) thicknesses of 1, 2 and 5 μm. Again, no critical nickel consumption was detected.     

Thermosonic bonding of lead-free solder with metal bump for flip-chip bonding

While extensive research on the lead-free solder has been conducted, the high melting temperature of the lead-free solder has detrimental effects on the packages. Thermosonic bonding between metal bumps and lead-free solder using the longitudinal ultrasonic is investigated through numerical analysis and experiments for low-temperature soldering. The results of numerical calculation and measured viscoelastic properties show that a substantial amount of heat is generated in the solder bump due to viscoelastic heating. When the Au bump is thermosonically bonded to the lead-free solder bump (Sn-3%Ag-0.5%Cu), the entire Au bump is dissolved rapidly into the solder within 1 sec, which is caused by the scrubbing action of the ultrasonic. More reliable solder joints are obtained using the Cu/Ni/Au bump, which can be applied to flip-chip bonding.     

Review of Capabilities of the ENEPIG Surface Finish

Surface finishes are used to protect exposed copper metallization in printed circuit boards from oxidation and to provide a solderable surface on which to mount electronic components. While it is true that some people have called electroless nickel electroless palladium immersion gold (ENEPIG) a “universal finish” for a wide range of applications from wire bonding to solder interconnects, this paper provides a review of the current literature on ENEPIG and assesses its overall capabilities compared to other surface finishes. Gaps in understanding the performance of ENEPIG as a printed wiring board surface finish are identified and further testing is recommended.     

超声波在陶瓷基片化学镀铜中的作用研究

采用了将超声辅助化学镀铜工艺与传统化学镀铜工艺对比的方法，研究了超声波辅助处理在陶瓷基片化学镀铜（包括前处理）中的作用，结果表明：超声波辅助处理影响化学镀铜的全过程，具体体现为：超声波辅助除油及粗化处理有利于形成致密、表面平整度高的铜层、超声波辅助敏化和活化处理使铜层表面的平整度下降，超声波辅助处理对化学镀中铜的均匀沉积不利。同时分析了超声波辅助处理对沉积速率及铜层显微硬度的影响。     

Materials and Processes Issues in Fine Pitch Eutectic Solder Flip Chip Interconnection

New product designs within the electronics packaging industry continue to demand interconnects at shrinking geometry, both at the integrated circuit and supporting circuit board substrate level, thereby creating numerous manufacturing challenges. Flip chip on board (FCOB) applications are currently being driven by the need for reduced manufacturing costs and higher volume robust production capability. One of today's low cost FCOB solutions has emerged as an extension of the existing infrastructure for surface mount technology and combines an under bump metallization (UBM) with a stencil printing solder bumping process, to generate mechanically robust joint structures with low electrical resistance between chip and board. Although electroless Ni plating of the UBM, and stencil printing for solder paste deposition have been widely used in commercial industrial applications, there still exists a number of technical issues related to these materials and processes as the joint geometry is further reduced. This paper reports on trials with electroless Ni plating and stencil paste printing and the correlation between process variables in the formation of bumps and the shear strength of said bumps at different geometries. The effect of precise control of tolerances in squeegees, stencils and wafer fixtures was examined to enable the optimization of the materials, processes, and tooling for reduction of bumping defects     

化学镀镍镀钯浸金表面处理工艺概述及发展前景分析

随着电子封装系统集成度逐渐升高及组装工艺多样化的发展趋势,适应无铅焊料的化学镀镍镀钯浸金（ENEPIG）表面处理工艺恰好能够满足封装基板上不同类型的元件和不同组装工艺的要求,因此ENEPIG正成为一种适用于IC封装基板和精细线路PCB的表面处理工艺。ENEPIG工艺具有增加布线密度、减小元件尺寸、装配及封装的可靠性高、成本较低等优点,近年来受到广泛关注。文章基于对化学镍钯金反应机理的简介,结合对镀层基本性能及可靠性方面的分析,综述了ENEPIG表面处理工艺的优势并探讨了其发展前景。     

微波组件Al-Si封装材料表面改性工艺研究

对高硅铝合金进行表面改性工艺实验,工艺分步实施化学镀镍、电镀镍、电镀金步骤,得到的镀层表面光滑平整,没有明显的结瘤和夹杂,镀层经高温烘烤无起泡脱落现象,与对应的铅锡焊料具有良好的焊接性和焊接速度,焊接后长期放置不出现晶须。该工艺作为高硅铝合金可焊性表面处理技术之一,兼具可选择区域镀、可接触导通、良好的键合性能,能兼容各种助焊剂,对于铝基复合材料表面处理具有十分重要意义。     

Process development and adhesion behavior of electroless copper on liquid crystal polymer (LCP) for electronic packaging application

Liquid crystal polymer (LCP) has potentially a very wide application as substrate material in electronic packaging applications because of its unique advantages. The work in this paper was performed to realize the metallization of LCP for the purpose of board fabrication, and to study the adhesion between deposited copper and LCP. A homogenous electroless plated copper layer on LCP with 4 to 5 /spl mu/m thickness was achieved, while it increased up to 40 /spl mu/m with the subsequent electroplating. The timescale of etching, deposit ion rate, and pH value were gradually changing during the plating process and the influences on copper layer quality were investigated. The adhesion force of the copper-LCP layer system was measured by a shear-off-method. Scanning electron microscopy (SEM) was used to check the surface morphology after etching and the interface after shearing on both the backside of the copper layer and the LCP side. The relationship between the shear-off adhesion of copper and the time of chemical etching before plating was examined, and the optimal etching time is discussed. Heat treatment after plating was used, and it was shown that this significantly improved the adhesion strength.     

双面贴装电路板上BGA焊点的潜在失效机理

采用双面贴装回流焊工艺在FR4基板表面贴装Sn3.0Ag0.5Cu(SnAgCn)无铅焊点BGA器件,通过对热应力加速实验中失效的SnAgCu无铅BGA焊点的显微结构分析和力学性能检测,研究双面贴装BGA器件的电路板出现互连焊点单面失效问题的原因,单面互连焊点失效主要是由于回流焊热处理工艺引起的.多次热处理过程中,NiSnP层中形成的大量空洞是导致焊点沿(Cu,Ni)6Sn5金属间化合物层和Ni(P)镀层产生断裂失效的主要因素.改变回流焊工艺是抑制双面贴装BGA器件的印制电路板出现互连焊点单面失效问题的关键.     

CS-38新型印制电路板铜基上化学镀银工艺

介绍了一种在印制电路板铜基上化学镀银的新工艺CS-38,它是一种既可焊接又能键合（Bonding）并能有效取代热风整平（HASL）的新工艺。讨论了各组分及操作条件对镀银液及镀银层的影响,确定了最佳配方和操作工艺。结果表明：该工艺镀银液稳定．防变色能力强,特适合规模化生产。