一种对三维芯片中硅通孔进行完整建模与寄生参数提取的有效方法

针对三维芯片中硅通孔（through-silicon via, TSV）的准确电学建模问题,本文提出了一种电阻电容（RC）电路模型以及相应的有效参数提取技术。该电路模型同时考虑了半导体效应与静电场影响,适合于低频与中频的电路信号范围。该方法采用一种基于悬浮随机行走（floating random walk, FRW）算法的静电场电容提取技术,然后将它与刻画半导体效应的MOS电容结合,形成等效电路模型。与Synopsys公司软件Sdevice所采用的对静电场/半导体效应进行完整仿真的方法相比,本文方法计算效率更高,并且也能处理一般的TSV电路版图。对多个含TSV的结构进行了计算实验,结果验证了本文方法在从10KHz到1GHz频率范围内的建模准确性,也显示出它相比Sdevice方法最多有47倍的加速比。     

类同轴TSV的高频电学模型与分析

类同轴硅通孔(TSV)是射频三维(3D)集成电路(IC)中常用的垂直互连传输结构。针对该结构提出了一套通用的电阻-电感-电容-电导(RLCG)寄生参数计算公式,以及对应的高频等效电路模型。寄生参数是结构尺寸和材料特性的函数,可以方便地用于预测电学性能。使用三维全波仿真软件对所提出的模型进行了高达100 GHz的仿真验证,并分析了模型的散射参数与结构尺寸之间的关系。最后提出了特征阻抗的计算和优化方法,该方法可以为类同轴TSV的参数的确定提供参考。     

空心硅通孔的设计及其传输性能

硅通孔(TSV)能够实现信号的垂直传输,是微系统三维集成中的关键技术,在微波毫米波领域,硅通孔的高频传输特性成为研究的重点。针对微系统三维集成中,无源集成的硅基转接板的空心TSV垂直传输结构低损耗的传输要求,进行硅通孔的互连设计和传输性能分析。采用传输线校准方式,首先在硅基转接板上设计TSV阵列接地的共面波导(CPW)传输线和带TSV过孔的传输结构,并分别进行仿真分析,计算得出带TSV过孔的传输结构的插入损耗;然后通过后道TSV工艺,在硅基转接板上制作传输线和带TSV过孔的传输结构,用矢量网络分析仪法测试传输线和带TSV过孔的传输结构的插入损耗;最后计算得到单个TSV过孔的插入损耗,结果显示在0.1～30 GHz频段内其插入损耗S21≤0.1 dB,实现了基于TSV的低损耗信号传输。     

基于物理结构的GaN HEMTs小信号等效电路的精确建模方法研究

为了有效地表征GaN HEMTs在微波频段下的电学特性,研究了其高频等效电路的精确建模方法。基于GaN HEMTs器件的本征物理结构,综合考虑器件在制版过程中由电极和通孔所带来的寄生特性,描述了一种具有26个详细参数网络的小信号等效电路模型。此模型考虑了器件在工作环境下所受到的集肤效应,同时通过对小信号等效电路进行双端口网络参数分析,推导了其准静态近似的微波等效电路参数直接提取的简化算法,最终通过ADS仿真平台将所建模型和传统模型的S参数模拟结果与实测数据的一致性进行对比,验证了小信号等效电路模型的精确性与参数提取算法的有效性。     

一种基于BSIM-CMG的FinFET变容管模型

提出了一种适用于FinFET变容管的建模方法.在BSIM-CMG的基础上,模型采用衬底模型和外围寄生模型来表征变容管的射频寄生效应.提出了具体的参数提取方法,将测试的S参数导入到安捷伦IC-CAP建模软件提取参数,测试结构引入高频寄生采用(open+ short)去嵌方法进行去嵌.通过调节模型参数拟合测试曲线得到FinFET变容管模型.该模型可精确表述FinFET变容管全工作区域特性,解决传统MOS变容管模型无法准确描述三维FinFET器件变容特性的问题.模型和模型参数提取方法采用20个硅鳍、16个栅指、158 nm栅长、578 nm栅宽的FinFET变容管进行建模验证,模型仿真和测试所得C-V,R-V和S参数特性吻合良好.     

使用传输线理论的硅通孔电参数提取方法

针对三维集成电路中的关键技术硅通孔的电特性,使用传输线理论提取了其单位长度RL-GC参数。将硅通孔等效为传输线,利用HFSS仿真结果并结合传输线理论给出了具体的参数提取方法。计算结果表明,硅通孔单位长度RLGC 参数呈现较强的频变特性,当频率从1 MHz增加到20 GHz时,单位长度的电阻和导纳分别从0.45 mΩ/μm和2.5μS/μm增加到2.5 mΩ/μm和17μS/μm,而单位长度电感和电容分别从8.7 pH/μm和8.8 fF/μm减小至7.5 pH/μm和0.2 fF/μm。与传统的阻抗矩阵和导纳矩阵提取方法相比,该方法具有结果绝对收敛和适用频率高等诸多优点,可进一步应用于三维集成电路的仿真设计。     

新型同轴型混合碳纳米管填充的硅通孔

针对碳纳米管填充的硅通孔(TSV)的信号传输性能优化问题,提出一种新型的基于同轴型混合碳纳米管填充的硅通孔结构.在内外层管束交界处的耦合电容的基础上,提出新型TSV结构的可变参数等效电路模型,并基于TSV在三种不同应用层次上的尺寸参数,通过此电路模型分析新型TSV中的信号传输性能.分析结果表明,在0～40 GHz内与单一类型碳纳米管填充的TSV相比,所提出TSV结构具有更小的插入损耗与更短的上升时延,并随TSV的尺寸增大优势更加显著.最后,对所提出TSV结构进行时域眼图仿真,仿真结果表明其在高速集成电路中可以满足对信号完整性的要求.     

VDMOS等效电路的SPICE模型

分析了VDMOS器件中存在的各种寄生效应以及这些寄生效应对器件性能的影响,在此基础上建立了VDMOS等效电路的SPICE模型.通过MEDICI数值分析软件,模拟VDMOS在不同偏置条件下的电压、电流、电容特性,从而提取出VDMOS等效电路模型参数.并用SPICE软件对等效电路仿真,进行了直流分析和瞬态分析,得到等效电路的电学特性曲线图.仿真的结果与MEDICI器件模拟工具模拟结果相互比较,具有较好的一致性.     

基于TSV的三维集成螺旋电感等效电路模型

基于硅通孔(TSV)技术,可以实现微米级三维无源电感的片上集成,可应用于微波/射频电路及系统的微型化、一体化三维集成。考虑到三维集成电路及系统中复杂、高密度的电磁环境,在TSV电感的设计和使用中,必须对其电路性能及各项参数指标进行精确评估及建模。采用解析方法对电感进行等效电路构建和寄生参数建模,并通过流片测试对模型进行了验证。结果表明,模型的S参数结果与三维仿真结果吻合良好,证实了等效电路构建的精确性。采用所建立的等效电路模型可以提高TSV电感的设计精度和仿真效率,解决微波电路设计及三维电磁场仿真过程中硬件配置要求高、仿真速度慢等问题。     

关于传输线等效集总电路模型的拓展教学

传输线的等效集总电路模型有助于理解和掌握传输线的基本概念,并可用于电特性的仿真分析。本文分别探讨了在教学过程中需拓展的两个重要知识点。其一,在高频工作情况下,需要对含有频变分布参数的传输线进行准确建模,获取相应的等效集总电路模型;其二,在分析多导体构成的耦合传输线时,等效集总电路模型同样值得探究。     

双根锥形硅通孔结构的精确RLGC电路模型

A fast RLGC circuit model with analytical expression is proposed for the dual tapered through-silicon via （TSV） structure in three-dimensional integrated circuits under different slope angles at the wide frequency region. By describing the electrical characteristics of the dual tapered TSV structure, the RLGC parameters are extracted based on the numerical integration method. The RLGC model includes metal resistance, metal inductance, substrate resistance, outer inductance with skin effect and eddy effect taken into account. The proposed analytical model is verified to be nearly as accurate as the Q3D extractor but more efficient.     

RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

3D integration including Through Silicon Vias is more and more considered as the solution to overcome conventional 2D IC issues. In this way, TSV analytical equivalent models are hardly required to achieve 3D products and to make design recommendations. In this paper, a 3D process flow is detailed and used to integrate specific RF structures including copper-filled TSVs with 3 μm wide and 15 μm deep dimensions. Both measurements and simulations of these structures lead to the extraction of frequency-dependent parameters and the building of a SPICE compatible π-shaped analytical parametrical model of the TSV.     

Capacitance characterization of tapered through-silicon-via considering MOS effect

In this paper, closed-form expression for the parasitic capacitance of tapered TSV (T-TSV) considering metal–oxide–semiconductor (MOS) effect is proposed by solving two-dimensional (2D) Poisson's equation. ANSYS Q3D Extractor is employed to verify the proposed model for the slope wall angle of 75°, 80°, 85° and 90°. It is shown that error is less than ~5%. The capacitance characterization of copper T-TSV is studied in detail, by taking slope wall angle of 80° for instance. The results show that the capacitance of T-TSV acts as that of MOS device in changing the bias voltage; the increases of the bottom radius of T-TSV (from 1 to 5 μm), dielectric liner thickness (from 0.1 to 0.5 μm), liner dielectric constant (from 1 to 5), T-TSV height (from 10 to 50 μm) and acceptor concentration (from 1×10¹⁵ to 5×10¹⁵ cm⁻³) cause increase of T-TSV capacitance by about 25 fF, −12 fF, 12 fF, 210 fF and 12 fF, respectively. Finally, the condition for T-TSV simplified to cylindrical TSV is obtained.     

基于环形振荡器的TSV故障非接触测试方法

为避免传统的探针检测对硅通孔(TSV)造成损伤的风险,提出了一种非损伤的TSV测试方法.用TSV作为负载,通过环形振荡器测量振荡周期.TSV缺陷造成电阻电容参数的变化,导致振荡周期的变化.通过测量这些变化可以检测TSV故障,同时对TSV故障的不同位置引起的周期变化进行了研究与分析,利用最小二乘法拟合出通过周期来判断故障位置的曲线,同时提出预测模型推断故障电阻范围.测试结构是基于45 nm PTM COMS工艺的HSPICE进行设计与模拟,模拟结果表明,与同类方法相比,此方法在测试分辨故障的基础上对TSV不同位置的故障进行分析和判断,并能推断故障电阻范围.     

Study on crosstalk characteristic of carbon nanotube through silicon vias for three dimensional integration

Coupling noise induced by through silicon vias (TSVs) is expected to be a major concern for three dimensional integrated circuits (3-D ICs) system design. Using equivalent electrical parameters for carbon nanotube (CNT) TSV interconnects, a lumped crosstalk noise model is introduced to capture the TSV-to-TSV coupling noise in CNT via based 3-D ICs and validated with multiple conductor transmission line (MTL) simulation results. The effect of geometrical and material parameters involved on the noise transfer function and peak crosstalk noise, such as insulation thickness, TSV–TSV spacing, TSV height, TSV radius, substrate conductivity and metallic CNT density, is investigated with the proposed model. Simulation results show that the TSV coupling can be divided into three frequency behavior regions. Three approaches using driver sizing, grounded vias shielding and air gap-based silicon-on-insulator (SOI) technique are proposed to mitigate TSV crosstalk coupling noise. The proposed approaches are demonstrated in frequency- and time- domain simulations. They provide the reduction in full-band noise transfer function by an average of 11.71 dB, 24.85 dB and 3.46 dB, and the decrease in 1 GHz peak noise voltage by 53.24 mV, 40.72 mV and 15.1 mV.     

Compact model to efficiently characterize TSV-to-transistor noise coupling in 3D ICs

A methodology is proposed to characterize through silicon via (TSV) induced noise coupling in three-dimensional (3D) integrated circuits. Different substrate biasing schemes (such as a single substrate contact versus regularly placed substrate contacts) and TSV fabrication methods (such as via-first and via-last) are considered. A compact π model is proposed to efficiently estimate the coupling noise at a victim transistor. Each admittance within the compact model is approximated with a closed-form expression consisting of logarithmic functions. The methodology is validated using the 3D transmission line matrix (TLM) method, demonstrating, on average, 4.8% error. The compact model and the closed-form expressions are utilized to better understand TSV induced noise as a function of multiple parameters such as TSV type, placement of substrate contacts, signal slew rate and voltage swing. The effect of differential TSV signaling is also investigated. Design guidelines are developed based on these results.     

Theoretical analysis and modeling of submicron channel length DMOStransistors

Previous analytical models of the DMOS transistor are inadequate at the shorter gate lengths, and can lead to spurious predictions of DMOS device behavior. To avoid such shortcomings, an improved DMOS model is proposed to better address DMOS performance issues. These include the identification of desirable device operating regimes and the examination of device frequency response. Increases in DMOS gate capacitance, which have previously been demonstrated only by computer simulation and device measurements, are now modeled analytically. Furthermore, in demonstrating the shortcomings of previous DMOS models, a universal condition for current saturation in MOS devices is derived. The derivation and applicability of the universal condition is independent of mobility model     

三维集成电路中硅通孔缺陷建模及自测试/修复方法研究

硅通孔(Through Silicon Via, TSV)是3维集成电路(3D IC)进行垂直互连的关键技术,而绝缘层短路缺陷和凸点开路缺陷是TSV两种常见的失效形式。该文针对以上两种典型缺陷建立了TSV缺陷模型,研究了侧壁电阻及凸点电阻与TSV尺寸之间的关系,并提出了一种基于TSV缺陷电阻端电压的检测方法。同时,设计了一种可同时检测以上两种缺陷的自测试电路验证所提方法,该自测试电路还可以级联起来完成片内修复功能。通过分析面积开销可得,自测试/修复电路在3D IC中所占比例随CMOS/TSV工艺尺寸减小而减小,随TSV阵列规模增大而减小。     

Air-gap-based RF coaxial TSV and its characteristic analysis

Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance （RLGC） model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6%0, on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6-4.0 times higher bandwidth than the con- ventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.     

Small-signal analysis of the gate-controlled diode

This paper describes the small signal behavior of MOS gate-controlled diodes. An expression for the capacitance of this device is developed from basic device physics equations. Computer calculations are compared with measured data and the model is seen to predict both the frequency and voltage dependence of the capacitance. The development of this model was made possible through the careful decomposition of teh basic MOS equations into time dependent and static parts.