Optimization of GaAs MESFET logic gates with subnanosecond propagation delays

This paper describes the optimization of logic gates using GaAs MESFETs. Nonlinear stored charges are evaluated, and propagation delays and power dissipations are computed for logic gates with and without load driver. The performances of these two circuit alternatives are compared, and parameter values are optimized to provide a minimum propagation delay for a given power allocation.     

Electron-beam fabrication of submicrometer gates for a GaAs MESFET logic

A direct electron-beam lithography is applied to the fabrication of a submicrometer gate for an enhancement-mode GaAs MESFET logic. Exposure doses to produce submicrometer stripes in the positive PMMA resist on a GaAs wafer are investigated for different beam scans of a 0.1-µm-diameter spot. The resist adhesion against a GaAs etchant under the gate recessing is tested to make a fine control of an epitaxial layer thickness with good results. A propagation delay of 64 ps with an associated power consumption of 0.4 mW is obtained with a 0.5 × 20-µm-gate GaAs MESFET, which demonstrates the fastest speed among the enhancement-mode logics.     

Direct measurement of picosecond propagation delays in individual logic gates by a differential optoelectronic technique

We describe the first direct measurement of single-gate propagation delays in gigabit GaAs digital IC's. Our technique uses picosecond light pulses to generate short on-chip logic-level-switched pulses and infers single logic gate delays by differential measurement of output waveforms. In the ∼ 2-GHz clock-rate D-flip-flop selected for these measurements, single-gate propagation delays of ∼ 100 ps were measured in specific NOR gates internal to the flip-flop (FF) with this new measurement technique; the technique is easily extendible to measurement of gate delays of the order of a few picoseconds.     

External stress effect on GaAs MESFET Characteristics

An experimental investigation has been carried out for clarifying the external mechanical stress effect on GaAs MESFET performance. The stress was induced by bending wafers. It was found that threshold voltage varied linearly with the applied stress. In the case of refractory-gate n+ self-aligned FET's (LG= 1 µm), the magnitude was about 10 mV for 2 × 10⁸-dyn/cm²stress change. The threshold voltage shift direction was opposite for [011]- and [011]-oriented FET's. These results were found to be caused by a change in refractory-gate electrode stress which produces piezoelectrical charge densities in the GaAs substrate.     

Three-dimensional beam propagation analysis of nonlinear opticalfibers and optical logic gates

A three-dimensional (3-D) beam propagation method is described for the analysis of nonlinear optical fibers, where the finite element and finite difference methods are, respectively, utilized for discretizing the fiber cross section and the propagation direction. For efficient evaluation of wide-angle beam propagation Pade approximation is applied to the differential operator along the propagation direction. In order to improve the efficiency and accuracy of solutions, isoparametric elements and numerical integration formulae derived by Hammer et al. are introduced. The propagation characteristics of nonlinear optical fibers with linear core and nonlinear cladding are analyzed, and unique features of nonlinear guided-wave propagation are investigated. Furthermore, all-optical logic gates with practical, 3-D geometry consisting of optical fibers and a nonlinear film are proposed, and their operations of Boolean arithmetic are demonstrated     

Proximity effect of dislocations on GaAs MESFET threshold voltage

Spatial inhomogeneity of semi-insulating LEC-grown GaAs is currently a subject of considerable attention, and there have been contradictory reports that dislocations affect FET threshold voltage either directly or indirectly. Careful measurements of the threshold voltage are carried out in the vicinity of cellular dislocation networks, lineages, and the densely dislocated wafer periphery, which are dislocation distributions peculiar to LEC-grown GaAs crystals. The measurements were made in an attempt to verify the proximity effect of dislocations on the threshold voltage. It is concluded that, even though there is still ambiguity at very close gate-to-pit distances, the proximity effect is apparently observed only when the gate-to-pit distance is less than about 50µm. A threshold voltage difference between dislocation-free and dislocated areas is also demonstrated.     

The effect of parasitic capacitances on the circuit speed of GaAs MESFET ring oscillators

Circuit parasitic capacitances for GaAs ring oscillators (RO's) were calculated and used for SPICE2 circuit simulation. The simulated delays agreed with the measured data to within ∼10 percent. The results indicate that the effect of the circuit parasitic capacitances are dominant in determining circuit speed for high-density IC's at the microwave frequency.     

GaAs MESFET自升温效应的分析

分析了ＧａＡｓＭＥＳＦＥＴ由于沟道电流功耗而引起的器件自升温效应。以基本的Ｐｏｉｓｏｎ方程、电流方程及热流方程为基础,采用二维数值分析法,确定了器件内部自升温效应下的温度分布特点,以及决定器件自升温幅度的主要因素。     

A large-signal, analytic model for the GaAs MESFET

An analytic, large-signal model for the GaAs MESFET is presented. The device model is physics-based and describes the conduction and displacement currents of the FET as a function of instantaneous terminal voltages and their time derivatives. The model allows arbitrary doping profiles in the channel and is thus suitable for the optimization of ion-implanted and buried-channel FETs. It also accounts for charge accumulation in the conducting channel at high electric fields and the associated capacitance in a self-consistent manner. Theoretical predictions of the model are correlated with experimental data on X -band power FETs and excellent agreement is obtained     

The synthesis method of logic circuits based on the iMemComp gates

The iMemComp is a family of logic gates based on RRAM devices. It has potential advantage on the design of high-performance logic circuits, since the NAND, AND, NOT and transmission iMemComp gates only consume single cycle, respectively. However, the synthesis method of logic circuits based on the iMemComp gates has not been systematically studied before. This work proposes the synthesis method of the row-oriented logic circuits based on the multi-input single-cycle iMemComp gates. The synthesis results show that the circuits generated from the proposed method outperform most of those RRAM based counterparts generated from the previous methods. Furthermore, the synthesis method of the array-oriented iMemComp logic circuits is proposed. The proposed array-oriented method generates the relatively high-performance logic circuits since both the row-based and the column-based single-cycle iMemComp gates are applied, and the generated circuits are relatively area-efficient because the intra-row and inter-row redundancies are utilized in the circuit mapping.     

半绝缘砷化镓及其MESFET器件光敏特性研究

用波长范围为 70 0～ 3 5 0 0 nm的光电流测试系统研究了 SI-Ga As衬底及其 MESFET器件中的深能级。结果显示在 SI-Ga As衬底及其 MESFET器件中存在着相似的深能级 ,衬底的深能级影响着器件的光敏等性能。还讨论了如何减少器件中光敏现象的方法。     

GaAs MESFET旁栅效应与旁栅距的关系研究

旁栅效应是影响 Ga As器件及电路性能的有害寄生效应。本文研究了旁栅阈值电压 Vth SG与旁栅距 LSG的关系 ,发现 Vth SG的大小与 LSG成正比关系 ,并理论探讨了产生这一现象的机制 ,从而验证了旁栅阈值电压与旁栅距关系的有关理论。     

GaAs MESFET栅取向效应中背栅的作用

根据压电效应模型,本文详细研究了压电电荷对GaAs MESFET沟道与衬底界面耗尽层的影响。认为正压电电荷比负压电电荷所引起的阀值电压漂移大,较好解释了(100)衬底上沿[011]和[011]取向的GaAs MESFET阈值电压非对称反向漂移的现象。     

BiCMOS三态输出门电路的设计、制备及应用

设计了几种BiCMOS三态输出门电路,提出了采用先进的0.5μm BiCMOS工艺,制备所设计的三态输出门的技术要点和器件参数,并分析了它们既具有双极型(Bipolar)门电路快速、大电流驱动能力,又具备CMOS逻辑门低压、低功耗和高集成度的特性,因而它们特别适用于高速缓冲数字信息系统和其它便携式数字设备中.     

Logic self-electrooptic effect devices: quantum-well optoelectronicmultiport logic gates, multiplexers, demultiplexers, and shift registers

Two-dimensional arrays of logic self-electrooptic effect devices (L-SEEDs), consisting of electrically connected quantum-well p-i-n diode detectors and modulators are demonstrated. The topology of the electrical connections between the detectors is equivalent to the connections between transistors in CMOS circuits. Three different L-SEED arrays were built and tested. Each element in one array can implement any of the four basic Boolean logic functions (i.e., NOR, NAND, AND, OR). Each element in the second L-SEED array can implement the function E=AB+CD. The third L-SEED array consists of 32×16 arrays of symmetric SEEDs (S-SEEDs) connected with optoelectronic transmission gates. Photonic switching nodes, multiplexers, demultiplexers, and shift registers have been demonstrated using this array     

Comparison of SiC, GaAs, and Si RF MESFET power densities

The maximum power density of Si, GaAs, and 4H-SiC MESFET's was modeled using material parameters, a planar MESFET cross section, and a piecewise linear MESFET drain characteristic. The maximum power density for the Si, GaAs, and 4H-SiC was calculated to be 0.45 W/mm, 0.78 W/mm, and 17.37 W/mm at drain voltages of 8.4 V, 8.3 V, and 105 V, respectively. Modeling power density as a function of drain voltage showed that, for low voltage applications, the GaAs MESFET has the highest power density because of its high electron mobility and very low channel resistance (R_on). For high voltage applications, the 4H-SiC MESFET has the highest absolute power density because of the higher breakdown voltage of this material. Experiment data agree qualitatively with the modeled results     

砷化镓衬底与MESFET中深能级研究

用波长范围为 70 0 nm到 350 0 nm的光电流测试系统研究了 SI- Ga As衬底、有源层和MESFET中的深能级。结果显示在 SI- Ga As衬底、有源层和 MESFET中的深能级有着较为密切的联系 ,这些深能级影响着器件的性能     

Si衬底上MBE GaAs MESFET与IC制备

叙述在MBE(分子束外延)GaAs/Si材料上制作GaAs MESFET与Ic的研究。考虑到GaAsIC与Si IC单片集成的需要,采用了Ti/TiW/Au肖特基金属化和Ni/AuGe/Ni/Au欧姆接触金属化,层间介质采用等离子增强淀积氮化硅和聚酰亚胺复合材料。在该工艺基础上,制备了性能良好的GaAs/Si MESFET与IC。     

GaAs MESFET欧姆接触可靠性研究进展

报道了ｎ型ＧａＡｓ上欧姆接触的制备及其可靠性，以及基于欧姆接触退经的ＧａＡｓＭＥＳＰＥＴ的失效分析，结果表明，ｎ型ＧａＡｓ上欧姆接触的制备已日趋成熟，接触电阻有所减小，表面形貌及热稳定性方面都得到了很大程度的提高，接触材料也日趋丰富ＧａＡｓＭＥＳＦＥＴ的失效分析方法也有明显改进。