Feasibility study of a scalable optical interconnection network for massively parallel processing systems

The theoretical modeling of a novel topology for scalable optical interconnection networks, called optical multimesh hypercube (OMMH), is developed to predict size, bit rate, bit-error rate, power budget, noise, efficiency, interconnect distance, pixel density, and misalignment sensitivity. The numerical predictions are validated with experimental data from commercially available products to assess the effects of various thermal, system, and geometric parameters on the behavior of the sample model. OMMH is a scalable network architecture that combines positive features of the hypercube (small diameter, regular, symmetric, and fault tolerant) and the mesh (constant node degree and size scalability). The OMMH is implemented by a free-space imaging system incorporated with a space-invariant hologram for the hypercube links and fiber optics to provide the mesh connectivity. The results of this work show that the free-space links can operate at 368 Mbits/s and the fiber-based links at 228 Mbits/s for a bit-error rate of 10(-17) per channel. The predicted system size for 32 nodes in the OMMH is 4.16 mm × 4.16 mm × 3.38 cm. Using 16-bit, bit-parallel transmission per node, the system can operate at a bit rate of up to 5.88 Gbits/s for a size of 1.04 cm × 1.04 cm × 3.38 cm.     

Experimental demonstration of the optical multi-mesh hypercube: scaleable interconnection network for multiprocessors and multicomputers

A prototype of a novel topology for scaleable optical interconnection networks called the optical multi-mesh hypercube (OMMH) is experimentally demonstrated to as high as a 150-Mbit/s data rate (2(7) - 1 nonreturn-to-zero pseudo-random data pattern) at a bit error rate of 10(-13)/link by the use of commercially available devices. OMMH is a scaleable network [Appl. Opt. 33, 7558 (1994); J. Lightwave Technol. 12, 704 (1994)] architecture that combines the positive features of the hypercube (small diameter, connectivity, symmetry, simple routing, and fault tolerance) and the mesh (constant node degree and size scaleability). The optical implementation method is divided into two levels: high-density local connections for the hypercube modules, and high-bit-rate, low-density, long connections for the mesh links connecting the hypercube modules. Free-space imaging systems utilizing vertical-cavity surface-emitting laser (VCSEL) arrays, lenslet arrays, space-invariant holographic techniques, and photodiode arrays are demonstrated for the local connections. Optobus fiber interconnects from Motorola are used for the long-distance connections. The OMMH was optimized to operate at the data rate of Motorola's Optobus (10-bit-wide, VCSEL-based bidirectional data interconnects at 150 Mbits/s). Difficulties encountered included the varying fan-out efficiencies of the different orders of the hologram, misalignment sensitivity of the free-space links, low power (1 mW) of the individual VCSEL's, and noise.     

Incrementally scalable optical interconnection network with a constant degree and constant diameter for parallel computing

A new scalable interconnection topology called the spanning-bus connected hypercube (SBCH) that is suitable for massively parallel systems is proposed. The SBCH uses the hypercube topology as a basic building block and connects such building blocks by use of multidimensional spanning buses. In doing so, the SBCH combines positive features of both the hypercube (small diameter, high connectivity, symmetry, simple routing, and fault tolerance) and the spanning-bus hypercube (SBH) (constant node degree, scalability, and ease of physical implementation), while at the same time circumventing their disadvantages. The SBCH topology permits the efficient support of many communication patterns found in different classes of computation, such as bus-based, mesh-based, and tree-based problems, as well as hypercube-based problems. A very attractive feature of the SBCH network is its ability to support a large number of processors while maintaining a constant degree and a constant diameter. Other positive features include symmetry, incremental scalability, and fault tolerance. An optical implementation methodology is proposed for the SBCH. The implementation methodology combines the advantages of free-space optics with those of wavelength-division multiplexing techniques. An analysis of the feasibility of the proposed network is also presented.     

Time multiplexing and control for optical cellular-hypercube arrays

We discuss the cellular-hypercube optical free-space interconnection architecture and its implementation by two-dimensional smart-pixel optoelectronic cellular arrays. We emphasize the behavior of the cellular hypercube in performing shift-invariant parallel shifts of data, a basic requirement of most single-instruction multiple-data algorithms. We present a time-multiplexing scheme for realizing the cellular hypercube, showing that the communication time is inversely proportional to the number of optical detectors per cell. We also present an improved hybrid interconnection network with improved performance that combines the cellular hypercube and mesh, using optics for the longer-distance connections and electronics for nearest-neighbor connections.     

Optical binary de Bruijn networks for massively parallel computing: design methodology and feasibility study

The interconnection network structure can be the deciding and limiting factor in the cost and the performance of parallel computers. One of the most popular point-to-point interconnection networks for parallel computers today is the hypercube. The regularity, logarithmic diameter, symmetry, high connectivity, fault tolerance, simple routing, and reconfigurability (easy embedding of other network topologies) of the hypercube make it a very attractive choice for parallel computers. Unfortunately the hypercube possesses a major drawback, which is the complexity of its node structure: the number of links per node increases as the network grows in size. As an alternative to the hypercube, the binary de Bruijn (BdB) network has recently received much attention. The BdB not only provides a logarithmic diameter, fault tolerance, and simple routing but also requires fewer links than the hypercube for the same network size. Additionally, a major advantage of the BdB network is a constant node degree: the number of edges per node is independent of the network size. This makes it very desirable for large-scale parallel systems. However, because of its asymmetrical nature and global connectivity, it poses a major challenge for VLSI technology. Optics, owing to its three-dimensional and globalconnectivity nature, seems to be very suitable for implementing BdB networks. We present an implementation methodology for optical BdB networks. The distinctive feature of the proposed implementation methodology is partitionability of the network into a few primitive operations that can be implemented efficiently. We further show feasibility of the presented design methodology by proposing an optical implementation of the BdB network.     

Experimental free-space optical network for massively parallel computers

A free-space optical interconnection scheme is described for massively parallel processors based on the interconnection-cached network architecture. The optical network operates in a circuit-switching mode. Combined with a packet-switching operation among the circuit-switched optical channels, a high-bandwidth, low-latency network for massively parallel processing results. The design and assembly of a 64-channel experimental prototype is discussed, and operational results are presented.     

Electrophotonic computer networks with strictly nonblocking and self-routing functions

Three-stage optical interconnection networks for use in massively parallel processors are proposed. Wavelength-division- and space-division-multiplexing switches used in these networks are described, and free-space optics to assist in the construction of networks that are small and provide high throughput are discussed.     

Hierarchical optical ring interconnection (HORN): scalable interconnection network for multiprocessors and multicomputers

A new interconnection network for massively parallel computing is introduced. This network is called a hierarchal optical ring interconnection (HORN). The HORN consists of a single-hop, scalable, constant-degree, strictly nonblocking, fault-tolerant interconnection topology that uses wavelength-division multiple access to provide better utilization of the terahertz bandwidth offered by optics. The proposed optical network integrates the attractive features of hierarchical ring interconnections, e.g., a simple node interface, a constant node degree, better support for the locality of reference, and fault tolerance, with the advantages of optics. The HORN topology is presented, its architectural properties are analyzed, and an optical design methodology for it is described. Furthermore, a brief feasibility study of the HORN is conducted. The study shows that the topology is highly amenable to optical implementation with commercially available optical elements.     

Scalability analysis of diffractive optical element-based free-space photonic circuits for interoptoelectronic chip interconnections

An interchip free-space optical interconnection module is investigated to solve the pin-input-output bottleneck at the interface of silicon integrated circuits. The scalability of the photonic circuit is theoretically analyzed by use of the minimum feature size requirement of each diffractive element used. The study showed that interconnection densities of 1000-2000 channels/cm is possible for a 40-mm interconnection length with a 3-mm-thick optical substrate. Diffraction-limited imaging capability has been demonstrated using a fabricated prototype, confirming its applicability for interchip free-space interconnections. Photonic circuit insertion losses of -23.4 dB for TE polarization and -25.9 dB for TM polarization as well as a polarization-dependent loss of 2.5 dB are found to be caused primarily by a pair of binary linear gratings used for beam deflections. Design modifications aiming at insertion loss reduction and further improvement of tolerance capabilities are also discussed.     

256 × 256 Turnover-type free-space multichannel optical switch based on polarization control using liquid-crystal spatial light modulators

Free-space multichannel optical switches using polarization control are attracting interest for future telecommunication networks and interconnection networks in computers. We describe a switching architecture, the turnover type, for such free-space multichannel optical switches. The architecture makes it possible to realize a large-scale and transparent optical switch that is also compact. A 256 × 256 multichannel optical switch based on the architecture is designed and fabricated. To the authors' knowledge, the channel number of the fabricated switch is the largest yet reported among rearrangeable optical switches. Switching operation and signal transmission at 400 Mbits/s are performed successfully with a prototype switch.     

Free-space optical cross-connect switch by use of electroholography

An electrically controlled holographic switch is proposed as a building block for a free-space optical interconnection network. The switch is based on the voltage-controlled photorefractive effect in KLTN crystals at the paraelectric phase. It is built of electrically controlled Bragg gratings stored in the volume of the crystal. A compact switch that connects four high-speed fiber-optic communication channels with high efficiency is demonstrated experimentally. The switch performance is investigated and optimized. This switch is extremely attractive for cascaded switching arrays such as those found in multistage interconnect networks.     

Generalized methodology for modeling and simulating optical interconnection networks using diffraction analysis

Research in the field of free-space optical interconnection networks has reached a point where simulators and other design tools are desirable for reducing development costs and for improving design time. Previously proposed methodologies have only been applicable to simple systems. Our goal was to develop a simulation methodology capable of evaluating the performance characteristics for a variety of different free-space networks under a range of different configurations and operating states. The proposed methodology operates by first establishing the optical signal powers at various locations in the network. These powers are developed through the simulation by diffraction analysis of the light propagation through the network. After this evaluation, characteristics such as bit-error rate, signal-to-noise ratio, and system bandwidth are calculated. Further, the simultaneous evaluation of this process for a set of component misalignments provides a measure of the alignment tolerance of a design. We discuss this simulation process in detail as well as provide models for different optical interconnection network components.     

High-speed free-space interconnect based on optical ring topology: experimental demonstration

The design and implementation of a high-speed optical-ring-topology-based free-space optical interconnect is described. This interconnect system operates at 500 MHz and consists of 16 laser transmitters, a four-channel free-space interconnect, and a high-speed receiver. A nearest-neighbor interconnect is demonstrated. At the data rate of 500 MHz the total system throughput is 8 Gbits/s. The system can easily be operated at much higher data rates since the rate is limited only by the electronic circuitry. A discussion is given about device issues such as optical switching devices, and practical system-design issues such as integration and interface with current electronic systems are considered. This interconnect is promising to the implementation of ultrafast massively parallel single-instruction multiple-data machines.     

Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.     

Optoelectronic Systems Based on InGaAs- Complementary-Metal-Oxide-Semiconductor Smart-Pixel Arrays and Free-Space Optical Interconnects

Free-space optical interconnects have been identified as a potentially important technology for future massively parallel-computing systems. The development of optoelectronic smart pixels based on InGaAs/AlGaAs multiple-quantum-well modulators and detectors flip-chip solder-bump bonded onto complementary-metal-oxide-semiconductor (CMOS) circuits and the design and construction of an experimental processor in which the devices are linked by free-space optical interconnects are described. For demonstrating the capabilities of the technology, a parallel data-sorting system has been identified as an effective demonstrator. By use of Batcher's bitonic sorting algorithm and exploitation of a perfect-shuffle optical interconnection, the system has the potential to perform a full sort on 1024, 16-bit words in less than 16 mus. We describe the design, testing, and characterization of the smart-pixel devices and free-space optical components. InGaAs-CMOS smart-pixel, chip-to-chip communication has been demonstrated at 50 Mbits/s. It is shown that the initial system specifications can be met by the component technologies.     

Optoelectronic neural-network scheduler for packet switches

A novel, to our knowledge, type of packet scheduler that could significantly outperform current state-of-the-art schedulers is presented. The operation and the design of such a scheduler are discussed, and a fully operational experimental implementation is described. The scheduler uses a neural network in a winner-take-all strategy to optimize decisions on the throughput of both a crossbar and a banyan switching fabric. The problems of high interconnection density are solved by use of a free-space optical interconnect that exploits diffractive optical techniques to generate the required interconnection patterns and weights.     

Sliding-banyan network performance analysis

The sliding-banyan (SB) network employs an interleaved multistage shuffle-exchange topology, implemented with a three-dimensional free-space interconnection architecture that connects a multichip backplane to itself. Surface-normal emitters and detectors, which compose the stages' input-output, are spatially multiplexed within the same chip location, along with electronic control and switching resources. A simple deflection self-routing scheme minimizes internal contention, providing efficient use of switching and interconnection resources. The blocking performance of the SB is quantified through simulations based on realistic nonuniform traffic patterns. Results show that the SB architecture requires significantly fewer resources than other self-routing banyan-based networks. The multistage-switching and interconnection-resource requirements are close to the theoretical minimum for nonblocking networks, and the SB's distributed self-routing control resources grow only approximately linearly with the number of nodes, providing good scalability.     

Dynamic digital photorefractive memory for optoelectronic neural network learning modules

Neural network modules based on page-oriented dynamic digital photorefractive memory are described. The modules can implement two different interconnection organizations, fan-out and fan-in, depending on their target network applications. Neural network learning is realized by the real-time memory update of dynamic digital photorefractive memory. Physical separation of subvolumes in the page-oriented photorefractive memory architecture contributes to the low cross talk and high diffraction efficiency of the stored interconnection weights. Digitally encoded interconnection weights ensure high accuracy, providing superior neural network system scalability. Module scalability and feedforward throughput have been investigated based on photorefractive memory geometry and the photodetector power requirements. The following four approaches to extend module scalability are discussed: partial optical summation, semiparallel feedforward operation, time partitioning, and interconnection matrix partitioning. Learning capabilities of the system are investigated in terms of required interconnection primitives for implementing learning processes and three memory-update schemes. The experimental results of Perceptron learning network implementation with 900 input neurons with digital 6-bit accuracy are reported.     

一种可扩展的双层光互连网络设计与分析

本文设计一种具有可扩展性的双层并行光互连网络.顶层为数字路由结点和光网络接口卡组成的星型网,底层为光网络接口卡连接而成的环形网.结点机以及数字路由结点影响网络的性能.结点机的吞吐能力限制了整个网络的吞吐率;扩展PCI总线的位数能够提高光网络接口卡的吞吐速率,采用64bit/66MHz工作模式可获得4.224 Gbps峰值传输速率.网络的实际最大吞吐速率为8.448Gbps,环网内平均延迟2195ns,环网间平均延迟4713 ns.可以采用本文设计的数字路由结点对网络进行低成本级联扩展,扩展后网络性能显著提高.