共查询到19条相似文献,搜索用时 468 毫秒
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基于直接键合方法,通过约束性逐级低温退火实现了碳化硅与硅的低应力异质键合,得到了翘曲度小于5μm、平均应力约32 MPa、键合完整性极高的6英寸(1英寸=2.54 cm)晶圆。通过水接触角测试、红外图像检测、翘曲度和应力测试、扫描电子显微镜(SEM)、能量色散谱仪(EDS)等分析了键合结果,并采用“刀片法”测试其键合面的键合能。键合完成的晶圆具有键合完整性高、键合强度强、晶圆应力小等特点。通过对比晶圆表面材料、退火温度、退火方式等相关的实验结果,对该低应力异质键合技术的工艺原理进行了解释。该技术路线对Si和SiC的三维集成有重要意义,且该方法可以推广用于更多种类材料的低应力异质键合。 相似文献
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田芳 《电子工业专用设备》2013,42(1):5-7,42
论述了晶圆叠层3D封装中的典型工艺——晶圆键合技术,并从晶圆键合原理、工艺过程、键合方法、设备要求等方面对其进行了深入探讨;以期晶圆叠层3D封装能够应用到更加广泛的领域。 相似文献
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热压键合是垂直结构LED制备的关键工艺步骤,通过TEM,PL,Raman等测试手段,探讨热压键合造成的应力损伤、GaN材料缺陷、LED内量子效率以及反向漏电间的内在联系,研究以键合引起的应力诱导垂直结构GaN基LED光电特性的退化机制,探讨应力损伤对垂直结构GaN基LED光电特性的影响.实验结果表明,热压键合过程会在GaN材料内产生GPa量级的残余应力,在量子限制strark效应作用下,GaN材料辐射复合效率发生明显退化;同时热压键合应力还会诱发GaN材料位错密度的增加,最终导致LED反向漏电增大. 相似文献
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基于UV光照的圆片直接键合技术 总被引:1,自引:1,他引:1
研究了UV辅助活化与湿化学清洗活化相结合的圆片直接键合技术,并利用红外测试系统、单轴拉伸测试仪和场发射扫描电子显微镜,结合恒温恒湿实验、高低温循环实验对键合质量进行了测试.结果表明,采用该技术可以实现较好的圆片直接键合,提高键合强度,控制合适的UV光照时间可以获得更高的强度,对键合硅片进行恒温恒湿和高低温交变循环处理后,硅片仍能保持较高的键合强度.因此,该工艺对于改进圆片直接键合技术是行之有效的,具有很大的应用潜力. 相似文献
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Material integration by wafer bonding and layer transfer is one of the main approaches to increase functionality of semiconductor
devices and to enhance integrated circuits (IC) performance. Even though most mismatches such as different lattice constants
betweeen bonding materials present no obstacle for wafer direct bonding, thermal stresses caused by thermal mismatches must
be minimized by low temperature bonding to avoid debonding, sliding or cracking. In order to achieve a strong bond at low
temperatures, two approaches may be adopted: 1) Bonding at room temperature by hydrogen bonding of OH, NH, or FH terminated
surfaces followed by polymerization to form covalent bonds. Within this approach the key is to remove the by-products of the
reaction at the bonding interface. 2) Direct formation of a covalent bond between clean surfaces without adsorbents in ultra
high vacuum conditions. Low temperature bonding allows bonding processed wafers for technology integration. Layer transfer
requires uniform thinning of one wafer of a bonded pair. The most promising technology involves a buried embrittled region
by hydrogen implantation. A layer with a thickness corresponding to the hydrogen implantation depth is then transferred onto
a bonded desired substrate by either splitting due to internal gas pressure or by forced peeling as long as the bonding energy
is higher than the fracture energy in the embrittled region at the layer transfer temperature. This approach is quite generic
in nature and may be applied to almost all materials. We have found that B+H co-implantation and/or H implantation at high
temperatures can significantly lower the splitting temperature. However, the wafer temperature during H implantation has to
be within a temperature window that is specific for each material. The experimentally determined temperature windows for some
semiconductors and single crystalline oxides will be given. 相似文献
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The deposition rate, the etch rate in a HF-based solution and the residual internal stress of PECVD oxides are systematically analysed for various deposition conditions and post-anneal treatments. Rapid thermal anneal (RTA) at a temperature over 900 °C for 15 s is proven to be the most efficient to reduce the residual stress in the film and its etch rate in BHF solution, as well as to enhance its long term stability. The reduction of the internal stress in PECVD oxide is mandatory to minimize the wafer bow which degrades the wafer bonding quality. Bonded samples show that the resulting surface energy tends to vary inversely with the elastic energy stored by the conformation of the wafers during the direct bonding. About 45 μm wafer bow (3 inch wafer, 380 μm-thick) comes out as an upper bow limit, preventing direct bonding to occur. The use of a RTA step following the PECVD oxide layer deposition is demonstrated to be an efficient technological solution to minimize the wafer bow and thus maximize the bonding surface toughness. The experimental results presented in this paper highlight the importance of monitoring the residual stress in intermediate oxide layers to assure high quality and reliable bonding and thus future three-dimensional integration. 相似文献
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晶圆直接键合技术由于能将表面洁净的两个晶圆集成到一起,从而可以用来制备晶格失配 III-V族多结太阳电池。为了制备GaInP/GaAs/InGaAsP/InGaAs四结太阳电池,需采用具有低电阻率的GaAs/InP键合界面,从而实现GaInP/GaAs和InGaAsP/InGaA上下两个子电池的电学导通。我们设计并研究了具有不同掺杂元素和掺杂浓度的三种键合界面,并采用IV曲线对其电学性质进行表征。此外,对影响键合界面质量的关键工艺过程进行了研究,主要包括表面清洗技术和键合参数优化,例如键合温度、键合压力和键合时间等。最终制备出的键合四结GaInP/GaAs/InGaAsP/InGaAs太阳电池在AM0条件下效率最高达33.2%。 相似文献
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回顾了Si面键合技术的历史,研究了国外此工艺技术发展过程与趋势,分析了Si面直接键合技术的特点和它在压电与声光器件中的应用。 相似文献
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