RSYN: a system for automated synthesis of reliable multilevelcircuits

Conventional logic synthesis systems are targeted towards reducing the area required by a logic block, as measured by the literal count or gate count; or, improving the performance in terms of gate delays; or, improving the testability of the synthesized circuit, as measured by the irredundancy of the resultant circuit. In this paper, we address the problem of developing reliability driven logic synthesis algorithms for multilevel logic circuits, which are integrated within the MIS synthesis system. Our procedures are based on concurrent error detection techniques that have been proposed in the past for two level circuits, and adapting those techniques to multilevel logic synthesis algorithms. Three schemes for concurrent error detection in a multilevel circuit are proposed in this paper, using which all the single stuck at faults in the circuit can be detected concurrently. The first scheme uses duplication of a given multilevel circuit with the addition of a totally self-checking comparator. The second scheme proposes a procedure to generate the multilevel circuit from a two level representation under some constraint such that, the Berger code of the output vector can be used to detect any single fault inside the circuit, except at the inputs. A constrained technology mapping procedure is also presented in this paper. The third scheme is based on parity codes on the outputs. The outputs are partitioned using a novel partitioning algorithm, and each partition is implemented using a multilevel circuit. Some additional parity coded outputs are generated. In all three schemes, all the necessary checkers are generated automatically and the whole circuit is placed and routed using the Timberwolf layout package. The area overheads for several benchmark examples are reported in this paper. The entire procedure is integrated into a new system called RSYN     

Voltage Injection Method for Three-Phase Current Reconstruction in PWM Inverters Using a Single Sensor

This paper presents a voltage injection method for reconstructing phase currents from current signals measured on single current-shunt circuits with cost-effective and high-performance configurations in the pulsewidth modulation (PWM) inverters that are used for digital appliances. This method involves the injection of voltage signals at the carrier frequency for reconstructing the phase currents in PWM inverters using a single current sensor in the DC-link. It uses minimum signals to reduce the voltage and current harmonics caused by the injected signals. The vector of the injected voltage is at a minimum distance from the original reference to ensure the measurement time in the reconstruction of the phase currents. An injection sequence control method is also proposed to avoid an abrupt change in the injection signals. A PWM scheme for splitting phase voltages is proposed to reduce any audible noise, especially in low-speed operation. The proposed method reconstructs the phase currents with signals from a single current sensor and minimizes the amplitude of the injected signals to reduce the harmonics at audible noise frequencies in the injection signals. Experimental results showed the effectiveness of the proposed method.     

Operating Margin-Oriented Design Methods for Threshold Element-Based Reconfigurable Logic Circuits Realizing any Symmetric Function

This paper presents operating margin-oriented design methods for threshold element-based reconfigurable logic circuits (TREC) that can realize any symmetric function. The methods can generate circuits under restrictions that originate in electric and structural properties of physical threshold elements. The threshold element is implemented in a floating-gate circuit that calculates its weighted sum using the charge in the floating gate. The operating margins of the floating-gate circuit are an important factor for its reliable operation because of the use of multiple levels on the charge for the weighted sum. The proposed methods have the three main features. First, the methods guarantee that any symmetric function can always be realized independent of the number of input variables. A designed TREC comprising (k + 2) floating-gate inverters realizes one of 2^{(k + 1)} symmetric functions of k input variables, using binary (k + 1) control variables. Secondly, a unique circuit structure is determined by selecting the proper values for the parameters that characterize the floating-gate inverters. These values maximize the operating margins against variations and fluctuations in both the charge and the floating-gate threshold voltage. Lastly, the operating margins are illustrated with a graphical representation. We can obtain knowledge not only of the relationship between the margins, but also of the design trade-off between circuit performances and the margins for reliable operation. To demonstrate the effectiveness of the methodology, the TREC was designed and evaluated by circuit simulation. The proper operations necessary for realizing or changing any symmetric function were confirmed.     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology

NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection capability. All of them are usually based on a similar circuit scheme with multiple-stage inverters to drive the main ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage inverter and 1-stage inverter controlling circuits have been studied to verify the optimal circuit schemes in the NMOS-based power-rail ESD clamp circuits. Besides, the circuit performances among the main ESD clamp NMOS transistors drawn in different layout styles cooperated with the controlling circuit of 3-stage inverters or 1-stage inverter are compared. Among the NMOS-based power-rail ESD clamp circuits, an abnormal latch-on event has been observed under the EFT test and fast power-on condition. The root cause of this latch-on failure mechanism has been clearly explained by the emission microscope with InGaAs FPA detector.     

Modular log-domain filters realized using wave port terminators

Log-domain wave filters that simulate the passive LC ladder prototype filters are introduced in this paper. The proposed circuits are constructed from the wave equivalents of the reactive elements corresponding to those in the prototype circuit. The wave equivalent circuits are obtained by using a novel log-domain wave port terminator. The wave equivalent of a capacitor in a shunt branch was chosen as an elementary building block for creating high-order filters. The wave equivalent circuits of all other reactive elements in a shunt or in a series-branch connection can be readily obtained using the elementary building block plus some inverters. This way the derived high-order filter configurations are modular. A design example of a third-order elliptic low-pass filter is given, and the performance of the filter was verified by simulation.     

基于二分法量子可逆逻辑电路综合

 为了能以较小的代价自动高效地构造量子可逆逻辑电路,提出了一种新颖的量子可逆逻辑电路综合方法.该方法通过线拓扑变换和对换演算,利用递归思想,将n量子电路综合问题转换成单量子电路综合问题,从而完成电路综合,经过局部优化生成最终电路.该算法综合出全部的3变量可逆函数,未优化时平均需6.41个EGT门,优化后平均只需5.22个EGT门;理论分析表明,综合n量子电路最多只需要n2^n－1个EGT门.与同类算法相比,综合电路所用可逆门的数量大幅减少.同时该算法还避免了时空复杂度太大的问题,便于经典计算机实现.     

Modular implementation of efficient self-checking checkers for the Berger code

A technique for designing efficient checkers for conventional Berger code is proposed in this paper. The check bits are derived by partitioning the information bits into two blocks, and then using an addition array to sum the number of 1's in each block. The check bit generator circuit uses a specially designed 4-input 1's counter. Two other types of 1's counters having 2 and 3 inputs are also used to realize checkers for variable length information bits. Several variations of 2-bit adder circuits are used to add the number of 1's. The check bit generator circuit uses gates with fan-in of less than or equal to 4 to simplify implementation in CMOS. The technique achieves significant improvement in gate count as well as speed over existing approaches.     

基于概率表达式的MPRM电路功耗计算方法

采用基于信号概率的功耗计算模型进行MPRM（Mixed Polarity Reed-Muller）电路功耗优化,信号概率计算是功耗计算的关键.提出一种基于概率表达式的MPRM电路功耗计算方法.该方法兼顾信号概率计算的时间效率和准确性,对MPRM电路中不存在空间相关性的信号通过在电路中传播信号概率的方式计算其信号概率,存在空间相关性的信号则利用概率表达式计算其信号概率,并在电路中传播概率表达式以解决空间相关性问题,在此基础之上根据基于信号概率建立的解析动态功耗和静态功耗计算模型计算电路功耗.为进一步提高时间效率,该方法采用二元矩图表示概率表达式.使用基准电路对所提出方法进行了验证,并与其他采用不同信号概率计算方法的MPRM电路功耗计算方法进行了比较.结果表明所提出方法准确有效.     

A simple snubber configuration for three-level GTO inverters

A simple snubber configuration for three-level gate turn-off thyristor (GTO) inverters is proposed. The proposed snubber has a single resistor per arm for stored energy dissipation, while the conventional RLD/RCD snubber contains six. This implies that the proposed snubber needs only one chopper circuit per arm for snubber energy recovery. This helps reduce the size, cost, and number of components. Besides the single resistor, the proposed snubber requires two less diodes per arm than the RLD/RCD snubber. Furthermore, the proposed snubber resolves the voltage imbalance problem between inner and outer GTOs without additional components. We have analyzed the proposed circuits and proven its performance through simulations and experiments     

Statistical fault sampling

Computational requirements often discourage, or even prohibit, complete fault simulation of circuit designs having greater than 20000 single stuck-at faults. To circumvent this problem, statistical sampling methods have been proposed that provide fault coverage values within a small, predictable error range by simulating only a fraction of the circuit's total faults and using the result fault coverage value as an estimate of the fault coverage for the total circuit. As an introduction to the application of sampling methods to fault simulation of integrated circuits, the statistical theory behind these sampling methods and proposed augmentations of these methods for improving the precision of the sample fault coverage are presented. Various proposed sampling schemes are applied to example circuit designs, and the results are analyzed     

非状态空间搜索的电路面积优化

文章给出了一个通过去除冗余的方法，实现了电路面积优化的算法。该算法通过电路网络结点值的计算来找到相容的冗余，可以避免由遍历状态空间造成的计算量呈指数增长，同时，所在被找到的冗余将在一次全部除掉。变换后的电路延迟将不会超过初始电路。算法将计算相容时序的冗余，并通过在电路中传播它们来简化电路。实验比较证明，这一算法对大电路是有效的。     

Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools

Cell Fault Model (CFM) is a well-adopted functional fault model used for cell-based circuits. Despite of the wide adoption of CFM, no test tool is available for the estimation of CFM testability. The vast majority of test tools are based on the single stuck-at fault model.In this paper we introduce a method to calculate the CFM testability of a cell-based circuit using any single stuck-at fault based test tool. Cells are substituted by equivalent cells and Test Generation and Fault Simulation for CFM are emulated by Test Generation and Fault Simulation for a set of single stuck-at faults of the equivalent cells. The equivalent cell is constructed from the original cell with a simple procedure, with no need of knowledge of gate-level implementation, or its function. With the proposed methodology, the maturity and effectiveness of stuck-at fault based tools is used in testing of digital circuits, with respect to Cell Fault Model, without developing new tools.     

Mass characterisation of organic transistors and Monte-Carlo circuit simulation

We present a method for designing organic circuits using Monte-Carlo based circuit simulation. The organic devices suffer from mismatch and variations that are due to systematic and random fluctuations in the process and material characteristics. In this work, we have used the variable range hopping model to extract the model parameters using a mass characterisation technique. The parameter fluctuations of organic transistors are taken into account and process corners determined based on static (noise margin) and transient (delay) characteristics. Thus a methodology is developed to find the parameter range of individual devices, within which the circuits are having good performance, for instance inverters working with desired noise margin. We also found out the critical parameters of the transistor, that predominantly affects the static and transient performance of an inverter. These critical parameters can be provided as input to the process engineers to fine tune the process. This information can also be used in developing robust circuit design techniques, which can overcome the variation effects of these critical parameters. Thus, a mass characterisation of transistors combined with the proposed method, allows robust circuit design in the presence of huge process variations.     

CMOS数字集成电路的高温电学性能分析

本文给出了ＣＭＯＳ倒相器的高温等效电路，分析了它的高温直流传输特性和瞬态特性，文章还讨论了ＣＭＯＳ静态数字集成电路高温电学特性的分析方法。本文提出了的ＣＭＯＳ数字集成电路的高温学特性模型和实验结果相接近。     

一种可逆有限状态机的电路设计

不同以往通过重构电路行为实现可逆有限状态机方法,本文提出了一种可逆有限状态机的电路结构.该电路主要包括次态与输出计算电路以及状态预置与采样锁存电路两部分,且提出的可逆有限状态机电路中不存在独立的可逆触发器,但可以实现可逆JK,D,T等触发器功能.同时,文中也提出了基于该可逆有限状态机电路的可逆时序电路综合方法,并用实例进行了验证.相比于基于行为重构的可逆有限状态机的综合方法,本文提出的综合方法可以避免原始状态机的逆状态机的求解和增加额外的信号位,从而使得综合过程变得更加简单.     

Precomputation-based sequential logic optimization for low power

We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions. If the output values can be precomputed, the original logic circuit can be “turned off” in the next clock cycle and will have substantially reduced switching activity. The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit. Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay