A 0.7-3 GHz GaAs QPSK/QAM direct modulator

A single chip I/Q direct modulator for use in digital radio links is presented. This device translates directly the phase and quadrature baseband signals to a microwave frequency that can be chosen between 700 MHz and 3 GHz avoiding the use of IF circuits. It is able to generate any type of digital modulation as QPSK, n-PSK, n-QAM, GMSK, etc., with band-limited spectrum. The bandwidth of the I/Q modulating signals is more than 500 MHz allowing the use of the circuit even in the highest capacity systems. The device has 120 components in a 2.2×2.4 mm chip and has been fabricated using 0.5 μm GaAs MESFET process     

A 170 MHz RF front-end for ERMES pager applications

A 170 MHz RF front-end for ERMES pager applications has been implemented in a 1.2 μm BiCMOS technology. The chip comprises a low noise amplifier with AGC, a double balanced mixer, a varactor tuned LC local oscillator, and an IF strip containing an AGC amplifier and a double balanced mixer with integrated active output filter. The LNA has a measured gain of 22.3 dB at 170 MHz with a usable AGC range of approximately 20 dB while the conversion transconductance of the mixer is 130 μS. This front-end is suitable for direct conversion and superheterodyne pager receivers, and its noise figure is 6.2 dB. Low power operation has been achieved with the front-end drawing 230 μA at 3 V, which is compatible with the intended application in wrist-watch style pagers     

A mesoscopic ballistic electron mixer with efficient frequencyconversion at radio frequency

The voltage-current characteristic of a four-terminal mesoscopic cross is grossly nonlinear, exhibiting two clear regions of negative differential resistance (NDR). This behavior is potentially useful in millimeter wave detectors since these small devices have very low parasitic capacitance and great sensitivity. The device exploits a planar GaAs technology which lends itself to integrated systems. We have exploited one of the NDR regions (at a current of only 1.9 μA) to carry out frequency conversion. At low frequency we observed efficient frequency doubling, with the second harmonic exceeding the fundamental by up to 10 dB at the output. We have also operated the device at radio frequency (5 MHz) and demonstrated both asynchronous and heterodyne amplitude demodulation. The effect of DC current bias was examined and it was shown that biasing the device close to the NDR gave the optimum frequency conversion. A conversion loss in the heterodyne mixer circuit of 3 dB was achieved     

射频电路中混频器的设计

目前实现小型化以及低功耗射频电路的一种可行性方法是实现收发机射频电路的集成。在射频电路的前端,混频器是实现频谱搬移的重要器件,是十分重要的模块。设计了一种微带平衡混频器,其主要由3dB定向耦合器、匹配电路、晶体管和低通滤波器组成,滤波器用来滤除输出信号中高次谐波频率成分,从而得到需要的中频成分。然后用ADS软件进行各部分电路设计、仿真,从功能仿真图中看到输出信号的频谱中有需要的中频频率成分,这就验证了混频器频谱搬移的功能。     

A 10.7-MHz CMOS SC radio IF filter using orthogonal hardwaremodulation

FM radio receivers require an IF filter for channel selection, customarily set at an IF center frequency of 10.7 MHz. Up until now, the limitations of integrated radio selectivity filters in terms of power dissipation, dynamic range, and cost are such that it is still required to use an external ceramic 10.7-MHz bandpass filter. This paper demonstrates a CMOS switched-capacitor IF filter that can be integrated with most of the rest of the FM receiver, eliminating external components and printed circuit board area. This is made possible through a combination of two techniques: orthogonal hardware modulation, and delta-charge redistribution. It exhibits a tightly controlled center frequency with a Q of 55 and also contains a programmable gain. The filter occupies an area of 0.7 mm² in a 0.6 μm CMOS process with poly-poly capacitors. The new filter requires only 16 mW of power, and this is offset by elimination of the power needed in current designs to drive off-chip filters     

0.1 THz鳍线单平衡式基波混频电路研究

研究了一种基于石英基片的0.1 THz频段的鳍线单平衡混频电路,混频电路的射频和本振信号分别从WR10标准波导端口通过波导单面鳍线微带过渡和波导微带探针过渡输入,中频信号通过本振中频双工器输出。这是一种新型的混频电路形式,与传统的W波段混频器相比,混频电路可以省略一个复杂的W波段滤波器,具有电路设计简单、安装方便的特点。该电路使用两只肖特基二极管通过倒装焊工艺粘结在厚度为75 m的石英基片上,石英基片相对传统基板,可以极大提高电路加工精度。在固定50 MHz中频信号时,射频90~110 GHz范围内,0.1 THz混频器单边带变频损耗小于9 dB。     

Compact Harmonic Filter Design and Fabrication Using IPD Technology

An integrated passive device (IPD) technology has been developed to meet the ever increasing needs of size and cost reduction in radio front-end transceiver module applications. Electromagnetic (EM) simulation was used extensively in the design of the process technology and the optimization of inductor and harmonic filter designs and layouts. Parameters such as inductor shape, inner diameter, metal thickness, metal width, and substrate thickness have been optimized to provide inductors with high quality factors. The technology includes 1) a thick plated gold metal process to reduce resistive loss; 2) MIM capacitors using PECVD SiN dielectric layer; 3) airbridges for inductor underpass and capacitor pick-up; and 4) a 10 mil finished GaAs substrate to improve inductor quality factor. Both lumped element circuit simulations and electromagnetic (EM) simulations have been used in the harmonic filter circuit designs for high accuracy and fast design cycle time. This paper will present the EM simulation calibration and demonstrate the importance of using EM simulation in the filter design in order to achieve first-time success in wafer fabrication. The fabricated IPD devices have insertion loss of 0.5 dB and harmonic rejections of 30dB with die size of 1.42 mm for high band (1710 MHz-1910 MHz) and 1.89 mm for low band (824-915 MHz) harmonic filters.     

Monolithic integration of a 94 GHz AlGaAs/GaAs 2-DEG mixer onquartz substrate by epitaxial lift-off

In this paper, we report the integration of an AlGaAs/GaAs two-dimensional electron gas (2-DEG) bolometric mixer and a quartz-based microstrip circuit using the epitaxial lift-off (ELO) technique. The 1 μm thick high-mobility 2-DEG device transplanted on quartz showed no sign of degradation resulting from the ELO process. The 2-DEG mixer fabrication procedure demonstrated here is advantageous for its simplicity and uncritical choice of substrate. We obtained a minimum intrinsic conversion loss of 17 dB at 94 GHz at liquid nitrogen temperature. The measured IF bandwidth of the mixer was greater than 3 GHz     

A parallel structure for CMOS four-quadrant analog multipliers andits application to a 2-GHz RF downconversion mixer

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 μm N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under a single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV_p-p at both multiplier inputs. The -3 dB bandwidth is 2.2 MHz and the DC current is 2.3 mA. By using the proposed multiplier as a mixer-core and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5 μm single-poly-double-metal N-well CMOS technology. The experimental results have shown that, under 3 V supply voltage and 2 dBm LO power, the mixer has -1 dB conversion gain, 2.2 GHz input bandwidth, 180 MHz output bandwidth, and 22 dB noise figure. Under the LO frequency 1.9 GHz and the total DC current 21 mA, the third-order input intercept point is +7.5 dBm and the input 1 dB compression point is -9 dBm     

2.7 V 50 MHz IF sampling ΔΣ modulator with +37 dBV IIP3

The design and experimental results of a 2.7 V 50 MHz switched-capacitor DS modulator in a 0.35 μm BiCMOS process are presented. The circuit is targeted for the IF section of a radio receiver in a GSM cellular phone. It combines frequency downconversion with analogue to digital conversion by directly sampling an input signal from an IF of 50 MHz. The measured peak signal-to-noise ratio for a 100 kHz bandwidth is 81 dB with a 53 MHz blocking signal and the measured IIP3 for IF input is +36.9 dBV     

Mixed analog/digital, FIR/IIR realization of a linear-phase lowpassfilter

A 5 kHz linear-phase lowpass filter is implemented in a 2-μm BiCMOS technology as a combination of sigma-delta front-end, a digital shift register, a switched capacitor (SC) summer circuit with 50 input capacitors, and an SC biquad running at a 1 MHz clock. The measured group delay variation in the passband is less than 1 μs and the measured total harmonic distortion (THD) is -80 dB for an input sine wave amplitude of 0.7 V at 1 kHz. The circuit consumes 80 mW from ±5 V supply and measures 8.12 mm² without pads     

Switched-current signal processing for video frequencies and beyond

Switched-current (SI) signal processing circuits with video frequency performance are presented. The delay cells employ negative feedback to produce a `virtual earth' at the input node to improve transmission accuracy. Fully differential structures with common-mode feedback are used to reduce charge injection errors and crosstalk from digital signals. An IC test circuit, in a 1 μm standard digital CMOS process, containing simple delay lines and an FIR filter section is described, and measured performance is given. Typically, a 2T delay line sampling at 13.3 MHz gave a low-frequency gain error of -54 dB, a settling error of -60 dB, a third-harmonic distortion of -40 dB with 75% modulation, and an S/N ratio of 60 dB. Scaling of the memory cell device dimensions and currents should permit SI operation at clock frequencies beyond 100 MHz     

一种无源高线性混频组件的设计与实现

在射频通信系统中,混频器作为接收机的核心器件,其线性指标将直接影响整个接收系统的性能。文中设计并实现了一种无源高线性混频组件电路,采用“平衡混频器+吸收式滤波器”的方式达到了高线性要求。平衡混频器采用一对双平衡混频器互联,通过相位抵消达到优化线性的目的;吸收式滤波器吸收混频器产生非线性谐波,使其无法在空间中进行反射,两者共同作用优化了组件整体的线性指标。测试显示,在射频频率为30~1 350 MHz,本振频率为3 030~4 350 MHz,中频频率为3 000 MHz的条件下,混频组件的IIP₂可以达到94 dBm,IIP₃可以达到29 dBm。相比于单独混频器,新电路的线性性能得到极大的优化,更适合高性能的接收机使用。     

An I/Q mixer with an integrated differential quadrature all-pass filter for on-chip quadrature LO signal generation

A down-conversion in-phase/quadrature (I/Q) mixer employing a folded-type topology, integrated with a passive differential quadrature all-pass filter (D-QAF), in order to realize the final down-conversion stage of a 60 GHz receiver architecture is presented in this work. Instead of employing conventional quadrature generation techniques such as a polyphase filter or a frequency divider for the local oscillator (LO) of the mixer, a passive D-QAF structure is employed. Fabricated in a 65 nm CMOS process, the mixer exhibits a voltage gain of 7-8 dB in an intermediate frequency (IF) band ranging from 10 MHz-1.75 GHz. A fixed LO frequency of 12 GHz is used to down-convert a radio frequency (RF) band of 10.25-13.75 GHz. The mixer displays a third order input referred intercept point (IIP₃) ranging from -8.75 to -7.37 dBm for a fixed IF frequency of 10 MHz and a minimum single-sideband noise figure (SSB-NF) of 11.3 dB. The mixer draws a current of 6 mA from a 1.2 V supply voltage dissipating a power of 7.2 mW.     

A 2-GHz 1.6-mW phase-locked loop

This paper describes the design of a 2 GHz 1.6 mW phase-locked loop (PLL) fabricated in an 18 GHz 0.6 μm BiCMOS technology. Employing cross-coupled delay elements and inductive peaking, the circuit merges the oscillator and the mixer into one stage to lower the power dissipation. An experimental prototype exhibits an r.m.s. jitter of 2.8 ps, a tracking range of 100 MHz, and a capture range of 70 MHz while operating from a 3 V supply. The phase noise in the locked condition is -115 dBc/Hz at 400 kHz offset     

Monolithic programmable RF filter

A voltage programmable monolithic continuous-time bandpass filter that employs transconductance amplifier based fully differential integrators is introduced. Experimental results of a circuit fabricated in a 3 μm CMOS process that is programmable over the range from 2 to 16 MHz are presented     

A current-mode bit-block circuit applicable to low-voltage, low-power pipeline video-speed A/D converters

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 m device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.     

Testing of RF mixers with adaptive filters

This work describes a technique for testing RF mixers with digital adaptive filters. RF circuits are widely used on data transmission applications, such as wireless communication, radio and portable phone systems. However, traditional analog testing covers mainly linear circuits, being not suitable to non-linear pieces of hardware like analog mixers. Herein, an adaptive non-linear filter is trained so that it can mimic the behavior of a RF mixer. Then, a test stimulus is simultaneously applied to the filter and the mixer and the outputs of both circuits are compared to check whether the circuit under test is faulty or fault free. A prototype of a mixer was built in order to allow fault injection in the circuit under test. Thus, the detection capability of the proposed technique could be checked in a real life circuit. The preliminary results point to a very promising test technique. The test is very precise, low cost and allows a complete fault coverage with a very small testing time.     

RF characterization of the semiconductor junction igniter in the2.75 folding fin aircraft rocket

The design and characterization of a novel passive ignition system which consists of a simple two-stage radio frequency (RF) low pass filter and a novel RF insensitive electro-explosive device is discussed [1]-[3]. Lumped parameter modeling was used to provide the frequency response of the circuit. The 2.75 Folding Fin Aircraft Rocket (2.75 FFAR) was utilized as a test vehicle for field measurements which were performed as specified in MIL-STD 1385B at the Naval Surface Warfare Center in Dhalgren, VA. The configuration exhibited excellent performance over the entire frequency range of 1.5 MHz to 1 GHz