A 3.3-V, low-distortion ISDN line driver with a novel quiescentcurrent control circuit

A U-interface line driver for a single-chip ISDN (integrated services digital network) NT (network termination) in an advanced 3.3-V, 0.5-μm CMOS technology is presented. It features a THD (total harmonic distortion) better than -68 dB for an output swing of 5 V_pp on a 67-Ω load in a band up to 60 kHz. A novel quiescent current control circuit is implemented. The advantages of this new approach lie in the reduction of the variation of the quiescent current and the facilitation of the driver's circuits and compensation scheme     

Control Strategy for a 42-V Waste-Heat Thermoelectric Vehicle

A 42-V waste-heat thermoelectric vehicle is employed as a potential application of thermoelectric generators for fuel economy improvement and emissions reduction. The 42-V waste-heat thermoelectric vehicle currently in development employs an assemblage driving system consisting of a waste-heat thermoelectric generator, a 42-V powernet, and an integrated starter and generator (ISG). The waste-heat thermoelectric generator also functions as a power supply. To optimize the utilization of the waste-heat energy generated by the thermoelectric generator, an electric assist control strategy and a torque split control strategy are proposed herein. Through the development of relevant systems and strategies, including the thermoelectric generator and an electric bus system, two vehicle models are established and compared using the ADVISOR platform based on MATLAB/Simulink. The calculation results show improved fuel economy and emissions performance resulting from the integration of the torque split control strategy into the 42-V waste-heat thermoelectric vehicle.     

An 80-V integrated boost converter for piezoelectric actuators in smartphones

A boost converter for piezoelectric actuator driving system in haptic smartphones is proposed and implemented using a 0.35 μm BCDMOS process. The designed boost converter generates extremely high output voltage from a low-voltage battery supply. The boost converter provides stable power for the piezoelectric actuator with the peak-current control technique. The minimum variation of the output ripple variation can be achieved by the designed current-sensing and peak-current control circuits. The supply voltage of the boost converter is 2.7–4.2 V and the maximum output voltage is up to 80 V. The complete piezoelectric actuator driving system consists of a serial interface, SRAM, and signal-shaping logic as well as the boost converter. It also includes the resistor-string digital-to-analog converter and high voltage piezoelectric actuator driver (PZ driver). The fabricated chip size is 2,100 × 2,200 μm, including bonding pads.     

An integrated strategy for reducing location management cost

In this letter, an integrated location information management strategy is proposed for mobile networks, where local anchor and replica are deployed to efficiently manage the location information of a mobile terminal (MT) based on its call and mobility characteristics. As an MT's user is roaming within the local signal transfer point (LSTP) region serving the user's home or workplace, the MT's location change is reported to a local anchor (LA)-the visitor location register (VLR) associated with the user's home or workplace. Meanwhile, the LA's location is replicated at several switches (called the replicas) originating relatively high call rates to the MT. As a result, the MT's home location register (HLR) needs to be accessed only when the MT changes its LSTP region or an incoming call for the MT is generated by a nonreplica originating switch. This is shown to reduce location tracking costs.     

An integrated AC drive system using a controlled-current PWMrectifier/inverter link

Two identical three-phase, bipolar transistor, controlled-current, pulsewidth modulation (PWM) power modulators are integrated so that one functions as a rectifier and the other as an inverter in an AC drive system. The rectifier input currents maintain near-60-Hz sinusoidal waveforms with unity power factor. A leading power factor is also possible. The modulators do not depend on the availability of bidirectional switch elements. Performance as a polyphase induction motor drive under motoring and regenerative braking is reported. The study includes digital simulation of operation as a synchronous motor drive     

Passive protection strategy for a drive system with a matrixconverter and an induction machine

In this paper, the design and testing of a new protection strategy for a matrix power converter feeding an induction motor with a squirrel cage rotor is described. The new protection strategy with excellent overvoltage protection allows the removal of the large and expensive diode clamp     

An integrated automatic design system for complex DSP algorithms

An integrated design environment for the automated design of DSP systems is described. The overall design time of complex DSP systems on silicon can be reduced drastically by offering the designer a complete silicon compilation environment, integrating architectural level synthesis tools, a module generator and a floorplanner. The system is supported by a flexible and powerful library. A true exploration of the design space in an interactive way is possible. Examples of the first complex chips that have been designed with this system are discussed.     

An outline of design techniques for linear integrated circuits

The components available in integrated circuits are well known for their large tolerances and temperature coefficients. This paper is a condensed survey of design principles that make use of the advantages offered in monolithic structures: close matching and tracking of parameters, control over component geometries, and the availability of a large number of active devices at little extra cost. With these techniques it is, in many cases, possible to duplicate or even exceed the performance of discrete component linear circuits.     

An integrated multiscaling strategy based on a particle swarm algorithm for inverse scattering problems

The application of a multiscale strategy integrated with a stochastic technique to the solution of nonlinear inverse scattering problems is presented. The approach allows the explicit and effective handling of many difficulties associated with such problems ranging from ill-conditioning to nonlinearity and false solutions drawback. The choice of a finite dimensional representation for the unknowns, due to the upper bound to the essential dimension of the data, is iteratively accomplished by means of an adaptive multiresolution model, which offers a considerable flexibility for the use of the information on the scattering domain acquired during the iterative steps of the multiscaling process. Even though a suitable representation of the unknowns could limit the local minima problem, the multiresolution strategy is integrated with a customized stochastic optimizer based on the behavior of a particle swarm, which prevents the solution from being trapped into false solutions without a large increasing of the overall computational burden. Selected examples concerned with a two-dimensional microwave imaging problem are presented for illustrating the key features of the integrated stochastic multiscaling strategy.     

An optimization based design for integrated dependable real-time embedded systems

Moving from the traditional federated design paradigm, integration of mixed-criticality software components onto common computing platforms is increasingly being adopted by automotive, avionics and the control industry. This method faces new challenges such as the integration of varied functionalities (dependability, responsiveness, power consumption, etc.) under platform resource constraints and the prevention of error propagation. Based on model driven architecture and platform based design’s principles, we present a systematic mapping process for such integration adhering a transformation based design methodology. Our aim is to convert/transform initial platform independent application specifications into post integration platform specific models. In this paper, a heuristic based resource allocation approach is depicted for the consolidated mapping of safety critical and non-safety critical applications onto a common computing platform meeting particularly dependability/fault-tolerance and real-time requirements. We develop a supporting tool suite for the proposed framework, where VIATRA (VIsual Automated model TRAnsformations) is used as a transformation tool at different design steps. We validate the process and provide experimental results to show the effectiveness, performance and robustness of the approach.     

20 Gbit/s operation of a high-efficiency InGaAsP/InGaAsP MQWelectroabsorption modulator with 1.2-V drive voltage

The authors have fabricated a ridge waveguide electroabsorption modulator based on the quantum-confined Stark effect in InGaAsP/InGaAsP multiple quantum wells. The drive voltage for 12-dB extinction ratio is 1.2 V, and the frequency response is flat within 2 dB from DC to 20 GHz. Operation at 20 Gb/s is reported. Extensive data concerning the parasitic phase modulation (chirping) are obtained as a function of applied bias acid operating wavelength     

An efficient back-bias generator with hybrid pumping circuit for1.5-V DRAMs

An efficient back-bias (V_bb) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a V_bb level of -1.44 V at V_cc=1.5 V, compared to a conventional system in which V_bb only reaches -0.6 V. HPC can pump without the threshold voltage (V_th) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAMs, because a V_bb level lower than -1.0 V is necessary to meet the limitations of the V_th, of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection     

An Output Buffer for 3.3-V Applications in a 0.13-μm 1/2.5-V CMOS Process

With a 3.3-V interface, such as PCI-X application, high-voltage overstress on the gate oxide is a serious reliability problem in designing I/O circuits by using only 1/2.5-V low-voltage devices in a 0.13-mum CMOS process. Thus, a new output buffer realized with low-voltage (1- and 2.5-V) devices to drive high-voltage signals for 3.3-V applications is proposed in this paper. The proposed output buffer has been fabricated in a 0.13-mum 1/2.5-V 1P8M CMOS process with Cu interconnects. The experimental results have confirmed that the proposed output buffer can be successfully operated at 133 MHz without suffering high-voltage gate-oxide overstress in the 3.3-V interface. In addition, a new level converter that is realized with only 1- and 2.5-V devices that can convert 0/1-V voltage swing to 1/3.3-V voltage swing is also presented in this paper. The experimental results have also confirmed that the proposed level converter can be operated correctly     

An analog drive loop for a capacitive MEMS gyroscope

The linear model and the design of an analog drive loop for the drive (primary) resonator in a capacitive gyroscope are presented. Four different types of gain control topologies are compared and analyzed with both P- and PI-type controllers. The simple model proposed in the paper allows the small signal properties of the loop to be predicted. The theoretical models based on the small signal analysis are compared to the simulated and measured results. A proportional amplitude controller, together with the rest of the drive loop, is implemented using a high-voltage 0.35-μm CMOS technology and a nominal supply of 3 V. Clock generation using a PLL and the drive loop signal as the reference are also discussed in the paper.     

An overview to integrated power module design for high power electronics packaging

In recent years, there has been an explosion in demand for smaller and lighter, more efficient, and less expensive power electronic supplies and converters. There are a number of reasons for this recent necessity, ranging from the need for smaller and cheaper power converters for consumer electronics (such as laptop computers and cellular phones) to the need for highly reliable power electronics for such items as satellite and military craft power systems, which are required to be highly efficient, light in weight, smaller in volume, and low cost. This paper discusses the concept of Integrated Power Modules (IPMs), in which the electronic control circuitry and the high power electronics of the converter are integrated into a single compact standardized module. The advantages and disadvantages of such an approach will be discussed in reference to the current industry standard for power electronics design and packaging. The researchers will then take the readers through the IPM design, including basic circuit topology layout, module fabrication processes, and finally thermal considerations.     

Modeling and design of a DFB laser integrated with a Mach-Zehndermodulator

A comprehensive model for a complex-coupled distributed feedback laser diode monolithically integrated with a Mach-Zehnder modulator is developed and validated by comparison with experimental data. Methods and their tradeoffs for reduction of adiabatic frequency chirp due to the parasitic reflections from the modulator are discussed     

An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip

A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications. It adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption. The CGC technique combines an automatic gain control and an exponential gain control together to reduce power dissipation and to control both gain and threshold knee voltage. The ASNR technique changes the value of the signal-to-noise ratio (SNR) in accordance with input amplitude in order to minimize power consumption and to optimize the SNR by sensing an input signal. The proposed analog front-end circuit achieves 86-dB peak SNR in the case of third-order /spl Sigma//spl Delta/ modulator with 3.8-/spl mu/Vrms of input-referred noise voltage. It dissipates a minimum and maximum power of 59.4 and 74.7 /spl mu/W, respectively, at a single 0.9-V supply. The core area is 0.5 mm/sup 2/ in a 0.25-/spl mu/m standard CMOS technology.     

An integrated control and structural design approach for mesh reflector deployable space antennas

An integrated control and structural design approach for mesh reflector deployable space antennas is presented in this paper. The coupled relationship of the antenna structure, deployment trajectory, and control system is discussed, and then the integrated design model is proposed. A multi-objective function is set to simultaneously minimize the antenna mass, the impact on antenna, and the energy dissipation of control system. The cross section areas of links, Bezier control points, and controller gain parameters are selected as the design variables. With the eigenfrequency, rigidity, stability, rapidity and accuracy constraints, the optimal integrated design is achieved. The highly nonlinear characteristic of this problem is discussed and corresponding solving strategy and methodology are described. Experiments are carried out to verify the rationality and validity of the structural analysis models and the control algorithm. Numerical simulations demonstrate the feasibility of the proposed design method.     

符号化仿真技术用于提高模拟集成电路设计良率

模拟电路对于工艺偏移的敏感性以及设计良率是模拟电路设计师关心的重要问题.由于数值仿真工具的局限性,至今设计界仍缺乏能有效提高电路可靠性与良率的通用设计辅助工具.提出利用符号化仿真器GRASS(Graph Reduction Analog Symbolic Simulator)快速导出频域设计指标关于电路参数的解析表示,并由此用三维立体图示的方式展示设计指标关于电路参数的依赖敏感度,设计者能够直观的判断如何选择合适的参数组合,以降低工艺偏移可能导致的电路性能恶化,从而提高设计良率.实验表明本文提出的方法可以有效地辅助设计者对于电路参数进行准确判断与选择,是一种值得在实际模拟电路设计中使用的辅助方法.