0.18 μm 1.8 V 10 bit 100 MS/s CMOS电流舵D/A IP设计与验证

基于GSMC 0.18μm CMOS工艺,采用曲率补偿带隙参考电压源和中心对称Q2随机游动对策拓扑方式的NMOS电流源阵列版图布局,实现了一种10 bit 100 MS/s分段温度计译码CMOS电流舵D/A转换器.当电源电压为1.8 V时,D/A转换器的功耗为10 mW,微分非线性误差和积分非线性误差分别为1 LSB和0.5 LSB.在取样速率为100 MS/s,输出频率为5 MHz条件下,SFDR为70 dB,10 bit D/A转换器的有效版图面积为0.2 mm2,符合SOC的嵌入式设计要求.     

一种1.8V 10位120MS/s CMOS电流舵D/A转换器IP核

采用低摆幅低交叉点的高速CMOS电流开关驱动器结构和中心对称Q2随机游动对策拓扑方式的pMOS电流源阵列版图布局方式,基于TSMC 0.18靘 CMOS工艺实现了一种1.8V 10位120MS/s分段温度计译码电流舵CMOS电流舵D/A转换器IP核.当电源电压为1.8V时,D/A转换器的微分非线性误差和积分非线性误差分别为0.25LSB和0.45LSB,当采样频率为120MHz,输出频率为24.225MHz时的SFDR为64.9dB.10位D/A转换器的有效版图面积为0.43mm×0.52mm,符合SOC的嵌入式设计要求.     

一种1.8V 10位120MS/s CMOS电流舵D/A转换器IP核

采用低摆幅低交叉点的高速CMOS电流开关驱动器结构和中心对称Q2随机游动对策拓扑方式的pMOS电流源阵列版图布局方式,基于TSMC 0.18靘 CMOS工艺实现了一种1.8V 10位120MS/s分段温度计译码电流舵CMOS电流舵D/A转换器IP核.当电源电压为1.8V时,D/A转换器的微分非线性误差和积分非线性误差分别为0.25LSB和0.45LSB,当采样频率为120MHz,输出频率为24.225MHz时的SFDR为64.9dB.10位D/A转换器的有效版图面积为0.43mm×0.52mm,符合SOC的嵌入式设计要求.     

高速12位D/A转换器

介绍了高速12位D/A转换器的电路设计,采用2μm等平面高速双极工艺,研制出数据更新率≥80MHz,线性误差≤3LSB,微分非线性≤3LSB的12位D/A转换器电路.     

高速12位D/A转换器

介绍了高速12位D/A转换器的电路设计,采用2μm等平面高速双极工艺,研制出数据更新率≥80MHz,线性误差≤3LSB,微分非线性≤3LSB的12位D/A转换器电路.     

高速12位D/A转换器

介绍了高速12位D/A转换器的电路设计，采用2μm等平面高速双极工艺，研制出数据更新率≥80MHz，线性误差≤3LSB，微分非线性≤3LSB的12位D/A转换器电路.     

CMOS图像传感器中RSD A/D转换器的设计与实现

提出了CMOS图像传感器中RSD A/D转换器的设计方法.基于冗余符号数(RSD)算法,RSD A/D转换器降低了对比较器的性能要求.并且全差分的模拟信号处理用以改进抗噪声度,信噪比和系统的动态范围.RSD A/D转换器是基于90 nm CMOS工艺实现的,测试结果表明它的微分非线性误差(DNL)为±1 LSB,积分非线性误差(INL)为±1.5 LSB,总的未调整误差(TUE)为-3 LSB～1 LSB,功耗约为20 mW.     

一种14位400MS/S分段型电流舵DAC的设计

基于TSMC O.25μm CMOS工艺,采用分段开关电流结构,设计了一种基于2.5 V电源电压的14位400MS/s D/A转换器.该D/A转换器内置高精度带隙基准源、高速开关驱动电路和改进的Cascode单位电流源电路,以提高性能.D/A转换器的积分非线性(INL)和微分非线性(DNL)均小于0.5 LSB.在400 MHz采样频率、199.8 MHz输出信号频率时,其无杂散动态范围(SFDR)达到85.4 dB.     

低功耗、全差分流水线操作CMOS A/D转换器

提出一种基于运算跨导放大器共享技术的流水线操作A/D转换器体系结构,其优点是可以大幅度降低芯片的功耗和面积.采用这种结构设计了一个10位20MS/s转换速率的全差分流水线操作A/D转换器,并用CSMC 0.6μm工艺实现.测试结果表明,积分非线性为1.95LSB,微分非线性为1.75LSB;在6MHz/s采样频率下,对1.84MHz信号转换的无杂散动态范围为55.8dB;在5V工作电压、20MHz/s采样频率下,功耗为65mW.     

一种10位40 MHz两步式A/D转换器

提出了一种基于两步转换法(5 6)的高速高精度A/D转换器体系结构,其优点是可以大幅度降低芯片的功耗及面积。采用这种结构,设计了一个10位40 MHz的A/D转换器,并用0.6μm BiCMOS工艺实现。经过电路模拟仿真,在40 MHz转换速率,1 V输入信号(Vp-p),5 V电源电压时,信噪比(SNR)为63.3 dB,积分非线性(INL)和微分非线性(DNL)均小于10位转换器的±0.5 LSB,电源电流为85.4 mA。样品测试结果:SNR为55 dB,INL和DNL小于10位转换器的±1.75 LSB。     

A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration

The design of a 600-MS/s 5-bit analog-to-digital (A/D) converter for serial-link receivers has been investigated. The A/D converter uses a closed-loop pipeline architecture. The input capacitance is only 170 fF, making it suitable for interleaving. To maintain low power consumption and increase the sampling rate beyond the amplifier settling limit, the paper proposes a calibration technique that digitally adjusts the reference voltage of each pipeline stage. Differential input swing is 400 mV/sub p-p/ at 1.8-V supply. Measured performance includes 25.6 dB and 19 dB of SNDR for 0.3-GHz and 2.4-GHz input frequencies at 600 MS/s for the calibrated A/D converter. The suggested calibration method improves SNDR by 4.4 dB at 600 MS/s with /spl plusmn/0.35 LSB of DNL and /spl plusmn/0.15 LSB of INL. The 180 /spl times/ 1500 /spl mu/m/sup 2/ chip is fabricated in a 0.18-/spl mu/m standard CMOS technology and consumes 70 mW of power at 600 MS/s.     

14位50MS/s100mW0.18μm CMOS流水线ADC

实现了一种14位40MS/s CMOS流水线A/D转换器(ADC)。在1.8V电源电压下,该ADC功耗仅为100mW。基于无采样/保持放大器前端电路和双转换MDAC技术,实现了低功耗设计,其中,无采样/保持放大器前端电路能降低约50%的功耗,双转换MDAC能降低约10%的功耗。该ADC采用0.18μm CMOS工艺制作,芯片尺寸为2.5mm×1.1mm。在40MS/s采样速率、10MHz模拟输入信号下进行测试,电源电压为1.8V,DNL在±0.8LSB以内,INL在±3.5LSB以内,SNR为73.5dB,SINAD为73.3dB,SFDR为89.5dBc,ENOB为11.9位,THD为-90.9dBc。该ADC能够有效降低SOC系统、无线通信系统及数字化雷达的功耗。     

一种基于0.13m CMOS工艺的10位SAR A/D转换器

基于SMIC0.13μm CMOS1P6M Logic工艺,采用一种新型R-C组合式D/A转换结构、伪差分比较结构以及低功耗电平转换结构设计了一种用于多电源SoC的10位8通道逐次逼近型A/D转换器。在3.3V模拟电源电压和1.2V数字电源电压下,测得DNL和INL分别为0.31LSB和0.63LSB。当采样频率为1MS/s,输入信号频率为490kHz时,测得的SFDR为67.33dB,ENOB为9.48bits,功耗为3.25mW。该A/D转换器版图面积为318μm×270μm,能直接应用于嵌入式多电源SoC。     

A high performance 90 nm CMOS SAR ADC with hybrid architecture

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design chal-lenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238×214 μm~2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.     

An 8-bit high-speed CMOS A/D converter

An 8-bit high-speed A/D converter has been developed in a 1.5-/spl mu/m bulk CMOS double-polysilicon process technology. The design, process technology, and performance of the converter are described. In order to achieve high speed and low power, a fine-pattern process technology and a novel capacitor structure have been introduced and the transistor sizes of a chopper-type comparator have been optimized. High speed (30 MS/s) and low power consumption (60 mW) have been obtained. Computerized evaluations such as the histogram test and the fast Fourier transform test have been used to measure dynamic performance. The linearity error in dynamic operation is less than /spl plusmn/1 LSB. Signal-to-peak-noise ratio is 40 dB at a sampling rate of 14.32 MS/s and an input frequency of 1.42 MHz.     

A 10-bit 200-MS/s CMOS parallel pipeline A/D converter

This paper describes a 10-bit 200-MS/s CMOS parallel pipeline analog-to-digital (A/D) converter that can sample input frequencies above 200 MHz. The converter utilizes a front-end sample-and-hold (S/H) circuit and four parallel interleaved pipeline component A/D converters followed by a digital offset compensation. By optimizing for power in the architectural level, incorporating extensively parallelism and double-sampling both in the S/H circuit and the component ADCs, a power dissipation of only 280 mW from a 3.0-V supply is achieved. Implemented in a 0.5-μm CMOS process, the circuit occupies an area of 7.4 mm². The converter achieves a differential nonlinearity and integral nonlinearity of ±0.8 LSB and ±0.9 LSB, respectively, while the peak spurious-free-dynamic-range is 55 dB and the total harmonic distortion better than 46 dB at a sampling rate of 200 MS/s     

A 10-bit low power SAR A/D converter based on 90 nm CMOS

Traditional and some recently reported low power, high speed and high resolution approaches for SAR A/D converters are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations for high speed SAR A/D converters are presented. Moreover, an R-C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process. The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively. With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively, and the power dissipation is measured to be just 3.17 mW.     

A 1-V CMOS D/A converter with multi-input floating-gate MOSFET

A low-voltage D/A converter using multi-input floating-gate MOSFET within a matrix current cell architecture is described in this paper. The two-input floating-gate p-channel MOSFET of each current cell performs the combined functions of current source and current switch. The double-gate-driven MOSFET circuit technique was employed in the digital circuitry to facilitate low supply voltage operation. A 6-bit and 8-bit digital-to-analog converter (DAC) have been fabricated in standard double-poly double-metal 1.2 μm CMOS technology. Measurements show a supply voltage as low as 0.9 and 1.0 V is sufficient to operate the 6-bit and 8-bit DAC, respectively, with a 5 Msamples/s conversion rate     

A 100-MS/s 8-b CMOS subranging ADC with sustained parametricperformance from 3.8 V down to 2.2 V

A 100-MS/s 8-b CMOS analog-to-digital converter (ADC) designed for very low supply voltage and power dissipation is presented. This single-ended-input ADC is based on the unified two-step subranging architecture, which processes the coarse and fine decisions in identical signal paths to maximize their matching. However, to minimize power and area, the coarse-to-fine overlap correction has been aggressively reduced to only one LSB. The ADC incorporates five established design techniques to maximize performance: bottom-plate sampling, distributed sampling, autozeroing, interpolation, and interleaving. Very low voltage operation required for a general purpose ADC was obtained with four additional and new circuit techniques. These are a dual-gain first-stage amplifier, differential T-gate boosting, a supply independent delay generator, and a digital delay-locked-loop controlled output driver. For a clock rate of 100 MS/s, 7.0 (7.3) effective bits for a 50 MHz (10 MHz) input are maintained from 3.8 V down to 2.2 V. At 2.2 V, this 100-MS/s converter dissipates 75 mW plus 9 mW for the reference ladder. For a typical supply of 2.7 V, it consumes just 1 mW per MS/s over the 10-160-MS/s clock frequency range. Differential nonlinearity below 0.5 LSB is maintained from 2.7 V down to 2.2 V, and it degrades only slightly to 0.8 LSB at 3.8-V supply. The converter is implemented in a 0.35-μm CMOS process, with double-poly capacitors and no low-threshold devices     

一种电容阵列结构的10位8通道1MS/s逐次逼近AD转换器

设计了一种用于多电源SoC的10位8通道1MS/s逐次逼近结构AD转换器。为提高ADC精度,DAC采用改进的分段电容阵列结构。为降低功耗,比较器使用了反相器阈值电压量化器,在模拟输入信号的量化过程中减少静态功耗产生。电平转换器将低电压数字逻辑信号提升为高电平模拟信号。采用UMC 55nm 1P6M数字CMOS工艺上流片验证设计。测试结果表明,当采样频率为1 MS/s、输入信号频率为10 kHz正弦信号情况下,该ADC模块在3.3 V模拟电源电压和1.0 V数字电源电压下,具有最大微分非线性为0.5LSB,最大积分非线性为1LSB。测得的SFDR为75 dB,有效分辨率ENOB为9.27位。