功放的数字基带预失真系统研究与仿真

为了克服功率放大器的非线性失真和满足制定的功率谱密度要求,数字基带预失真技术以其良好的线性度、宽带宽、高效率和全自适应性等优点成为解决功率放大器非线性失真的问题.文中在详细地分析数字基带预失真系统原理和单位延迟抽头多项式模型的基础上,提出了具有记忆效应的数字基带预失真电路,并在ADS环境中实现了系统级仿真.仿真结果表明,系统对功率谱密度的改善最大能达到30dBm,具有很好的预失真效果.故构建的系统级仿真电路对实际的数字预失真系统设计起着重要的指导作用.     

数字基带自适应预失真算法设计及仿真实现

从算法的递归方式、收敛速度和三阶互调失真改善效果方面考虑,对各种自适应算法做了详细的分析,完成了数字基带自适应预失真算法的设计。Matlab仿真结果表明,以自适应预失真算法为核心的数字基带预失真功放较线性化之前三阶互调失真改善12dB。     

基于直方图匹配的功放基带预失真方法

传统功放基带预失真方法在系统环路延迟补偿精度下降时性能迅速下降,已有的基于累积分布函数的方法无需精确的环路延迟补偿,但其忽略了功放的相位非线性,应用受到限制。提出了一种基于直方图匹配方法求解功放幅度和相位非线性特性,从而构建基带预失真器的方法。仿真结果证明,该方法能够有效改善功放的幅度和相位非线性,效果优于传统方法,且无需进行环路延迟补偿。     

带记忆效应的射频功放数字基带预失真

在无线通信系统中，射频大功率器是产生非线性失真的主要器件，预失真技术因其成本低廉、自适应能力强、效率高等优势成为最有发展潜力的线性化技术。本文介绍了射频功放的记忆效应及用于识别HPA记忆效应的数字预失真器的结构和特点,提出了基于Wiener模型预失真器的相关算法。通过计算机仿真验证了该算法的有效性以及基于Wiener模型的数字预失真技术能够有效改善记忆功放的线性化，从而提高发射机的整体性能。     

OFDM系统中基带预失真技术研究

本文针对无线OFDM系统中功放非线性的影响,提出了基于基带预失真技术的解决方案.通过计算机仿真考查其对不同功放特性的自适应有效性,结果表明该基带预失真技术对OFDM系统的功放非线性恶化改善明显.     

OFDM系统中基带预失真技术研究

本文针对无线OFDM系统中功放非线性的影响,提出了基于基带预失真技术的解决方案。通过计算机仿真考查其对不同功放特性的自适应有效性,结果表明该基带预失真技术对OFDM系统的功放非线性恶化改善明显。     

一种基于2．14GHz功率放大器的预失真反馈延迟估计

反馈回路的延迟估计是功率放大器数字预失真技术的前提,本文提出了一种环路延迟估测方法,在考虑信道畸变的同时,降低了运算量。然后基于一款Freescale（MHL21336）2．14GHz的AB类功率放大器,采用无记忆预失真方法和正交记忆多项式预失真方法实验验证,结果表明该环路延迟估计算法能够使无记忆多项式预失真器的单载波WCDMA信号的ACPR（邻近信道功率比）改善近20dB,而对正交记忆多项式预失真方法大约可以改善24dB。     

插入式短波预失真器的设计与实现

在已有带预失真的短波发信系统中,预失真处理通常与激励器基带信号处理部分高度融合,无法直接应用于已有的短波通信系统,或者需要对已有系统进行大幅修改。针对该问题,提出一种插入式预失真技术,并利用DSP+FPGA硬件平台,设计一种插入式短波预失真器。插入式短波预失真器级联在激励器与功放之间,DSP控制整个系统以及预失真算法部分。FPGA完成正常通信与测量2种模式下的数字混频数字滤波以及预失真补偿,利用ARM控制板集成的以太网功能实现PC与插入式短波预失真器的网口通信。实验结果表明,该插入式短波预失真器可有效改善功放互调失真指标,由仅1/3频点达标改善为全频段抑制至-36 dB以下,达到了预设指标要求。     

一种适合于硬件实现的数字预失真算法

传统的数字基带预失真算法较复杂不易实现。为此,设计一种适合于硬件实现的数字预失真算法。考虑对模拟射频部分引入的环路延迟和相位偏转的补偿,采用2块大小为32×16的查找表作为预失真模块,存储针对不同输入幅度信号的调整系数,以预先抵消功率放大器的失真。用调制方式为64QAM OFDM信号进行测试,结果表明,该算法的预失真性能较好。     

用于功放线性化的自适应预失真可变索引方法研究及实现

该文提出了一种用于功放线性化的预失真查找表（LUT）的可变索引方法及其实现。在这种方法中,查找表项的密度与功率放大器非线性程度成比例,与传统LUT地址寻址方法相比,这种方法具有简单、灵活、自适应、易于实现等特点,并在FPGA中成功实现。实现结果表明,这种方法是切实可行的。     

Application of principal component analysis based effective digital predistortion technique for low‐cost FPGA implementation

This article investigates the issue of low‐cost digital predistortion (DPD) implementation in fixed‐point field programmable gate array (FPGA) by considering the bit‐resolution along with lower number of coefficients. The impact of principle component analysis (PCA) on bit‐resolution of DPD solution is proposed within the context of established DPD models. Unlike previously proposed PCA based solutions, it is established by simulation and measurement that the numerical stability problem associated with popular models such as memory polynomial (MP) can be alleviated when PCA is applied to the observation data matrix. It is reported with measurement results that PCA based model provides better linearization performance with the least memory size requirement and number of LUTs in 16‐bit fixed‐point FPGA operation than MP, orthogonal memory polynomial (OMP), and generalized memory polynomial (GMP) models. The performance of the proposed model, is evaluated in terms of normalized mean square error, adjacent channel error power ratio, matrix condition number, and dispersion coefficient for continuous Class‐AB and ZX60‐V63+ power amplifiers using wide code‐division multiple access signal (WCDMA) and long term evolution (LTE) signal with peak‐to‐average‐power ratio (PAPR) around 9.895 and 11.92 dB, respectively.     

New estimation and compensation method for quadrature modulator and demodulator errors in digital predistortion system

This article proposes a new method to estimate and compensate for the in‐phase and quadrature (IQ) imbalance errors of the quadrature modulator (QM) and demodulator (QDM) without interrupting the transmission. It uses two groups of captured signals, which transmit through two feedback loops with different propagation delays, to separate and estimate the IQ imbalance errors. In comparison with the previous methods, the greatest advantage of the proposed method is that both compensators of the QM and QDM can be obtained without additional feedback loop, and then the digital predistorter can be designed without the disturbance of IQ imbalance errors. This method can improve the compensation performance of digital predistortion with lower costs and less complexity. Experimental results show the correctness and effectiveness of the proposed method. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2012.     

基于分段线性函数的功放模型及数字预失真应用

为了克服通信系统中功率放大器的非线性和记忆效应,数字预失真技术成为研究的热点。提出一种基于分段线性函数的多项式模型,与广义记忆多项式模型相比,我们把多项式中的高阶项转换为分段求和项,消除了高阶相乘带来的不稳定性,同时由于分段阈值的存在,该模型的适用性和稳定性均有所提高。把功放模型应用于数字预失真结构中的实验结果表明:与广义记忆多项式模型相比,分段线性函数模型所需系数要少40%,邻信道功率比提高约1dB,归一化均方误差提高约8dB,因此该模型在数字预失真方面具有较好的效果。     

Dynamic deviation reduction‐based concurrent dual‐band digital predistortion

This article introduces the concurrent dual‐band digital predistortion (DPD) architecture with only one upconvertion unit, which is suitable for the linearization of wideband power amplifiers (PAs) excited by concurrent dual‐band signals. By extending the conventional dynamic deviation reduction (DDR) model to the concurrent dual‐band mode, we propose two DDR‐based concurrent dual‐band models, the dual‐band DDR (DB‐DDR) model and the simplified dual‐band DDR (SDB‐DDR) model. The performance of these two models is experimentally assessed with two types of wideband PAs (a GaN Class F PA and a GaN Doherty PA) driven by the concurrent dual‐band signal, and compared with the prior two‐dimensional digital predistortion (2D‐DPD) model and the two‐dimensional modified memory polynomial (2D‐MMP) model. The results prove the good DPD performance and low computational complexity of the proposed models. © 2013 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:401–411, 2014.     

One‐bit in‐phase observation for direct learning‐based digital predistortion with modified frequency‐domain delay estimation and alignment

This article proposes a novel digital predistortion (DPD) implementation method for RF power amplifiers. The new approach adopts only one 1‐bit comparator in the feedback path to observe the in‐phase (I) or the quadrature (Q) component of the error signal between the input and the output signals. To this end, the theoretical derivation of the in‐phase observation based on direct learning architecture (DLA) DPD is first given in this article, by combining the existing 1‐bit method and the low‐cost in‐phase observation. To facilitate the delay estimation and alignment, a modified iterative frequency‐domain delay estimation is presented, which only acquires either I or Q components of the output signal to achieve satisfied delay estimation. Experimental results show that the proposed DPD method decreased the normalized mean square error (NMSE) and the adjacent channel power ratio (ACPR) to less than ?42 and ?51 dB, respectively, which indicates that the proposed DPD system can achieve comparable performance as the existing DPD identification techniques with lower implementation complexity.     

Digital techniques to mitigate feedback impairment and noise of look‐up table digital predistortion

In this article, some new effects of feedback impairment and noise on look‐up table (LUT) digital predistortion (DPD) are presented. Several digital techniques are proposed to mitigate these effects. A smoothing filter (SMF) for LUTs is used to eliminate fluctuations of the transfer function of the overall DPD amplification system. By combining SMF method with iterative average (IA) method, the LUTs iterative process becomes stable and well converged. A postcompensator is established according to the proposed two‐box model for feedback impairment. For the demonstration, both simulation and experiments are carried out based on a Hammerstein‐type PA. Simulation results give some preliminary cognition of these new effects and the effectiveness of proposed techniques. Experimental tests are performed on an S‐band amplifier excited with single‐carrier WCDMA signal. The adjacent channel power ratio (ACPR) at 5‐MHz offset is ?48 dBc after DPD with SMF method and postcompensator. A total of 8 dB extra improvement of ACPR is obtained compared with that with neither SMF nor postcompensator. The result clearly shows that the proposed digital techniques are qualified for LUT DPD system, especially when it suffers significant feedback impairment and noise. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011.     

基于反馈迭代的双带功率放大器数字预失真

为补偿双带功率放大器中的非线性,提出了二维多项式模型并结合反馈迭代法建立数字预失真系统。相比于传统的线性化技术,二维数字预失真方法降低了对数/模转换器和模/数转换器的要求。仿真结果表明,采用间隔频率为100 MHz的两路WCDMA信号同时驱动功率放大器,二维多项式模型能够更好地消除非线性失真,反馈迭代方法在求逆上更精确。     

An accurate physical knowledge‐based model for behavioral modeling and digital predistortion of power amplifiers

The objective of this article is to present an accurate model for behavioral modeling and digital predistortion of power amplifiers (PAs) using physical knowledge. Starting with the physically meaningful block model, we present a novel approach to simplify the block model and propose a simplified physical knowledge‐based (SPK) model. The SPK model's performance was experimentally assessed by two types of PAs (a LDMOS Doherty PA and a GaN Doherty PA) and two signals (a single carrier 16QAM signal and a 2‐carrier WCDMA signal). All experimental results prove the superiority of the SPK model. Compared with the 1st‐dynamic deviation reduction (DDR) approach and the 2nd‐simplified DDR approach, the SPK approach achieves average ACPR improvements of 4.4 dB and 2.5 dB, respectively. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE 23: 682–689, 2013.     

An efficient combination of digital predistortion and OFDM clipping for power amplifiers

This article presents a strategy for enhancing efficiency in power amplifiers (PAs) by combining digital predistortion (DPD) linearization and clipping strategies for orthogonal frequency division multiplexing signals in a WiMAX scenario. On the one hand, by reducing the peak‐to‐average power ratio of multicarrier signals using the well‐known clipping technique, it is possible to perform a more efficient PA amplification. On the other hand, nonlinear and linear distortion introduced by the PA operating close to saturation is compensated by the baseband adaptive DPD linearizer. The DPD has to counteract not only the PA nonlinear behavior, but also its dynamics. A test‐bench implementing a WiMAX transmitter was deployed to evaluate the possibilities for enhancing power efficiency while fulfilling the demanded linearity requirements. Experimental results showing the power efficiency and linearity enhancement achieved by the proposed strategy are provided. © 2009 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

Frequency domain data based model extraction for band‐limited digital predistortion of wideband RF power amplifiers

Bandwidth constraints pose significant challenges to linearization of wideband RF power amplifiers (PAs) with digital predistortion (DPD). A recently proposed band‐limited DPD scheme uses a band‐limited modeling technique to eliminate the bandwidth constraints and reduce DPD implementation cost. However, time consuming convolution operations are involved for model extraction in this time domain data based band‐limited modeling method. In this article, band‐limited model extraction is formulated as a generalized least squares problem and investigated from a frequency domain perspective. A frequency domain data based model extraction method is proposed, which greatly reduces the computational complexity for extracting band‐limited DPD model parameters. A 10 W GaN HEMT inverse class‐F PA excited by a 20 MHz four‐carrier WCDMA signal and a 40 MHz two‐carrier LTE signal is tested to validate the method. Experimental results show that the computationally efficient frequency domain data based model extraction method for band‐limited DPD provides as good linearization performance as the time domain data based method. © 2013 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:412–420, 2014.