Static and dynamic transconductance of MOSFETs

A model for the dynamic transconductance of small-channel-length MOSFETs operating in the linear region is presented. The model includes the effects of interface traps and their frequency-dependent admittance, Coulombic scattering due to all charges near the Si-SiO₂ interface, and surface roughness scattering. This model is used to explain the behavior of measured devices that have been subjected to ionizing radiation that introduces charges in the insulator and at the insulator-semiconductor interface. In particular, it is shown that the transconductance peak increases with the frequency of operation. The size of this effect is related mainly to the density of interface traps but is also controlled by the number of trapped charges near the Si-SiO ₂ interface, which increases during irradiation. Static and high-frequency measurements of the transconductance of n-channel MOSFETs are compared with simulated results using the proposed model     

Frequency-dependent electrical characteristics of GaAs MESFETs

Output resistance and transconductance of GaAs MESFETs have been observed to change significantly at very low frequencies. Extensive measurements of these characteristics as a function of device bias are reported. Direct measurements of the dispersive behavior between DC and 100 kHz and over a broad temperature range have been made on ion-implanted monolithic microwave IC (MMIC) devices. Conductance deep level transient spectroscopy (DLTS) and microwave S-parameter measurements have also been made to investigate this behavior. These measurements reveal that surface or channel-substrate interface traps in the material are most likely to be responsible for the observed behavior. A new equivalent-circuit model which accounts for many of the observed characteristics is developed. Unlike previously proposed equivalent circuits, the model does not rely on physically unrealistic circuit element values in order to obtain accurate performance predictions. The bias dependence of circuit element values is computed for one device. Effects not described by the model are also discussed     

On the characterization of surface states and deep traps in GaAs MESFETs

A simple model of frequency-dependent transconductance (g′_m(f)) is developed for characterizing surface states and bulk traps in GaAs metal semiconductor field effect transistors (MESFETs) by considering the occupancy modulation of the surface states and bulk traps. It is shown that the transconductance dispersion provides information for the determination of surface state and bulk trap energy levels. In particular, it is shown that the peak frequency in the transconductance spectrum, dg′_m(f)/df vs f, is equal to the characteristic frequency of a surface state or a bulk trap that is responsible for the peak. Thus, the temperature dependence of the peak frequency facilitates the measurement of the surface state or bulk trap energy level. It is found that peaks due to surface states can be distinguished from those due to bulk traps in the gated channel region by their different dependence of peak heights on the gate-source reverse bias. A comparison of the theoretical results and the available experimental observations shows that the model can successfully explain both the surface leakage current dependence of transconductance dispersion magnitude reported by Ozeki et al. [Inst. Phys. Conf. Ser., No. 63, pp. 323–328 (1982)] and the temperature dependence of transconductance dispersion observed by Blight et al. [IEEE Trans. Electron Devices ED-35, 257–267 (1988)].     

4H-SiC MESFET表面陷阱效应研究

借助ISE TCAD,对4H-SiC MESFET进行二维数值模拟,研究分析了表面陷阱对直流和瞬态特性的影响。数值模拟表明,在直流特性上,由于表面陷阱电荷引入附加耗尽层,器件饱和电流下降,输出电阻增加,夹断电压向右偏移,跨导降低;在瞬态特性上,表面陷阱电荷的缓慢变化引起了栅延迟的出现。能级靠近价带、密度较高时,表面陷阱效应越明显。     

Characterization of the frequency dispersion of transconductance and drain conductance of GaAs MESFET

Frequency dispersions of the transconductance and the drain conductance of ion-implanted gallium arsenide (GaAs) metal-semiconductor field-effect transistors (MESFETs) are measured and analyzed. In the linear region of the MESFET (low drain voltage), a positive transconductance dispersion is observed, which is caused by the deep-level traps at the surface between the source and the gate. In the saturation region (high drain voltage), however, a negative transconductance dispersion becomes dominant. The drain conductance does not show a dispersion in the linear region, while a distinct positive dispersion is observed in the saturation region with the same activation energy as the negative transconductance dispersion. The difference of the dispersion activation energy of the MESFET with and without the p-buried layer beneath the channel indicates that the negative transconductance and the drain conductance dispersion are caused by the deep-level traps at the channel-substrate interface. Because there exists the high electric field at the drain edge of the gate and an electron accumulation layer is formed, the potential in the channel becomes lower when the drain current is larger with high gate voltage. The emission of electrons from electron traps with lower potential is the cause of the negative frequency dispersion.     

Numerical analysis of frequency dispersion of transconductance inGaAs MESFETs

A fully two-dimensional numerical model for the transconductance dispersion in GaAs MESFETs is presented. According to simulated results, the dominating surface traps belong to the hole trap type in order to obtain consistent results with reported measurements. The AC frequency-dependent modulation of negative surface charge can explain this anomalous phenomenon. The holes injecting from and emitting out of the gate metal electrode interact with the surface hole traps, and result in the change of the gate-to-source and the gate-to-drain resistances, which in turn cause the change in transconductance. The gate voltage and the gate length effects on the dispersion are also considered. Good agreement with reported results is obtained     

A comparison of the trap properties and locations within GaAs fieldeffect transistors measured under different bias conditions

The activation energy and capture cross section of traps found in GaAs field effect transistors (GaAs FETs) have been measured with both ohmic channel and current saturation bias using a variety of transient, frequency dispersion, and noise spectroscopy techniques. With current saturation bias these effects have been seen in both the transconductance and the output conductance. The results for all methods and bias conditions are compared with those found by others. The relative sensitivity of the techniques and the location of the traps are discussed     

Investigation of High-Electric-Field Degradation Effects in AlGaN/GaN HEMTs

High-electric-field degradation phenomena are investigated in GaN-capped AlGaN/GaN HEMTs by comparing experimental data with numerical device simulations. Under power- and OFF-state conditions, 150-h DC stresses were carried out. Degradation effects characterizing both stress experiments were as follows: a drop in the dc drain current, the amplification of gate-lag effects, and a decrease in the reverse gate leakage current. Numerical simulations indicate that the simultaneous generation of surface (and/or barrier) and buffer traps can account for all of the aforementioned degradation modes. Experiments also showed that the power-state stress induced a drop in the transconductance at high gate-source voltages only, whereas the OFF-state stress led to a uniform transconductance drop over the entire gate-source-voltage range. This behavior can be reproduced by simulations provided that, under the power-state stress, traps are assumed to accumulate over a wide region extending laterally from the gate edge toward the drain contact, whereas, under the OFF-state stress, trap generation is supposed to take place in a narrower portion of the drain-access region close to the gate edge and to be accompanied by a significant degradation of the channel transport parameters.     

Thermal storage effects on AlGaN/GaN HEMT

The effects of thermal storage on GaN–HEMT devices grown on SiC substrate have been investigated by DC and pulsed electrical measurements, breakdown measurements (by means of a Transmission Line Pulser, TLP), and optical and electron microscopy. After 3000 h of thermal storage testing at 300 °C, only a limited reduction of the DC drain saturation current and of the transconductance peak was observed (20% and 25% decrease, respectively). However, pulsed measurements on aged devices clearly highlight a dramatic current collapse effect that has been attributed to a creation of surface traps in the gate-to-drain and gate-to-source access region. On-state breakdown characterization carried out on aged devices did not highlight any noticeable changes with respect to the untreated devices similarly to the DC characterization. Failure analyses have demonstrated that a loss of adhesion of the passivation layer was responsible for the observed trap formation. An improved passivation deposition process was therefore developed, including a surface cleaning procedure aimed at preventing passivation detaching. The devices fabricated using this new procedure do not show any enhancement of trapping effects up to 500 h of thermal stress at 300 °C.     

Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation

In this paper, electrical behavior of symmetric double gate Ge channel MOSFETs with high-k dielectrics is reported on the basis of carrier concentration formalism. The model relies on the solution of Poisson-Boltzmann equations subject to suitable boundary conditions taking into account the effect of interface trap charge density (D_it) and the Pao-Sah’s current formulation considering field dependent hole mobility. It is continuous as it holds good for sub-threshold, weak and strong inversion regions of device operation. The proposed model has been employed to calculate the drain current of DG MOSFETs for different values of gate voltage and drain voltage along with various important device parameters such as transconductance, output conductance, and transconductance per unit drain current for a wide range of interface trap charge density, equivalent oxide thickness (EOT) and bias conditions. Moreover, most of the important device parameters are compared with their corresponding Si counter parts. Accuracy of the model has been verified by comparing analytical results with the numerical simulation data. A notable improvement of the drive current and transconductance for Ge devices is observed with reference to Si devices, particularly when D_it is small.     

Effect of localized traps on the anomalous behavior of the transconductance in nanocrystalline TFTs

It has been reported that nanocrystalline and microcrystalline devices show an anomalous behavior in the transconductance where several rates of increase of the transconductance with applied gate voltage, not present in amorphous TFTs are observed. In this paper we show that the anomalous effect of the transconductance is observed for an acceptor tail states activation energy similar to the normal values for hydrogenated silicon amorphous devices, (a-Si:H), provided that some conditions are met regarding the density of trapped charge in tail and deep states and the density of free charge in the material, which does not necessarily suggest a behavior in between amorphous and polycrystalline. The effect appears if the density of deep tail states, is smaller (higher) than the typical values in a-Si:H. The localized state distribution present in a nanocrystalline TFT prepared by hot wire deposition technique is estimated by comparison of experimental and simulated transconductance curves. In our case a lower density of deep states is obtained, which corresponds with their better light and bias stability.     

The effect of surface states on the characteristics of MIS field effect transistors

A theoretical model, including the effect of surface trapping and velocity limiting, is developed for the MISFET and is compared with experimental data obtained on depletion mode GaAs anodic oxide devices. It is shown that the results are consistent with a model in which the surface states are inoperative at frequencies in excess of ～10² Hz while at lower frequencies the traps can follow the applied signal leading to a marked reduction in transconductance. The FET data are shown to be entirely consistent with the available C/V data on this semiconductor and suggest that at low frequencies near zero bias the surface potential varies by as little as 18 meV per volt of applied gate bias for the 100 nm of oxide typical of such structures.     

基于陷阱的4H-SiC MESFET频散效应分析

在建立正确模型的基础上,运用ISE软件的二维仿真,模拟了4H-SiC MESFET在交流小信号条件下,表面陷阱和体陷阱对跨导和漏电导随频率变化的影响。分析了产生频散效应的原因以及内部机理,同时考虑了不同环境温度对跨导的频散影响。结果表明,在低频条件下,陷阱会导致跨导和漏电导频散,漏电压越大,环境温度越高,频散越不明显。     

60Co γ-rays irradiation effect in DC performance of AlGaN/GaN high electron mobility transistors

Unpassivated/passivated AlGaN/GaN high electron mobility transistors(HEMTs) were exposed to 1.25MeV60Co γ-rays at a dose of 1 Mrad(Si).The saturation drain current of the unpassivated devices decreased by 15%at 1 Mrad γ-dose,and the maximal transconductance decreased by 9.1% under the same condition;moreover,either forward or reverse gate bias current was significantly increased,while the threshold voltage is relatively unaffected.By sharp contrast,the passivated devices showed scarcely any change in saturation drain current and maximal transconductance at the same γ dose.Based on the differences between the passivated HEMTs and unpassivated HEMTs,adding the C-V measurement results,the obviously parameter degradation of the unpassivated AlGaN/GaN HEMTs is believed to be caused by the creation of electronegative surface state charges in source-gate spacer and gate-drain spacer at the low dose (1 Mrad).These results reveal that the passivation is effective in reducing the effects of surface state charges induced by the 60Co γ-rays irradiation.so the passivation is an effective reinforced approach.     

Effects of SiN passivation and high-electric field on AlGaN-GaN HFET degradation

The authors report on the effects of silicon nitride (SiN) surface passivation and high-electric field stress (hot electron stress) on the degradation of undoped AlGaN-GaN power HFETs. Stressed devices demonstrated a decrease in the drain current and maximum transconductance and an increase in the parasitic drain series resistance, gate leakage, and subthreshold current. The unpassivated devices showed more significant degradation than SiN passivated devices. Gate lag phenomenon was observed from unpassivated devices and removed by SiN passivation. However, SiN passivated devices also showed gate lag phenomena after high-electric field stress, which suggests possible changes in surface trap profiles occurred during high-electric field stress test.     

Radiation-induced depassivation of latent plasma damage

Plasma treatments are widely used in microelectronic industry but they may leave some residual passivated damage in the gate oxides at the end of the processing. The plasma-induced damage can be amplified by metal interconnects (antenna) attached to the gate during the plasma treatments. Ionising radiation reactivates this latent damage, which produces enhanced oxide charge and Si/SiO₂ interface state density. Two CMOS technologies have been investigated, with 5 and 7 nm gate oxides. Threshold voltage shifts, transconductance decrease, and interface traps build-up are always larger for plasma damaged devices than for reference devices.     

Transconductance of Silicon-on-insulator (SOI) MOSFET's

Transconductance of n-channel Silicon-on-Insulator (SOI) MOSFET's has been measured with backside gate (substrate) bias as a parameter. For negative values of the backside gate bias, transconductance of SOI transistors is similar to that of bulk devices. On the other hand, transconductance exhibits an unusual behavior when backside gate is positively biased. This is caused by mutual influence between the front-and the backside gate-related depletion zones. Modeling of transconductance using numerical solution of Poisson's equation show good agreement with experimental results.     

Performance and hot-carrier effects of small CRYO-CMOS devices

The performance characteristics of submicrometer CMOS devices operating at low/cryogenic temperatures (CRYO-CMOS) are determined. The advantages and problems in a CRYO-CMOS technology are experimentally studied in relation to the velocity saturation, source-drain resistances, mobility behavior, carrier freeze-out effects, hot-carrier effects, and circuit performance. The increase of the maximum transconductance at low temperatures (77, 4.2 K) has been confirmed even in the submicrometer channel region. However, improvement of inabilities at a VGnearly equal to 5 V is not so significant in devices with thinner oxides and less so in pMOS devices than in nMOS devices. Excellent subthreshold characteristics have been obtained at low temperatures, making very low-voltage operation possible. One problem found in the threshold control of pMOS transistors is that the boron ions implanted in the surface freeze out, causing unusual subthreshold behavior. Circuit delays have been improved by a factor of 2 to 3, and CRYO-CMOS shows the lowest power-delay product among existing semiconductor technologies with speed performance comparable to bipolar ECL devices. For LDD devices, speed improvements are only slightly smaller than for single-drain devices, while currents and transconductances in the linear regions are limited because of carrier freeze-out of the lightly doped drain. For both channel LDD devices, the transconductance degradations and VTshifts observed under dc stress conditions at 77 K are considered to result from electron injection into spacer oxides.     

Transport properties of AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors with Al2O3 of different thickness

The Al₂O₃ as a gate oxide and passivation was used to study the transport properties of AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors (MOSHFETs). Performance of the devices with Al₂O₃ of different thickness between 4 and 14 nm prepared by metal–organic chemical vapor deposition (MOCVD) and with 4 nm thick Al₂O₃ prepared by Al sputtering and oxidation was investigated. All MOS-devices yielded higher transconductance than their HFET counterparts, i.e. the transconductance/capacitance expected proportionality assuming the same carrier velocity was not fulfilled. A different electric field near/below the gate contact due to a reduction of traps is responsible for the carrier velocity enhancement in the channel of the MOSHFET. The trap reduction depends on the oxide used, as follows from the capacitance vs frequency dispersion for devices investigated. It is qualitatively in a good agreement with the different velocity enhancement evaluated, and devices with thinner oxide show higher traps reduction as well as higher transconductance enhancement. It is also shown that obtained conclusions can be applied well on performance of SiO₂/AlGaN/GaN MOSHFETs.     

Quantum-well p-channel AlGaAs/InGaAs/GaAs heterostructureinsulated-gate field-effect transistors with very high transconductance

Quantum-well p-channel pseudomorphic AlGaAs/InGaAs/GaAs heterostructure insulated-gate field-effect transistors with enhanced hole mobility are described. The devices exhibit room-temperature transconductance, transconductance parameter, and maximum drain current as high as 113 mS/mm, 305 mS/V/mm, and 94 mA/mm, respectively, in 0.8-μm-gate devices. Transconductance, transconductance parameter, and maximum drain current as high as 175 mS/mm, 800 mS/V/mm, and 180 mA/mm, respectively were obtained in 1-μm p-channel devices at 77 K. From the device data hole field-effect mobilities of 860 cm²/V-s at 300 K and 2815 cm²/V-s at 77 K have been deduced. The gate current causes the transconductance to drop (and even to change sign) at large voltage swings. Further improvement of the device characteristics may be obtained by minimizing the gate current. To this end, a type of device structure called the dipole heterostructure insulated-gate field-effect transistor is proposed