Structure and property of magnetron sputtered ternary cobalt-nickel silicide films

Ternary cobalt-nickel silicide films were prepared using magnetron sputtering from an equiatomic cobalt-nickel alloy target on Si substrate. The effect of post-deposition annealing on the phase formation, structural properties and resistivity of the resultant films has been studied. The results of XRD show that the annealing temperature and impurity level of oxygen play a crucial role in controlling the phase transformation of ternary silicide. Silicide phases are absent in the as-deposited film due to the amorphous nature. At relatively low annealing temperature, the phase of CoNi₃Si (2 2 0) and CoNiSi (2 2 0) coexist. With the increase of annealing temperature, the phase of CoNi₃Si (2 2 0) begins to transform into CoNiSi (2 2 0). At high annealing temperature (800 °C), only the phase of CoNiSi₂ (2 2 2) is formed. For Co-Ni silicide film annealed in pure argon gas ambient, two Raman peaks at 1357 cm⁻¹ and 1591 cm⁻¹ are attributed to the vibrational mode of CoSi₂ and NiSi₂ compounds. For ternary silicide annealed in atmosphere ambient, two Raman peaks located at 538 cm⁻¹ and 690 cm⁻¹ were observed and may be related to Si oxide or Co-Ni oxide. The 3D views of AFM images show that the surface roughness is relatively low when the silicidation temperature is smaller than 550 °C. After silicidation in 800 °C, the surface roughness increases abruptly. The resistance initially decreases with the increase of annealing temperature, and achieves minimum value (19 μΩ cm) in temperature ranges 500-550 °C. When the annealing temperature increases from 600 °C to 800 °C, the resistivity was found to increase slightly to 26 μΩ cm. The ternary silicide shows a temperature window for low resistivity as compared to binary NiSi.     

Temperature behavior and modeling of ohmic contacts to Si implanted n-type GaN

The behavior of an ohmic contact to an implanted Si GaN n-well in the temperature range of 25-300 °C has been investigated. This is the sort of contact one would expect in many GaN based devices such as (source/drain) in a metal-oxide-semiconductor transistor. A low resistivity ohmic contact was achieved using the metal combination of Ti (350 Å)/Al (1150 Å) on a protected (SiO₂ cap) and unprotected samples during the post implantation annealing. Sheet resistance of the implanted layer and metal-semiconductor contact resistance to N⁺ GaN have been extracted at different temperatures. Both, the experimental sheet resistance and the contact resistance decrease with the temperature and their characteristics are fitted by means of physical based models.     

Morphology evolution in TiN/Al-0.5Cu/Ti interconnection during chamber long stay and post-deposition annealing correlated to defect formation in metallization processing

TiN/Al-0.5Cu/Ti film stacks deposited on SiO₂ substrate were studied by X-ray diffraction and electron microscopy to clarify the effects of the chamber long stay and post-deposition annealing on the morphology evolution. Experimental results indicated that the chamber idleness at 270 °C resulted in significant Al₂Cu precipitation and hillock growth for the Al-Cu films, which enhanced the occurrence rate of the microcorrosion-induced bridging defects and caused yield degradation on production line while post-deposition annealing at 400 °C for 30 min was proven to effectively regain good yield for the chamber-idled wafers. The yield recovery could be attributed to the fast Al₂Cu dissolution and hillock mitigation at the annealing temperature. The electrical sheet resistance of the Al-Cu films would somewhat increase due to the formation of the Al₃Ti phase during annealing, but the Al₂Cu precipitates and surface hillocks formed during chamber idleness would scarcely change the electrical property of the films. This study suggests that the evolutions of second phase and surface hillocks can be controlled by the processing duration and post-deposition treatment rather than the deposition temperature or Cu addition amount of Al-Cu alloy.     

Thermal stability of Ni silicide films on heavily doped n and p Si substrates

Electrical and structural properties of Ni silicide films formed at various temperatures ranged from 200 °C to 950 °C on both heavily doped n⁺ and p⁺ Si substrates were studied. It was found that surface morphology as well as the sheet resistance properties of the Ni silicide films formed on n⁺ and p⁺ Si substrates at the temperatures higher than 600 °C were very different. Agglomerations of Ni silicide films on n⁺ Si substrates begin to occur at around 600 °C while there is no agglomeration observed in Ni silicide films on p⁺ Si substrates up to a forming temperature of 700 °C. It was also found that the phase transition temperature from NiSi phase to NiSi₂ phase depend on substrate types; 900 °C for NiSi film on n⁺ Si substrate and 750 °C for NiSi film on p⁺ Si substrate, respectively. Our results show that the agglomeration is, especially, important factor in the process temperature dependency of the sheet resistance of Ni silicides formed on n⁺ Si substrates.     

The effect of Si addition and Ta diffusion barrier on growth and thermal stability of NiSi nanolayer

Formation and thermal stability of nanothickness NiSi layer in Ni(Pt 4 at.%)/Si(1 0 0) and Ni_0.6Si_0.4(Pt 4 at.%)/Si(1 0 0) structures have been investigated using magnetron co-sputtering deposition method. Moreover, to study the effect of Si substrate in formation of NiSi and its thermal stability, we have used Ta diffusion barrier between the Ni_0.6Si_0.4 layer and the Si substrate. Post annealing treatment of the samples was performed in an N₂ environment in a temperature range from 200 to 900 °C for 2 min. The samples were analyzed by four point probe sheet resistance (R_s) measurement, X-ray diffraction (XRD) and atomic force microscopy (AFM) techniques. It was found that the annealing process resulted in an agglomeration of the nanothickness Ni(Pt) layer, and consequently, phase formation of discontinuous NiSi grains at the temperatures greater than 700 °C. Instead, for the Ni_0.6Si_0.4(Pt)/Si structure, 100 °C excess temperature in both NiSi formation and agglomeration indicated that it can be considered as a more thermally stable structure as compared with the Ni(Pt 4 at.%)/Si(1 0 0) structure. XRD, AFM and R_s analyses confirmed formation of a continuous NiSi film with R_s value of 5 Ω/□ in a temperature range of 700−800 °C. Use of Ta diffusion barrier showed that the role of diffusion of Ni atoms into the Si substrate is essential in complete silicidation of a NiSi layer.     

Characterisation of titanium disilicide thin films

Properties of TiN/TiSi₂ thin films prepared on phosphorus-doped Si (1 0 0) substrates by sputtering of Ti film followed by a rapid thermal annealing in NH₃ atmosphere at different conditions were studied. Thickness of as-deposited Ti layers was 40 and 60 nm and the annealing duration was set to 10 s at temperatures from 750 to 900 °C. Formation of a compact TiN/TiSi₂/Si structure by rapid thermal annealing has been analysed by Auger electron spectroscopy and time-of-flight secondary ion mass spectroscopy depth profiling. Different amounts of oxygen in TiN layers and phosphorus redistribution in both TiN and TiSi₂ layers have also been detected. Both C54 and C49 TiSi₂ phases were identified by micro-Raman spectroscopy in samples annealed at 750 °C, whereas single C54 phase has been observed in samples annealed at higher temperatures. Creation of TiSi₂ grains of sub-micrometer size at the TiSi₂/Si substrate, explaining the depth dependence of the sheet resistance of silicide layers has been revealed by the scanning electron microscopy.     

Yttrium silicide formation and its contact properties on Si(1 0 0)

Yttrium silicide formation and its contact properties on Si(1 0 0) have been studied in this paper. By evaporating a yttrium metal layer onto Si(1 0 0) wafer in conventional vacuum condition and rapid thermal annealing, we found that YSi_2-x begins to form at 350 °C, and is stable to 950 °C. Atomic force microscopy characterization shows the pinholes formation in the formed YSi_2-x film. By current-voltage measurement, the Schottky barrier height (SBH) of YSi_2-x diode on p-type Si(1 0 0) was shown to be between 0.63 and 0.69 eV for annealing temperature from 500 to 900 °C. By low temperature current-voltage measurement, the SBH of YSi_2-x diode on n-type Si(1 0 0) was directly measured and shown to be 0.46, 0.37, 0.32 eV for annealing temperature of 500, 600, and 900 °C, respectively, and possibly even lower for annealing at 700 or 800 °C.     

Visible photoluminescence from Ge nanoclusters implanted in nanoporous aluminum oxide films

Nanoporous aluminum oxide (Al₂O₃) films with uniform porous size of 45 nm prepared by the electrochemical process in inorganic acid medium were implanted at room temperature (RT) with 120 keV Ge⁺ ions with a fluence of 1.2×10¹⁶ cm⁻². The nucleation and growths of Ge nanoparticles, were obtained by thermal annealing of the implanted samples at the temperature range of 200-600 °C. The size and distribution of the nanoparticles were characterized by photoluminescence (PL) measurements. The photoluminescence measurements as a function of the annealing temperature shows that at low annealing temperature (200 °C), the sample presents a low intensity and broad emission band centered at 5456 Å consistent with emission band characteristics of nanocluster of Ge with diameter in the range of 4-8 nm, as the annealing temperature increases to 400 °C the PL intensity increases by a factor of almost 20 and the emission band suffers a small red shift. The intensity increases can be related to the increase of the number of Ge nanocluster. At the annealing temperature of 600 °C, the emission band is considerably red shifted by almost 172 Å and the emission intensity decreases significantly, strongly suggesting that nanocrystalline Ge having a character of direct optical transitions exhibits the visible photoluminescence.     

Effects of annealing schedule on orientations of Bi3.2Nd0.8Ti3O12 ferroelectric films prepared by metalorganic solution deposition

Fatigue-free Bi_3.2Nd_0.8Ti₃O₁₂ ferroelectric thin films were successfully prepared on p-Si(1 1 1) substrate using metalorganic solution deposition process. The orientation and formation of thin film under different annealing schedules were studied using XRD and AFM. XRD analysis indicated that (2 0 0)-oriented films with degree of orientation of I₍₂₀₀₎/I₍₁₁₇₎ = 2.097 and 0.466 were obtained by preannealing the film at 400 °C for 10 min followed by rapid thermal annealing at 700 °C for 3 min, 10 min and 20 min, respectively, (0 0 8)-oriented film with degree of orientation of I₍₀₀₈₎/I₍₁₁₇₎ = 1.706 were obtained by rapid thermal annealing the film at 700 °C for 3 min without preannealing, and (0 0 8)-oriented film with degree of orientation of I₍₀₀₈₎/I₍₁₁₇₎ = 0.719 were obtained by preheating the film from room temperature to 700 °C at 20 °C/min followed by annealing for 10 min. The a-axis and c-axis orientation decreased as increase in annealing time due to effects of (1 1 1)-oriented substrate. AFM analysis further indicated that preannealing at 400 °C for 10 min followed by rapid thermal annealing at 700 °C for 3 min resulted in formation of platelike crystallite parallel to substrate surface, however rapid thermal annealing at 700 °C for 3 min without preannealing resulted in columnar crystallite perpendicular to substrate surface.     

Fabrication and characterisation of high quality ZnO thin films by reactive electron beam evaporation technique

High quality zinc oxide thin films have been deposited on silicon substrates by reactive e-beam evaporation in an oxygen environment. The effect of the growth temperature and air annealing on the structural, optical and electrical properties has been investigated. X-ray diffraction measurements have shown that ZnO films are highly c-axis-oriented and that the linewidth of the (002) peak is sensitive to the variation of substrate temperature. The optimum growth temperature has been observed at 300 °C. Raman spectroscopy has been found to be an efficient tool to evaluate the residual stress in the as-grown ZnO films from the position of the E₂ (high) mode. On the other hand, the vanishing of the 574 cm⁻¹. Raman feature after annealing has been explained as due to an increase of grain size and the reduction of O-vacancy and Zn interstitial. The SEM images have shown that the surfaces of the electron beam evaporated ZnO became smoother for the growth temperatures higher than 300 °C. The optical transmittance is the highest at 300 °C and has been increased after annealing in air showing an improvement of the optical quality. Finally, the maximum electrical resistivity has been found at 300 °C, which explains its relation with the crystal quality and increased from 5.8×10⁻² Ω cm to reach an approximate value of 10⁹ Ω cm after annealing at 750 °C.     

Suppression of high-resistance phases of Ni silicide by Se passivation of Si(100)

High-resistance phases of Ni-rich Ni silicide are formed on Si(100) below 400/spl deg/C, while high-resistance phases of Si-rich Ni silicide are formed above 600/spl deg/C. The desired low-resistance NiSi is formed between 400/spl deg/C and 600/spl deg/C. In this paper, the authors report the suppression of high-resistance phases of Ni silicide by passivating the Si(100) surface with a monolayer of Se. A 500-/spl Aring/ Ni on n-type low 10/sup 15/ cm/sup -3/ doped Si(100) wafers, passivated with Se, shows a sheet resistance of /spl sim/2.55 /spl Omega//square upon annealing between 200/spl deg/C and 500/spl deg/C, while the sheet resistance of the 500-/spl Aring/ Ni on identical wafers without Se-passivation jumps to /spl sim/7.92 /spl Omega//square between 300/spl deg/C and 350/spl deg/C. Between 600/spl deg/C and 700/spl deg/C, the sheet resistance of the Se-passivated samples is /spl sim/ 10% lower than that of the control samples. Transmission electron microscopy, X-ray diffraction, and X-ray photoelectron spectroscopy all confirm that the suppression of high-resistance Ni silicides below 500/spl deg/C is attributed to the suppression of silicidation and above 600/spl deg/C to the delay in Si-rich Ni silicide formation at the Ni/Se-passivated Si(100) interface.     

Investigation of 4H-SiC MOS capacitors annealed in diluted N2O at different temperatures

Thermally grown oxide on 4H-SiC has been post-annealed in diluted N₂O (10% N₂O in N₂) at different temperatures from 900 to 1100 °C. The quality of the nitrided oxide and the SiO₂/4H-SiC interface was investigated by AC conductance and high frequency C-V measurements based on Al/SiO₂/4H-SiC metal-insulator-semiconductor (MOS) structure. It is found that N₂O annealing at 1000 °C produces the lowest interface state density, though the difference is not so significant when compared to the other samples annealed at 900 and 1100 °C. These results can be explained by the high temperature dynamic decomposition process of N₂O. By fitting the AC conductance data, it is found that higher temperature nitridation increases the capture cross-section of the interface traps.     

RTD characteristics for micro-thermal sensors

The physical and electrical characteristics of MgO (medium layer) and Pt (sensor material) thin films deposited by a reactive RF sputtering method and a magnetron sputtering method, respectively, were analyzed as a function of the annealing temperature and time by using a four-point probe, SEM, and XRD. After being annealed at 1000 °C for 2 h, the MgO layer showed good adhesive properties on both layers (Pt and SiO₂ layers) without any chemical reactions, and the surface resistivity and the resistivity of the Pt thin film were 0.1288 Ω/□ and 12.88 μΩ cm, respectively. Pt resistance patterns were made on MgO/SiO₂/Si substrates by the lift-off method, and Pt resistance thermometer devices (RTDs) for micro-thermal sensor applications were fabricated by using Pt-wire, Pt-paste, and spin-on-glass (SOG). From the Pt RTD samples having a Pt thin film thickness of 1.0 μm, we obtained a temperature coefficient of resistor (TCR) value of 3927 ppm/°C, which is close to the Pt bulk value, and the ratio variation of the resistance value was highly linear in the temperature range of 25-400 °C.     

Effect of a thin W, Pt, Mo, and Zr interlayer on the thermal stability and electrical characteristics of NiSi

It is reported that the thermal stability of NiSi is improved by employing respectively the addition of a thin interlayer metal (W, Pt, Mo, Zr) within the nickel film. The results show that after rapid thermal annealing (RTA) at temperatures ranging from 650 °C to 800 °C, the sheet resistance of formed ternary silicide Ni(M)Si was less than 3 Ω/□, and its value is also lower than that of pure nickel monosilicide. X-ray diffraction (XRD) and raman spectra results both reveal that only the Ni(M)Si phase exists in these samples, but the high resistance NiSi₂ phase does not. Fabricated Ni(M)Si/Si Schottky barrier devices displayed good I-V electrical characteristics, with the barrier height being located generally between 0.65 eV and 0.71 eV, and the reverse breakdown voltage exceeding to 40 V. It shows that four kinds of Ni(M)Si film can be considered as the satisfactory local connection and contact material.     

Interaction of low-temperature surfactant-grown InAs superlattice layers with arsenic precipitates

Double crystal X-ray diffraction (DCXRD), transmission electron microscopy (TEM) and photoluminescence (PL) measurements were used to study the effect of post-growth annealing temperature on the structural properties of novel low growth (250 °C) and normal growth (450 °C) temperature InAs surfactant-mediated grown materials. Under conditions of “arsenic-free” growth, high-quality InAs-GaAs superlattices are obtained at low temperatures (LT) even at thicknesses as high as 3 monolayers (MLs) for InAs. The interaction of the built-in strain fields and the point defects in LT-GaAs both before and after annealing has been studied in detail. DCXRD studies show that the thickness of the LT-grown InAs layers decreased by up to 0.7 ML as the annealing temperature increased to 550 °C. There is evidence from the DCXRD and TEM that the LT InAs-GaAs superlattice structure starts to distort at annealing temperatures above 450 °C. In comparison, the sample grown at normal temperature, 450 °C, still retained the periodicity of the superlattice layers up to an annealing temperature of 650 °C without any change in the thickness of either the InAs (wetting layer) or GaAs.     

Ti and Ti/Sb ohmic contacts on n-type 6H-SiC

Ohmic contacts consisting of Ti and Ti/Sb were prepared on silicon and carbon face of 6H-SiC with different doping densities. Ni contacts were used as reference. All structures were gradually annealed at different temperatures. Specific contact resistance was measured and morphology was monitored after each annealing. It was found that the same metallization has different properties on different 6H-SiC polar faces. Sb addition to Ti contact helped to reach lower values of specific contact resistance on Si-faces of substrates. On C-faces of substrates, pure titanium contacts were comparable or better than Ti/Sb. Annealing at 960 °C and 1065 °C caused contact morphology deterioration and surface spreading of Ti and Ti/Sb contacts. Ni contacts kept good morphology at all annealing temperatures and had the best values of specific contact resistance after annealing at 960 °C and 1065 °C. Using XPS profiling only small amount of free carbon was found in Ti-based contacts.     

Solid phase epitaxial growth of Dy-germanide films on Ge(0 0 1) substrates

Dy thin films are grown on Ge(0 0 1) substrates by molecular beam deposition at room temperature. Subsequently, the Dy film is annealed at different temperatures for the growth of a Dy-germanide film. Structural, morphological and electrical properties of the Dy-germanide film are investigated by in situ reflection high-energy electron diffraction, and ex situ X-ray diffraction, atomic force microscopy and resistivity measurements. Reflection high-energy electron diffraction patterns and X-ray diffraction spectra show that the room temperature growth of the Dy film is disordered and there is a transition at a temperature of 300-330 °C from a disordered to an epitaxial growth of a Dy-germanide film by solid phase epitaxy. The high quality Dy₃Ge₅ film crystalline structure is formed and identified as an orthorhombic phase with smooth surface in the annealing temperature range of 330-550 °C. But at a temperature of 600 °C, the smooth surface of the Dy₃Ge₅ film changes to a rough surface with a lot of pits due to the reactions further.     

High performance n/p and p/n germanium diodes at low-temperature activation annealing

In this work we demonstrate the fabrication and characterization of high performance junction diodes using annealing temperatures within the temperature range of 300-350 °C. The low temperature dopant activation was assisted by a 50 nm platinum layer which transforms into platinum germanide during annealing. The fabricated diodes exhibited high forward currents, in excess of 400 A/cm² at ∼|0.7| V for both p⁺/n and n⁺/p diodes, with forward to reverse ratio I_F/I_R greater than 10⁴. Best results for the n⁺/p junctions were obtained at the lower annealing temperature of 300 °C. These characteristics compare favorably with the results of either conventional or with Ni or Co assisted dopant activation annealing. The low-temperature annealing in combination with the high forward currents at low bias makes this method suitable for high performance/low operating power applications, utilizing thus high mobility germanium substrates.     

n/p ultra-shallow junction formation with plasma immersion ion implantation

n⁺/p ultra-shallow junctions formed by PH₃ plasma immersion ion implantation (PIII) have been studied and diodes with good electrical characteristics have been obtained. The influence of annealing conditions and carrier gas on junction depth and sheet resistance have been studied. It is found that a higher content of H and/or He in silicon can slow down the diffusion of phosphorus and the activation ability of implanted dopant ions in silicon; a shallower junction can been obtained with He rather than H₂ as the carrier gas; and the influence of annealing at 850°C for 20 s on sheet resistance is opposite to that of annealing at 900°C for 6 s on sheet resistance. In addition, mechanisms of unusual electrical characteristics for some diodes are discussed and analyzed in this paper.     

Study of deep level defect behavior in undoped n-InP (1 0 0) after rapid thermal annealing

The effects of rapid thermal annealing on deep level defects in the undoped n-type InP with Ru as Schottky contact metal have been characterized using deep level transient spectroscopy (DLTS). It is observed that the as-deposited sample exhibit two deep levels with activation energies of 0.66 and 0.89 eV. For the samples annealed at 300 °C and 400 °C, a deep level is identified with activation energies 0.89 and 0.70 eV, respectively below the conduction band. When the sample is annealed at 500 °C, three deep levels are observed with activation energies 0.25, 0.32 and 0.66 eV. Annealing of the sample at 300 °C, orders the lattice of as-grown material by suppressing the defect 0.66 eV (A1) which is found in the as-deposited sample. The trap concentration of the 0.89 eV deep levels is found to be increased with annealing temperature. The deep level 0.32 eV may be due to the lattice defect by thermal damage during rapid thermal annealing process such as vacancies, interstitials and its complexes, indicating the damage of the sample after annealing at 500 °C. The defects observed in all the samples are possibly due to the creation of phosphorous vacancy or phosphorous antisite.