Characterization of current-voltage (I-V) and capacitance-voltage-frequency (C-V-f) features of Al/SiO2/p-Si (MIS) Schottky diodes

The current-voltage (I-V) characteristics of metal-insulator-semiconductor Al/SiO₂/p-Si (MIS) Schottky diodes were measured at room temperature (300 K). In addition, capacitance-voltage-frequency (C-V-f) characteristics are investigated by considering the interface states (N_ss) at frequency range 100 kHz to 1 MHz. The MIS Schottky diode having interfacial insulator layer thickness of 33 Å, calculated from the measurement of the insulator capacitance in the strong accumulation region. At each frequency, the measured capacitance decreases with increasing frequency due to a continuous distribution of the interface states. From the I-V characteristics of the MIS Schottky diode, ideality factor (n) and barrier height (Φ_b) values of 1.766 and 0.786 eV, respectively, were obtained from a forward bias I-V plot. In addition, the interface states distribution profile as a function of (E_ss − E_v) was extracted from the forward bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_e) for the Schottky diode. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. This behaviour is attributed to the interfacial insulator layer, the interface states and barrier inhomogeneity of the device. As expected, the C-V curves gave a barrier height value higher than those obtained from I-V measurements. This discrepancy is due to the different nature of the I-V and C-V measurement techniques.     

Analysis of interface states and series resistance of MIS Schottky diodes using the current-voltage (I-V) characteristics

The purpose of this paper is to analyze interface states in Al/SiO₂/p-Si (MIS) Schottky diodes and determine the effect of SiO₂ surface preparation on the interface state energy distribution. The current-voltage (I-V) characteristics of MIS Schottky diodes were measured at room temperature. From the I-V characteristics of the MIS Schottky diode, ideality factor (n) and barrier height (Φ_B) values of 1.537 and 0.763 eV, respectively, were obtained from a forward bias I-V plot. In addition, the density of interface states (N_ss) as a function of (E_ss-E_v) was extracted from the forward bias I-V measurements by taking into account both the bias dependence of the effective barrier height (Φ_e), n and R_s for the MIS Schottky diode. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. In addition, the values of series resistance (R_s) were determined using Cheung’s method. The I-V characteristics confirmed that the distribution of N_ss, R_s and interfacial insulator layer are important parameters that influence the electrical characteristics of MIS Schottky diodes.     

The C-V-f and G/ω-V-f characteristics of Al/SiO2/p-Si (MIS) structures

The frequency dependence of capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of the Al/SiO₂/p-Si metal-insulator-semiconductor (MIS) structures has been investigated taking into account the effect of the series resistance (R_s) and interface states (N_ss) at room temperature. The C-V and G/ω-V measurements have been carried out in the frequency range of 1 kHz to 1 MHz. The frequency dispersion in capacitance and conductance can be interpreted only in terms of interface states and series resistance. The N_ss can follow the ac signal and yield an excess capacitance especially at low frequencies. In low frequencies, the values of measured C and G/ω decrease in depletion and accumulation regions with increasing frequencies due to a continuous density distribution of interface states. The C-V plots exhibit anomalous peaks due to the N_ss and R_s effect. It has been experimentally determined that the peak positions in the C-V plot shift towards lower voltages and the peak value of the capacitance decreases with increasing frequency. The effect of series resistance on the capacitance is found appreciable at higher frequencies due to the interface state capacitance decreasing with increasing frequency. In addition, the high-frequency capacitance (C_m) and conductance (G_m/ω) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance. Experimental results show that the locations of N_ss and R_s have a significant effect on electrical characteristics of MIS structures.     

On the profile of frequency dependent series resistance and dielectric constant in MIS structure

In this study, the frequency dependent of the forward and reverse bias capacitance-voltage (C-V) and conductance-voltage (G/ω - V) measurements of Al/SiO₂/p-Si (MIS) structures are carried out in frequency range of 10 kHz-10 MHz. The frequency dependence of series resistance (R_s), density of surface states (N_ss), dielectric constant (ε′), dielectric loss (ε″), dielectric loss tangent (tan δ) and the ac electrical conductivity (σ_dc) are studied for these structure at room temperature. Experimental results show that both electrical and dielectric parameters were strongly frequency and voltage dependent. The ε′ and ε″ are found to decrease with increasing frequency while σ_ac is increased. Also, both the effects of surface states N_ss and R_s on C-V and G/ω - V characteristics are investigated. It has been seen that the measured C and G decrease with increasing frequency due to a continuous distribution of N_ss in frequency range of 10 kHz-1 MHz. The effect of R_s on the C and G are found noticeable at high frequencies. Therefore, the high frequencies C and G values measured under both reverse and forward bias were corrected for the effect of series resistance R_s to obtain real MIS capacitance C_c and conductance G_c using the Nicollian and Goetzberger technique. The distribution profile of R_s-V gives a peak in the depletion region at low frequencies and disappears with increasing frequencies.     

On the energy distribution of interface states and their relaxation time and capture cross section profiles in Al/SiO2/p-Si (MIS) Schottky diodes

The energy distribution profile of the interface states (N_ss) and their relaxation time (τ) and capture cross section (σ_p) of metal-insulator-semiconductor (Al/SiO₂/p-Si) Schottky diodes have been investigated by using the high-low frequency capacitance and conductance methods. The capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of these devices were investigated by considering series resistance (R_s) effects in a wide frequency range (5 kHz-1 MHz.). It is shown that the capacitance of the Al/SiO₂/p-Si Schottky diode decreases with increasing frequency. The increase in capacitance especially at low frequencies results form the presence of interface states at Si/SiO₂ interface. The energy distributions of the interface states and their relaxation time have been determined in the energy range of (0.362-E_v)-(0.512-E_v) eV by taking into account the surface potential as a function of applied bias obtained from the measurable C-V curve (500 Hz) at the lowest frequency. The values of the interface state density (N_ss) ranges from 2.34 × 10¹² to 2.91 ×  10¹² eV⁻¹/cm², and the relaxation time (τ) ranges from 1.05 × 10⁻⁶ to 1.58 × 10⁻⁴ s, showing an exponential rise with bias from the top of the valance band towards the mid-gap.     

Effect of series resistance on the electrical characteristics and interface state energy distributions of Sn/p-Si (MS) Schottky diodes

In this study, electrical characteristics of the Sn/p-type Si (MS) Schottky diodes have been investigated by current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height obtained from C-V measurement is higher than obtained from I-V measurement and this discrepancy can be explained by introducing a spatial distribution of barrier heights due to barrier height inhomogeneities, which are available at the nanostructure Sn/p-Si interface. A modified Norde’s function combined with conventional forward I-V method was used to extract the parameters including barrier height (Φ_b) and the series resistance (R_S). The barrier height and series resistance obtained from Norde’s function was compared with those from Cheung functions. In addition, the interface-state density (N_SS) as a function of energy distribution (E_SS-E_V) was extracted from the forward-bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_b) and series resistance (R_S) for the Schottky diodes. While the interface-state density (N_SS) calculated without taking into account series resistance (R_S) has increased exponentially with bias from 4.235 × 10¹² cm⁻²eV⁻¹ in (E_SS - 0.62) eV to 2.371 × 10¹³ cm⁻²eV⁻¹ in (E_SS - 0.39) eV of p-Si, the N_SS obtained taking into account the series resistance has increased exponentially with bias from of 4.235 × 10¹² to 1.671 × 10¹³ cm⁻²eV⁻¹ in the same interval. This behaviour is attributed to the passivation of the p-doped Si surface with the presence of thin interfacial insulator layer between the metal and semiconductor.     

Calculation from the current-voltage and capacitance-voltage measurements of characteristics parameters of Cd/CdS/n-Si/Au-Sb structure with CdS interface layer grown on n-Si substrate by SILAR method

The CdS thin film has been directly formed on n-type Si substrate to form an interfacial layer between cadmium (Cd) and n-type Si with Successive Ionic Layer Adsorption and Reaction (SILAR) method. An Au-Sb electrode has been used as an ohmic contact. The Cd/CdS/n-Si/Au-Sb structure has demonstrated clearly rectifying behaviour by the current-voltage (I-V) curves studied at room temperature. The characteristics parameters such as barrier height, ideality factor and series resistance of Cd/CdS/n-Si/Au-Sb structure have been calculated from the forward bias I-V and reverse bias C⁻²-V characteristics. The diode ideality factor and the barrier height have been calculated as n = 2.06 and Φ_b = 0.92 eV by applying a thermionic emission theory, respectively. The diode shows non-ideal I-V behaviour with an ideality factor greater than unity that can be ascribed to the interfacial layer, the interface states and the series resistance. At high current densities in the forward direction, the series resistance (R_s) effect has been observed. The values of R_s obtained from dV/d(lnI)-I and H(I)-I plots are near to each others (R_s = 182.24 Ω and R_s = 186.04 Ω, respectively). This case shows the consistency of the Cheung′s approach. In the same way, the barrier height calculated from C⁻² -V characteristics varied from 0.698 to 0.743 eV. Furthermore, the density distribution of interface states (N_ss) of the device has been obtained from the forward bias I-V characteristics. It has been seen that, the N_ss has almost an exponential rise with bias from the mid gap toward the bottom of conduction band.     

Electrical parameters of a DC sputtered Mo/n-type 6H-SiC Schottky barrier diode

A Mo/n-type 6H-SiC/Ni Schottky barrier diode (SBD) was fabricated by sputtering Mo metal on n-type 6H-SiC semiconductor. Before the formation of Mo/n-type 6H-SiC SBD, an ohmic contact was formed by thermal evaporation of Ni on n-type 6H-SiC and annealing at 950 °C for 10 min. It was seen that the structure had excellent rectification. The electrical parameters were extracted using its current–voltage (I–V) and capacitance–voltage (C–V) measurements carried out at room temperature. Very high (1.10 eV) barrier height and 1.635 ideality factor values were reported for Mo/n-type 6H-SiC using ln I–V plot. The barrier height and series resistance values of the diode were also calculated as 1.413 eV and 69 Ω from Norde׳s functions, respectively. Furthermore, 1.938 eV barrier height value of Mo/n-type 6H-SiC SBD calculated from C–V measurements was larger than the one obtained from I–V data.     

Current–voltage and capacitance–voltage characteristics of Al Schottky contacts to strained Si-on-insulator in the wide temperature range

The electrical characteristics of Al/strained Si-on-insulator (sSOI) Schottky diode have been investigated using current–voltage (I–V) and capacitance–voltage (C–V) measurements in the wide temperature range of 200–400 K in steps of 25 K. It was found that the barrier height (0.57–0.80 eV) calculated from the I–V characteristics increased and the ideality factor (1.97–1.28) decreased with increasing temperature. The barrier heights determined from the C–V measurements were higher than those extracted from the I–V measurements, associated with the formation of an inhomogeneous Schottky barrier at the interface. The series resistance estimated from the forward I–V characteristics using Cheung and Norde methods decreased with increasing temperature, implying its strong temperature dependence. The observed variation in barrier height and ideality factor could be attributed to the inhomogeneities in Schottky barrier, explained by assuming Gaussian distribution of barrier heights. The temperature-dependent I–V characteristics showed a double Gaussian distribution with mean barrier heights of 0.83 and 1.19 eV and standard deviations of 0.10 and 0.16 eV at 200–275 and 300–400 K, respectively. From the modified Richardson plot, the modified Richardson constant were calculated to be 21.8 and 29.4 A cm⁻² K⁻² at 200–275 and 300–400 K, respectively, which were comparable to the theoretical value for p-type sSOI (31.6 A cm⁻² K⁻²).     

On the profile of frequency dependent series resistance and surface states in Au/Bi4Ti3O12/SiO2/n-Si(MFIS) structures

The frequency dependent capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of the metal-ferroelectric-insulator-semiconductor (Au/Bi₄Ti₃O₁₂/SiO₂/n-Si) structures (MFIS) were investigated by considering series resistance (R_s) and surface state effects in the frequency range of 1 kHz-5 MHz. The experimental C-V-f and G/ω-V-f characteristics of MFIS structures show fairly large frequency dispersion especially at low frequencies due to R_s and N_ss. In addition, the high frequency capacitance (C_m) and conductance (G_m/ω) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real capacitance of MFIS structures. The R_s-V plots exhibit anomalous peaks between inversion and depletion regions at each frequency and peak positions shift towards positive bias with increasing frequency. The C⁻²-V plot gives a straight line in wide voltage region, indicating that interface states and inversion layer charge cannot follow the ac signal in the depletion region, but especially in the strong inversion and accumulation region. Also, it has been shown that the surface state density decreases exponentially with increasing frequency. The C-V-f and G/w-V-f characteristics confirm that the interface state density (N_ss) and series resistance (R_s) of the MFIS structures are important parameters that strongly influence the electrical properties of MFIS structures.     

Schottky diode performance of an Au/Pd/GaAs device fabricated by deposition of monodisperse palladium nanoparticles over a p-type GaAs substrate

Au/Pd/p-GaAs Schottky diodes were fabricated by simple assembly of monodisperse Pd nanoparticles on a p-type GaAs semiconductor. Monodisperse 5-nm Pd nanoparticles were synthesized via reduction of palladium(II) acetylacetonate in oleylamine using a borane tert-butylamine complex. The Au/Pd/p-GaAs Schottky diodes provided a barrier height of 0.68 eV, which is higher than room-temperature values reported in the literature. A double distribution was observed for the barrier height for the Schottky diodes from I–V–T measurements. A decrease in temperature lowered the zero-bias barrier height and increased the ideality factor. These observations were ascribed to barrier height inhomogeneities at the interface that altered the barrier height distribution. Values of the series resistance obtained by the Norde method decreased with increasing temperature. Understanding the temperature dependence of the current–voltage characteristics of Au/Pd/p-GaAs devices might be helpful in improving the quality of Pd deposited on GaAs for future device technologies.     

Temperature dependent current-voltage characteristics of the Zn/ZnO/n-Si/Au-Sb structure with ZnO interface layer grown on n-Si substrate by SILAR method

This is the first time; it was employed Successive Ionic Layer Adsorption and Reaction (SILAR) method in order to prepare Zn/ZnO/n-Si/Au-Sb sandwich structure. The ZnO interface layer was directly formed on n-type Si substrate using SILAR method. The X-ray diffraction (XRD) and scanning electron microscopy (SEM) studies were showed that the film is covered well on n-type Si substrate and have polycrystalline structure. An Au-Sb electrode was used as an ohmic contact. The Zn/ZnO/n-Si/Au-Sb sandwich structure demonstrated clearly rectifying behavior by the current-voltage (I-V) curves studied at room temperature. The sample temperature effect on the current-voltage (I-V) characteristics of Zn/ZnO/n-Si/Au-Sb structure was investigated in temperature range 80-320 K by steps of 20 K. The parameters such as barrier height, ideality factor and series resistance of this structure were calculated from the forward bias I-V characteristics as a function of sample temperature. It was seen that the ideality factor and series resistance were decreased; the barrier height were increased with increasing temperature. The experimental values of barrier height and ideality factor for this device were calculated as 0.808 eV and 1.519 at 320 K; 0.220 eV and 4.961 at 80 K, respectively. These abnormal behaviors can be explained by the barrier inhomogeneities at the metal-semiconductor (M-S) interface.     

Formation of PNx/lnP structure byIn Situ remote plasma processes

In situ remote plasma processes consisting of removal of native oxide due to hydrogen (H₂) plasma, surface modification due to phosphine (PH₃) plasma and deposition of phosphorus nitride (PN_x) films due to decomposition of PH₃ by nitrogen (N₂) plasma have been developed. The insulating PN_x film with optical bandgap of 5.3 eV and electrical resistivity of 3.7× 10¹⁴ Ωcm is obtained by remote plasma chemical vapor deposition. Au/PN_x/InP tunneling metal-insulator-semiconductor (MIS) type Schottky junction is formed by thein situ multiprocess. The effective barrier height is estimated to be as high as 0.83 eV. Enhancement of the effective barrier height is due to both effects of the MIS structure and unpinning of the surface Fermi level.     

On the temperature dependence of series resistance and interface states in Al/SiO2/p-Si (MIS) Schottky diodes

The capacitance-voltage-temperature (C-V-T) and conductance-voltage-temperature (G/w-V-T) characteristics of metal-semiconductor (Al/p-Si) Schottky diodes with thermal growth interfacial layer were investigated by considering series resistance effect in the wide temperature range (80-400 K). It is found that in the presence of series resistance, the forward bias C-V plots exhibit a peak, and experimentally shows that the peak positions shift towards higher positive voltages with increasing temperature, and the peak value of the capacitance has a maximum at 80 K. The C-V and (G/w-V) characteristics confirm that the N_ss and R_s of the diode are important parameters that strongly influence the electric parameters in (Al/SiO₂/p-Si) MIS Schottky diodes. The crossing of the G/w-V curves appears as an abnormality when seen with respect to the conventional behaviour of the ideal MS or MIS Schottky diode. It is thought that the presence of a series resistance keeps this intersection hidden and unobservable in homogeneous Schottky diodes, but it appears in the case of inhomogeneous Schottky diode. In addition, the high frequency (C_m) and conductance (G_m/w) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance.     

Electrical characteristics and inhomogeneous barrier analysis of Au-Be/p-InSe:Cd Schottky barrier diodes

We have identically prepared Au-Be/p-InSe:Cd Schottky barrier diodes (SBDs) (21 dots) on the InSe:Cd substrate. The electrical analysis of Au-Be/p-InSe:Cd structure has been investigated by means of current-voltage (I-V), capacitance-voltage (C-V) and capacitance-frequency (C-f) measurements at 296 K temperature in dark conditions. The effective barrier heights and ideality factors of identically fabricated Au-Be/p-InSe:Cd SBDs have been calculated from their experimental forward bias current-voltage (I-V) characteristics by applying a thermionic emission theory. The BH values obtained from the I-V characteristics have varied between 0.74 eV and 0.82 eV with values of ideality factors ranging between 1.49 and 1.11 for the Au-Be/p-InSe:Cd SBDs. It has been determined a lateral homogeneous barrier height value of approximately 0.82 eV for these structures from the experimental linear relationship between barrier heights and ideality factors. The Schottky barrier height (SBH) value has been obtained from the reverse-bias C-V characteristics of Au-Be/p-InSe:Cd SBD for only one diode. At high currents in the forward direction, the series resistance effect has been observed. The value of series resistance has been determined from I-V measurements using Cheung’s and Norde’s methods.     

对MIS结构热弛豫时间的分析计算

对MIS（金属?绝缘层?半导体）结构从深耗尽过渡至强反型状态所需的热弛豫时间进行了研究。通过建立较教科书更精确的模型,对热弛豫时间τth与深耗尽时耗尽区宽度xd0、强反型时耗尽区最大宽度xdm、耗尽区内少子净产生率G和掺杂浓度ND等关键物理量之间的关联进行了推导,并基于MEDICI平台对推导结果完成了仿真验证,从而加强了学生对半导体表面效应的理解,也利于他们未来从事半导体方面的创新研究。     

雷达频率源的相位噪声对改善因子限制的频域分析

本文从频域研究了频率源的相位噪声对相参雷达改善因子的限制，给出了矩形脉冲和线性调频脉脉冲雷达接收机视频信号中相位噪声谱密度的计算公式，并导出了它们对改善因子限制的结果，证明了频域和时域所得的对改善因子限制的公式是一样的。     

Frequency and gate voltage effects on the dielectric properties of Au/SiO2/n-Si structures

To determine the dielectric constant (ε′), dielectric loss (ε″), loss tangent (tan δ), the ac electrical conductivity (σ_ac) and the electric modulus of Au/SiO₂/n-Si structure, the measurement admittance technique was used. Experimental results show that the values of ε′, ε″, tan δ, σ_ac and the electric modulus show fairly large frequency and gate bias dispersion especially at low frequencies due to the interface charges and polarization. An increase in the values of the ε′ and ε″ were observed with both a decrease in frequency and an increase in frequency. The σ_ac is found to increase with both increasing frequency and voltage. In addition, the experimental dielectrical data have been analyzed considering electric modulus formalism. It can be concluded that the interface charges and interfacial polarization have strong influence on the dielectric properties of metal-insulator-semiconductor (MIS) structures especially at low frequencies and both in depletion and accumulation regions.     

The characterization of a proposed model GaAs/anodic oxide interface

The n-GaAs/anodic oxide interface has been characterized using capacitance-voltage (C-V) measurements on MOS capacitors and current-voltage (I-V) measurements on Schottky barriers. A simple interface state model cannot explain the observed behavior. Schottky barrier measurements made on surfaces which were previously anodized with the oxide layer subsequently removed by etching show evidence for the presence of a compensated layer in the anodized semiconductor surface region. This leads to a maximum in the conduction band energy near the surface, and based on these observations a quantitative model is formulated which can partially explain some aspects of the GaAs/anodic oxide interface, including the accumulation mode capacitance dispersion observed by many authors. Further studies were made in which the oxides were grown to difference thickness and then etched to the same thickness. Measurements on these oxides show that the C-V dispersion is related to the current density during growth and to the thickness of the oxide. There is also a correlation between the temperature during oxide growth and the interface properties. Oxides grown at 65°C show significantly more dispersion than oxides grown at 0°C. The temperature during anodization is also found to influence the anodization constant. This work was supported by a research grant (ENG-76-81334) from the National Science Foundation, Washington, DC.     

Temperature dependent electrical and dielectric properties of a metal/Dy2O3/n-GaAs (MOS) structure

This paper describes the structural properties, electrical and dielectric characteristics of thin Dy₂O₃ layer deposited on the n-GaAs substrate by electron beam deposition under ultra vacuum. Structural and morphological characterizations are investigated by atomic force microscopy (AFM) and X-ray diffraction measurements (XRD). The XRD shows that the elaborated Dy₂O₃ oxide has a cubic structure. The electrical and dielectric properties of Co/Au/Dy₂O₃/n-GaAs structure were studied in the temperature range of 80–500 K. The conductance and capacitance measurements were performed as a function of bias voltage and frequency. The dielectric constant (ε′), dielectric loss (ε″) and dielectric loss tangent (tanδ) of the structure are obtained from capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements. These parameters are found to be strong functions of temperature and bias voltage. A strong negative capacitance (NC) phenomenon has been observed in C–V; hence ε′–V plots for each temperature value take negative values. The following behavior of the C and ε′ in the forward bias region has been explained with the minority-carrier injection and relaxation theory. From DC conductance study, electronic conduction is found to be dominated by thermally activated hopping at high temperature. Activation energy is deduced from the variation of conductance with temperature. The interface state density (N_ss) of the structure is of the order 1.13×10¹³ eV⁻¹ cm⁻².